| commit | 345f84227b50e90329dd303499024603596566f4 | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Wed Apr 29 14:14:35 2009 -0400 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Tue May 19 00:50:23 2009 -0500 |
| tree | 609868e873f374aacdbb58a37db8de4517bf4d8e | |
| parent | 06c4435021f4856261edd01e2691071edeb8fa51 [diff] |
net/ucc_geth: update riscTx and riscRx in ucc_geth Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>