tree 090e7de8dfc9c94f35ecf0267747b72ab5c71756
parent 66ef3493d4bb387f5a83915e33dc893102fd1b43
author Andy Shevchenko <andriy.shevchenko@linux.intel.com> 1444319786 +0300
committer Thomas Gleixner <tglx@linutronix.de> 1446889050 +0100

x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

The Intel Merrifield SoC is a successor of the Intel MID line of
SoCs. Let's set the neccessary capability for that chip. See commit
c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3)
for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: http://lkml.kernel.org/r/1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>