tree dbf312bceb367cfd6dd0b3ad3c201879afe128f9
parent c7788792a5e7b0d5d7f96d0766b4cb6112d47d75
author Soren Brinkmann <soren.brinkmann@xilinx.com> 1368467196 -0700
committer Michal Simek <michal.simek@xilinx.com> 1369146095 +0200

clk: zynq: Factor out PLL driver

Refactor the PLL driver so it works with the clock controller driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>