drm/nouveau/mspdec: separate from vp
Switch to NVIDIA's name for the device.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 157f59a..5ad17fc 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -136,6 +136,7 @@
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
__u64 disable; /* disable particular subsystems */
__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
};
@@ -348,7 +349,7 @@
struct kepler_channel_gpfifo_a_v0 {
__u8 version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index ddc3d5d..2b90ec9 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -61,6 +61,7 @@
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
+ NVDEV_ENGINE_MSPDEC,
NVDEV_SUBDEV_NR,
};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
new file mode 100644
index 0000000..2457f87
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
@@ -0,0 +1,6 @@
+#ifndef __NVKM_MSPDEC_H__
+#define __NVKM_MSPDEC_H__
+extern struct nouveau_oclass nv98_mspdec_oclass;
+extern struct nouveau_oclass nvc0_mspdec_oclass;
+extern struct nouveau_oclass nve0_mspdec_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
index 39baebe..7175e6e0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
@@ -1,9 +1,4 @@
#ifndef __NOUVEAU_VP_H__
#define __NOUVEAU_VP_H__
-
extern struct nouveau_oclass nv84_vp_oclass;
-extern struct nouveau_oclass nv98_vp_oclass;
-extern struct nouveau_oclass nvc0_vp_oclass;
-extern struct nouveau_oclass nve0_vp_oclass;
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index bc51b05..6bd3d75 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -2,17 +2,18 @@
nvkm-y += nvkm/engine/xtensa.o
include $(src)/nvkm/engine/bsp/Kbuild
-include $(src)/nvkm/engine/cipher/Kbuild
include $(src)/nvkm/engine/ce/Kbuild
+include $(src)/nvkm/engine/cipher/Kbuild
include $(src)/nvkm/engine/device/Kbuild
include $(src)/nvkm/engine/disp/Kbuild
include $(src)/nvkm/engine/dmaobj/Kbuild
include $(src)/nvkm/engine/fifo/Kbuild
include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
+include $(src)/nvkm/engine/mspdec/Kbuild
+include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/pm/Kbuild
-include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/sw/Kbuild
include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 55e4633..915ba95 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -51,7 +51,7 @@
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
@@ -95,7 +95,7 @@
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
@@ -138,7 +138,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 13203f5..4f100b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -51,6 +51,7 @@
#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
@@ -253,7 +254,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -311,7 +312,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -340,7 +341,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
@@ -371,7 +372,7 @@
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -401,7 +402,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -431,7 +432,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
@@ -461,7 +462,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index ae856f8..2a6fc7f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -47,7 +47,7 @@
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/msppp.h>
@@ -84,7 +84,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -117,7 +117,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -150,7 +150,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -182,7 +182,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -215,7 +215,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -247,7 +247,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -279,7 +279,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -312,7 +312,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
@@ -342,7 +342,7 @@
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 13934f2..b2225ec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -51,7 +51,7 @@
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
@@ -89,7 +89,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -123,7 +123,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -157,7 +157,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
@@ -213,7 +213,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -247,7 +247,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
@@ -281,7 +281,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
case 0x108:
@@ -314,7 +314,7 @@
device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
+ device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 6abcd5c..727358d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -57,7 +57,8 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0020; break;
- case NVDEV_ENGINE_VP : addr = 0x0040; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
@@ -95,7 +96,8 @@
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
- case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
@@ -148,7 +150,8 @@
case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
- case NVDEV_ENGINE_VP : context |= 0x00400000; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break;
case NVDEV_ENGINE_CIPHER:
case NVDEV_ENGINE_SEC :
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
@@ -195,6 +198,7 @@
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
@@ -270,6 +274,7 @@
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index d86601c..6e05b0b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -120,13 +120,13 @@
int ret;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
- case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -157,13 +157,13 @@
u32 addr;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
- case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
+ case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -215,7 +215,7 @@
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_VP) |
+ (1ULL << NVDEV_ENGINE_MSPDEC) |
(1ULL << NVDEV_ENGINE_MSPPP), &chan);
*pobject = nv_object(chan);
if (ret)
@@ -381,12 +381,12 @@
nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
{
switch (engn) {
- case NVDEV_ENGINE_GR : engn = 0; break;
- case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_MSPPP: engn = 2; break;
- case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_CE0 : engn = 4; break;
- case NVDEV_ENGINE_CE1 : engn = 5; break;
+ case NVDEV_ENGINE_GR : engn = 0; break;
+ case NVDEV_ENGINE_MSVLD : engn = 1; break;
+ case NVDEV_ENGINE_MSPPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPDEC: engn = 3; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
@@ -401,7 +401,7 @@
case 0: engn = NVDEV_ENGINE_GR; break;
case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_MSPPP; break;
- case 3: engn = NVDEV_ENGINE_VP; break;
+ case 3: engn = NVDEV_ENGINE_MSPDEC; break;
case 4: engn = NVDEV_ENGINE_CE0; break;
case 5: engn = NVDEV_ENGINE_CE1; break;
default:
@@ -551,7 +551,7 @@
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PCOUNTER" },
- { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
+ { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PDAEMON" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index ea31e2d..f5965eb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -48,7 +48,7 @@
} fifo_engine[] = {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_CE2)),
- _(NVDEV_ENGINE_VP , 0),
+ _(NVDEV_ENGINE_MSPDEC , 0),
_(NVDEV_ENGINE_MSPPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
@@ -148,10 +148,10 @@
case NVDEV_ENGINE_CE2:
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
return 0;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -182,14 +182,14 @@
u32 addr;
switch (nv_engidx(object->engine)) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_CE0 :
- case NVDEV_ENGINE_CE1 :
- case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
- case NVDEV_ENGINE_GR : addr = 0x0210; break;
- case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
- case NVDEV_ENGINE_VP : addr = 0x0250; break;
- case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
+ case NVDEV_ENGINE_SW : return 0;
+ case NVDEV_ENGINE_CE0 :
+ case NVDEV_ENGINE_CE1 :
+ case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
+ case NVDEV_ENGINE_GR : addr = 0x0210; break;
+ case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
+ case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
+ case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
default:
return -EINVAL;
}
@@ -414,14 +414,14 @@
nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
{
switch (engn) {
- case NVDEV_ENGINE_GR :
- case NVDEV_ENGINE_CE2 : engn = 0; break;
- case NVDEV_ENGINE_MSVLD: engn = 1; break;
- case NVDEV_ENGINE_MSPPP: engn = 2; break;
- case NVDEV_ENGINE_VP : engn = 3; break;
- case NVDEV_ENGINE_CE0 : engn = 4; break;
- case NVDEV_ENGINE_CE1 : engn = 5; break;
- case NVDEV_ENGINE_MSENC: engn = 6; break;
+ case NVDEV_ENGINE_GR :
+ case NVDEV_ENGINE_CE2 : engn = 0; break;
+ case NVDEV_ENGINE_MSVLD : engn = 1; break;
+ case NVDEV_ENGINE_MSPPP : engn = 2; break;
+ case NVDEV_ENGINE_MSPDEC: engn = 3; break;
+ case NVDEV_ENGINE_CE0 : engn = 4; break;
+ case NVDEV_ENGINE_CE1 : engn = 5; break;
+ case NVDEV_ENGINE_MSENC : engn = 6; break;
default:
return -1;
}
@@ -622,7 +622,7 @@
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PERF" },
- { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
+ { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
new file mode 100644
index 0000000..c05281c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
@@ -0,0 +1,3 @@
+nvkm-y += nvkm/engine/mspdec/nv98.o
+nvkm-y += nvkm/engine/mspdec/nvc0.o
+nvkm-y += nvkm/engine/mspdec/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
index fc9ae0f..d47df06 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nv98.c
@@ -23,30 +23,30 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nv98_vp_priv {
+struct nv98_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nv98_vp_sclass[] = {
+nv98_mspdec_sclass[] = {
{ 0x88b2, &nouveau_object_ofuncs },
{ 0x85b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nv98_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0x98),
+nv98_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -58,13 +58,13 @@
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nv98_vp_init(struct nouveau_object *object)
+nv98_mspdec_init(struct nouveau_object *object)
{
- struct nv98_vp_priv *priv = (void *)object;
+ struct nv98_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -77,32 +77,32 @@
}
static int
-nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv98_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv98_vp_priv *priv;
+ struct nv98_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x01020000;
- nv_engine(priv)->cclass = &nv98_vp_cclass;
- nv_engine(priv)->sclass = nv98_vp_sclass;
+ nv_engine(priv)->cclass = &nv98_mspdec_cclass;
+ nv_engine(priv)->sclass = nv98_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nv98_vp_oclass = {
- .handle = NV_ENGINE(VP, 0x98),
+nv98_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv98_vp_ctor,
+ .ctor = nv98_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nv98_vp_init,
+ .init = nv98_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
index ac1f62a..c622010 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nvc0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nvc0_vp_priv {
+struct nvc0_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nvc0_vp_sclass[] = {
+nvc0_mspdec_sclass[] = {
{ 0x90b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nvc0_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0xc0),
+nvc0_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nvc0_vp_init(struct nouveau_object *object)
+nvc0_mspdec_init(struct nouveau_object *object)
{
- struct nvc0_vp_priv *priv = (void *)object;
+ struct nvc0_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@
}
static int
-nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_vp_priv *priv;
+ struct nvc0_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nvc0_vp_cclass;
- nv_engine(priv)->sclass = nvc0_vp_sclass;
+ nv_engine(priv)->cclass = &nvc0_mspdec_cclass;
+ nv_engine(priv)->sclass = nvc0_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nvc0_vp_oclass = {
- .handle = NV_ENGINE(VP, 0xc0),
+nvc0_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_vp_ctor,
+ .ctor = nvc0_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nvc0_vp_init,
+ .init = nvc0_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
index d4c3108..84108b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/nve0.c
@@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
-#include <engine/vp.h>
+#include <engine/mspdec.h>
-struct nve0_vp_priv {
+struct nve0_mspdec_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
- * VP object classes
+ * MSPDEC object classes
******************************************************************************/
static struct nouveau_oclass
-nve0_vp_sclass[] = {
+nve0_mspdec_sclass[] = {
{ 0x95b2, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
- * PVP context
+ * PMSPDEC context
******************************************************************************/
static struct nouveau_oclass
-nve0_vp_cclass = {
- .handle = NV_ENGCTX(VP, 0xe0),
+nve0_mspdec_cclass = {
+ .handle = NV_ENGCTX(MSPDEC, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@@ -57,13 +57,13 @@
};
/*******************************************************************************
- * PVP engine/subdev functions
+ * PMSPDEC engine/subdev functions
******************************************************************************/
static int
-nve0_vp_init(struct nouveau_object *object)
+nve0_mspdec_init(struct nouveau_object *object)
{
- struct nve0_vp_priv *priv = (void *)object;
+ struct nve0_mspdec_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@@ -76,33 +76,33 @@
}
static int
-nve0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_mspdec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_vp_priv *priv;
+ struct nve0_mspdec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
- "PVP", "vp", &priv);
+ "PMSPDEC", "mspdec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00020000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
- nv_engine(priv)->cclass = &nve0_vp_cclass;
- nv_engine(priv)->sclass = nve0_vp_sclass;
+ nv_engine(priv)->cclass = &nve0_mspdec_cclass;
+ nv_engine(priv)->sclass = nve0_mspdec_sclass;
return 0;
}
struct nouveau_oclass
-nve0_vp_oclass = {
- .handle = NV_ENGINE(VP, 0xe0),
+nve0_mspdec_oclass = {
+ .handle = NV_ENGINE(MSPDEC, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_vp_ctor,
+ .ctor = nve0_mspdec_ctor,
.dtor = _nouveau_falcon_dtor,
- .init = nve0_vp_init,
+ .init = nve0_mspdec_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
index 6c1d9d1..e4bfb6e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
@@ -1,4 +1 @@
nvkm-y += nvkm/engine/vp/nv84.o
-nvkm-y += nvkm/engine/vp/nv98.o
-nvkm-y += nvkm/engine/vp/nvc0.o
-nvkm-y += nvkm/engine/vp/nve0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index dbcea49..a1bb3e4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -11,9 +11,9 @@
include $(src)/nvkm/subdev/instmem/Kbuild
include $(src)/nvkm/subdev/ltc/Kbuild
include $(src)/nvkm/subdev/mc/Kbuild
+include $(src)/nvkm/subdev/mmu/Kbuild
include $(src)/nvkm/subdev/mxm/Kbuild
include $(src)/nvkm/subdev/pmu/Kbuild
include $(src)/nvkm/subdev/therm/Kbuild
include $(src)/nvkm/subdev/timer/Kbuild
-include $(src)/nvkm/subdev/mmu/Kbuild
include $(src)/nvkm/subdev/volt/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index 1da2bed..3a629e0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -33,7 +33,7 @@
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index 8bc7668..830fdff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -67,7 +67,7 @@
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index fea3be5..f70b954 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -33,7 +33,7 @@
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index 4ad22a4..672aaf34 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -70,7 +70,7 @@
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (r022500 & 0x00000002) {
- disable |= (1ULL << NVDEV_ENGINE_VP);
+ disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 384d7ee..962273e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -194,6 +194,8 @@
engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC);
+ if (!engine && en->data2 == NVDEV_ENGINE_VP)
+ engine = nouveau_engine(subdev, NVDEV_ENGINE_MSPDEC);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 06fc28b..49de0cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -32,7 +32,7 @@
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */
{ 0x00008000, NVDEV_ENGINE_MSVLD },
- { 0x00020000, NVDEV_ENGINE_VP },
+ { 0x00020000, NVDEV_ENGINE_MSPDEC },
{ 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
{ 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
{ 0x00100000, NVDEV_SUBDEV_TIMER },
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 76f440e..a52687a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -36,7 +36,7 @@
{ 0x00002000, NVDEV_SUBDEV_FB },
{ 0x00008000, NVDEV_ENGINE_MSVLD },
{ 0x00040000, NVDEV_SUBDEV_THERM },
- { 0x00020000, NVDEV_ENGINE_VP },
+ { 0x00020000, NVDEV_ENGINE_MSPDEC },
{ 0x00100000, NVDEV_SUBDEV_TIMER },
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 4ac6eb9..70e1a14 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -172,7 +172,8 @@
switch (i) {
case NVDEV_ENGINE_GR : vme = 0x00; break;
- case NVDEV_ENGINE_VP : vme = 0x01; break;
+ case NVDEV_ENGINE_VP :
+ case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : vme = 0x08; break;