tree 8b674544cc2b3381fa9481d2e1e60eb99ef62a71
parent 1bb772679ffb0ba1ff1d40d8c6b855ab029f177d
author Nicolas Pitre <nico@cam.org> 1221792947 -0400
committer Nicolas Pitre <nico@cam.org> 1237165281 -0400

[ARM] xsc3: add highmem support to L2 cache handling code

On xsc3, L2 cache ops are possible only on virtual addresses.  The code
is rearranged so to have a linear progression requiring the least amount
of pte setups in the highmem case.  To protect the virtual mapping so
created, interrupts must be disabled currently up to a page worth of
address range.

The interrupt disabling is done in a way to minimize the overhead within
the inner loop.  The alternative would consist in separate code for
the highmem and non highmem compilation which is less preferable.

Signed-off-by: Nicolas Pitre <nico@marvell.com>