commit 39aee490288908a0fe50f09de8b13e8423ed7b21
author Alex Deucher <alexander.deucher@amd.com> Wed Apr 10 13:41:25 2013 -0400
committer Alex Deucher <alexander.deucher@amd.com> Thu Jun 27 10:49:12 2013 -0400
tree 5609d935aa34c8214fafdf50e6cf962d08587f0e
parent 0672e27bea2c91015627d46b0b858ed9815b0b24

drm/radeon: add cik tile mode array query

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/radeon/cik.c

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e867d95..8f6ff07 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1059,6 +1059,7 @@
 				gb_tile_moden = 0;
 				break;
 			}
+			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 		}
 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
@@ -1277,6 +1278,7 @@
 					gb_tile_moden = 0;
 					break;
 				}
+				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 			}
 		} else if (num_rbs < 4) {
@@ -1402,6 +1404,7 @@
 					gb_tile_moden = 0;
 					break;
 				}
+				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 			}
 		}
@@ -1619,6 +1622,7 @@
 				gb_tile_moden = 0;
 				break;
 			}
+			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 		}
 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {