tree 793a5765c09ff57451c33a255aa0575be950cf51
parent d4e4ab86bcba5a72779c43dc1459f71fea3d89c8
author Soren Brinkmann <soren.brinkmann@xilinx.com> 1375313099 -0700
committer Michal Simek <michal.simek@xilinx.com> 1376404655 +0200

arm: zynq: dt: Set correct L2 ram latencies

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>