Merge "drm/msm/dsi-stagging: support 180 degree panel orientation caps" into msm-4.9
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
index 2347477..8a3e704 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
@@ -25,8 +25,9 @@
Value type: <stringlist>
Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",
"osm_perfcl_base", "l3_pll", "pwrcl_pll", "perfcl_pll",
- "l3_sequencer", "pwrcl_sequencer", "perfcl_sequencer".
- Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse".
+ "l3_sequencer", "pwrcl_sequencer", or "perfcl_sequencer".
+ Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse",
+ "pwrcl_acd", "perfcl_acd", "l3_acd".
Must be specified in the same order as the corresponding
addresses are specified in the reg property.
@@ -328,6 +329,77 @@
Definition: Contains the addresses of the RAILx_CLKDOMy_PLL_MIN_FREQ
registers for the three clock domains.
+- qcom,acdtd-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values to program to the ACD
+ Tunable-Length Delay register for the L3, power and
+ performance clusters.
+
+- qcom,acdcr-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD control register
+ for the L3, power and performance clusters.
+
+- qcom,acdsscr-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD Soft Start Control
+ register for the L3, power and performance clusters.
+
+- qcom,acdextint0-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the initial values for the ACD
+ external interface configuration register for the L3, power
+ and performance clusters.
+
+- qcom,acdextint1-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the final values for the ACD
+ external interface configuration register for the L3, power
+ and performance clusters.
+
+- qcom,acdautoxfer-val
+ Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD auto transfer
+ control register for the L3, power and performance clusters.
+
+- qcom,acdavg-init
+ Usage: optional if pwrcl_acd, perfcl_acd or l3_acd registers are
+ specified
+ Value type: <prop-encoded-array>
+ Definition: Array which defines if the AVG feature for ACD should be
+ initialized for the L3, power and performance clusters.
+ Valid values are 0 or 1.
+
+- qcom,acdavgcfg0-val
+ Usage: required if qcom,acdavg-init is true for an ACD clock domain
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD AVG CFG0
+ registers for the L3, power and performance clusters.
+
+- qcom,acdavgcfg1-val
+ Usage: required if qcom,acdavg-init is true for an ACD clock domain
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD AVG CFG1
+ registers for the L3, power and performance clusters.
+
+- qcom,acdavgcfg2-val
+ Usage: required if qcom,acdavg-init is true for an ACD clock domain
+ Value type: <prop-encoded-array>
+ Definition: Array which defines the values for the ACD AVG CFG2
+ registers for the L3, power and performance clusters.
+
- clock-names
Usage: required
Value type: <string>
@@ -349,11 +421,27 @@
<0x178b0000 0x1000>,
<0x17d42400 0x0c00>,
<0x17d44400 0x0c00>,
- <0x17d46c00 0x0c00>;
+ <0x17d46c00 0x0c00>,
+ <0x17930000 0x10000>,
+ <0x17920000 0x10000>,
+ <0x17910000 0x10000>;
reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
"l3_pll", "pwrcl_pll", "perfcl_pll",
"l3_sequencer", "pwrcl_sequencer",
- "perfcl_sequencer";
+ "perfcl_sequencer", "l3_acd", "pwrcl_acd",
+ "perfcl_acd";
+
+ /* ACD configurations for L3, Silver, and Gold clusters */
+ qcom,acdtd-val = <0x0000b411 0x0000b411 0x0000b411>;
+ qcom,acdcr-val = <0x002c5ffd 0x002c5ffd 0x002c5ffd>;
+ qcom,acdsscr-val = <0x00000901 0x00000901 0x00000901>;
+ qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8 0x2cf9ae8>;
+ qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe 0x2cf9afe>;
+ qcom,acdautoxfer-val = <0x00000015 0x00000015 0x00000015>;
+ qcom,acdavgcfg2-val = <0x0 0x56a38822 0x56a38822>;
+ qcom,acdavgcfg1-val = <0x0 0x27104e20 0x27104e20>;
+ qcom,acdavgcfg0-val = <0x0 0xa08007a1 0xa08007a1>;
+ qcom,acdavg-init = <0 1 1>;
vdd-l3-supply = <&apc0_l3_vreg>;
vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt b/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt
index a244d6c..51abe56 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt
@@ -12,6 +12,7 @@
or when entering sleep state.
- #address-cells: Should be <1> Address cells for i2c device address
- #size-cells: Should be <0> as i2c addresses have no size component
+ - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.
Child nodes should conform to i2c bus binding.
@@ -30,4 +31,5 @@
pinctrl-1 = <&qup_1_i2c_5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
+ qcom,wrapper-core = <&qupv3_0>;
};
diff --git a/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt b/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt
new file mode 100644
index 0000000..7da95f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt
@@ -0,0 +1,37 @@
+Qualcomm Technologies, Inc. GENI Serial Engine Driver
+
+GENI Serial Engine Driver is used to configure and read the configuration
+from the Serial Engines on Qualcomm Technologies, Inc. Universal Peripheral
+(QUPv3) core. It is also used to enable the stage1 IOMMU translation and
+manage resources associated with the QUPv3 core.
+
+Required properties:
+- compatible: Must be "qcom,qupv3-geni-se".
+- reg: Must contain QUPv3 register address and length.
+- qcom,bus-mas-id: Master Endpoint ID for bus driver.
+- qcom,bus-slv-id: Slave Endpoint ID for bus driver.
+
+Optional properties:
+- qcom,iommu-s1-bypass: Boolean flag to bypass IOMMU stage 1 translation.
+
+Optional subnodes:
+qcom,iommu_qupv3_geni_se_cb: Child node representing the QUPV3 context
+ bank.
+
+Subnode Required properties:
+- compatible : Must be "qcom,qupv3-geni-se-cb";
+- iommus: A list of phandle and IOMMU specifier pairs that
+ describe the IOMMU master interfaces of the device.
+
+Example:
+ qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x8c0000 0x6000>;
+ qcom,bus-mas-id = <100>;
+ qcom,bus-slv-id = <300>;
+
+ iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
+ compatible = "qcom,qupv3-geni-se-cb";
+ iommus = <&apps_smmu 0x1 0x0>;
+ };
+ }
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
index 0173a3d..b616bf3 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
@@ -15,10 +15,9 @@
- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
Should be "active" and "sleep" for the pin confuguration when core is active
or when entering sleep state.
+- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.
Optional properties:
-- qcom,bus-mas: contains the bus master id needed to put in bus bandwidth votes
- for inter-connect buses.
- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.
Example:
@@ -34,6 +33,6 @@
pinctrl-0 = <&qup_1_uart_3_active>;
pinctrl-1 = <&qup_1_uart_3_sleep>;
interrupts = <0 355 0>;
- qcom,bus-mas = <MASTER_BLSP_2>;
+ qcom,wrapper-core = <&qupv3_0>;
qcom,wakeup-byte = <0xFF>;
};
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
index 868a5f0..cd2d2ea 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
@@ -23,6 +23,7 @@
- spi-max-frequency: Specifies maximum SPI clock frequency,
Units - Hz. Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
+- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller.
SPI slave nodes must be children of the SPI master node and can contain
properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -44,6 +45,7 @@
pinctrl-1 = <&qup_1_spi_2_sleep>;
interrupts = <GIC_SPI 354 0>;
spi-max-frequency = <19200000>;
+ qcom,wrapper-core = <&qupv3_0>;
dev@0 {
compatible = "dummy,slave";
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
index f7d4b89..1fdf740 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
@@ -242,6 +242,16 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
+&dsi_dual_nt35597_truly_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-panel-mode-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
@@ -266,7 +276,7 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
-&dsi_dual_nt35597_truly_video_display {
+&dsi_dual_nt35597_truly_cmd_display {
qcom,dsi-display-active;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
index 5b18545..508b645 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
@@ -94,6 +94,16 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
+&dsi_dual_nt35597_truly_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-panel-mode-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
@@ -118,7 +128,7 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
-&dsi_dual_nt35597_truly_video_display {
+&dsi_dual_nt35597_truly_cmd_display {
qcom,dsi-display-active;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
index e5d1a74..0fb455f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
@@ -14,6 +14,18 @@
&soc {
/* QUPv3 South instances */
+ qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x8c0000 0x6000>;
+ qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>;
+ qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,iommu-s1-bypass;
+
+ iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
+ compatible = "qcom,qupv3-geni-se-cb";
+ iommus = <&apps_smmu 0x003 0x0>;
+ };
+ };
/*
* HS UART instances. HS UART usecases can be supported on these
@@ -33,8 +45,8 @@
interrupts-extended = <&intc GIC_SPI 607 0>,
<&tlmm 48 0>;
status = "disabled";
- qcom,bus-mas = <MSM_BUS_MASTER_BLSP_1>;
qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_0>;
};
qupv3_se7_4uart: qcom,qup_uart@0x89c000 {
@@ -51,8 +63,8 @@
interrupts-extended = <&intc GIC_SPI 608 0>,
<&tlmm 96 0>;
status = "disabled";
- qcom,bus-mas = <MSM_BUS_MASTER_BLSP_1>;
qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_0>;
};
/* I2C */
@@ -69,6 +81,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -85,6 +98,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -101,6 +115,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -117,6 +132,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -133,6 +149,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -149,6 +166,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -165,6 +183,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -181,6 +200,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -200,6 +220,7 @@
pinctrl-1 = <&qupv3_se0_spi_sleep>;
interrupts = <GIC_SPI 601 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -218,6 +239,7 @@
pinctrl-1 = <&qupv3_se1_spi_sleep>;
interrupts = <GIC_SPI 602 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -236,6 +258,7 @@
pinctrl-1 = <&qupv3_se2_spi_sleep>;
interrupts = <GIC_SPI 603 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -254,6 +277,7 @@
pinctrl-1 = <&qupv3_se3_spi_sleep>;
interrupts = <GIC_SPI 604 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -272,6 +296,7 @@
pinctrl-1 = <&qupv3_se4_spi_sleep>;
interrupts = <GIC_SPI 605 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -290,6 +315,7 @@
pinctrl-1 = <&qupv3_se5_spi_sleep>;
interrupts = <GIC_SPI 606 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -308,6 +334,7 @@
pinctrl-1 = <&qupv3_se6_spi_sleep>;
interrupts = <GIC_SPI 607 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
@@ -326,10 +353,24 @@
pinctrl-1 = <&qupv3_se7_spi_sleep>;
interrupts = <GIC_SPI 608 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
/* QUPv3 North Instances */
+ qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0xac0000 0x6000>;
+ qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>;
+ qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,iommu-s1-bypass;
+
+ iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
+ compatible = "qcom,qupv3-geni-se-cb";
+ iommus = <&apps_smmu 0x6c3 0x0>;
+ };
+ };
+
/* 2-wire UART */
/* Debug UART Instance for CDP/MTP platform */
@@ -344,8 +385,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_2uart_active>;
pinctrl-1 = <&qupv3_se9_2uart_sleep>;
- qcom,bus-mas = <MSM_BUS_MASTER_BLSP_2>;
interrupts = <GIC_SPI 354 0>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -362,7 +403,7 @@
pinctrl-0 = <&qupv3_se10_2uart_active>;
pinctrl-1 = <&qupv3_se10_2uart_sleep>;
interrupts = <GIC_SPI 355 0>;
- qcom,bus-mas = <MSM_BUS_MASTER_BLSP_2>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -380,6 +421,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -396,6 +438,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -412,6 +455,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -428,6 +472,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_i2c_active>;
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -444,6 +489,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_i2c_active>;
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -460,6 +506,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_i2c_active>;
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -476,6 +523,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_i2c_active>;
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -492,6 +540,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -511,6 +560,7 @@
pinctrl-1 = <&qupv3_se8_spi_sleep>;
interrupts = <GIC_SPI 353 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -529,6 +579,7 @@
pinctrl-1 = <&qupv3_se9_spi_sleep>;
interrupts = <GIC_SPI 354 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -547,6 +598,7 @@
pinctrl-1 = <&qupv3_se10_spi_sleep>;
interrupts = <GIC_SPI 355 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -565,6 +617,7 @@
pinctrl-1 = <&qupv3_se11_spi_sleep>;
interrupts = <GIC_SPI 356 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -583,6 +636,7 @@
pinctrl-1 = <&qupv3_se12_spi_sleep>;
interrupts = <GIC_SPI 357 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -601,6 +655,7 @@
pinctrl-1 = <&qupv3_se13_spi_sleep>;
interrupts = <GIC_SPI 358 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -619,6 +674,7 @@
pinctrl-1 = <&qupv3_se14_spi_sleep>;
interrupts = <GIC_SPI 359 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
@@ -637,6 +693,7 @@
pinctrl-1 = <&qupv3_se15_spi_sleep>;
interrupts = <GIC_SPI 360 0>;
spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
index 74bb133..255c0b3 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
@@ -371,7 +371,7 @@
};
&mdss_mdp {
- connectors = <&sde_rscc &sde_wb &dsi_dual_nt35597_truly_video_display>;
+ connectors = <&sde_rscc &sde_wb &dsi_dual_nt35597_truly_cmd_display>;
};
&dsi_dual_nt35597_truly_video {
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index 6e5a353..10b44f8 100644
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -263,6 +263,8 @@
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_USB_USBNET=y
+CONFIG_WIL6210=m
+# CONFIG_WIL6210_TRACING is not set
CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_CLD_LL_CORE=y
CONFIG_INPUT_EVDEV=y
@@ -413,6 +415,7 @@
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
CONFIG_DMADEVICES=y
+CONFIG_QCOM_GPI_DMA=y
CONFIG_UIO=y
CONFIG_UIO_MSM_SHAREDMEM=y
CONFIG_STAGING=y
@@ -429,7 +432,9 @@
CONFIG_QPNP_COINCELL=y
CONFIG_QPNP_REVID=y
CONFIG_USB_BAM=y
+CONFIG_MSM_11AD=m
CONFIG_SEEMP_CORE=y
+CONFIG_QCOM_GENI_SE=y
CONFIG_MSM_GCC_SDM845=y
CONFIG_MSM_VIDEOCC_SDM845=y
CONFIG_MSM_CAMCC_SDM845=y
@@ -481,6 +486,7 @@
CONFIG_ICNSS=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_MSM_ADSP_LOADER=y
+CONFIG_MSM_PERFORMANCE=y
CONFIG_MSM_CDSP_LOADER=y
CONFIG_MSM_AVTIMER=y
CONFIG_MSM_EVENT_TIMER=y
diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig
index 9fc6d4e..737f47f 100644
--- a/arch/arm64/configs/sdm845_defconfig
+++ b/arch/arm64/configs/sdm845_defconfig
@@ -254,6 +254,7 @@
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_QCOM=y
CONFIG_SCSI_UFS_QCOM_ICE=y
+CONFIG_SCSI_UFSHCD_CMD_LOGGING=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
@@ -272,6 +273,7 @@
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_USB_USBNET=y
+CONFIG_WIL6210=m
CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_CLD_LL_CORE=y
CONFIG_INPUT_EVDEV=y
@@ -429,6 +431,8 @@
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
CONFIG_DMADEVICES=y
+CONFIG_QCOM_GPI_DMA=y
+CONFIG_QCOM_GPI_DMA_DEBUG=y
CONFIG_UIO=y
CONFIG_UIO_MSM_SHAREDMEM=y
CONFIG_STAGING=y
@@ -445,7 +449,9 @@
CONFIG_QPNP_COINCELL=y
CONFIG_QPNP_REVID=y
CONFIG_USB_BAM=y
+CONFIG_MSM_11AD=m
CONFIG_SEEMP_CORE=y
+CONFIG_QCOM_GENI_SE=y
CONFIG_MSM_GCC_SDM845=y
CONFIG_MSM_VIDEOCC_SDM845=y
CONFIG_MSM_CAMCC_SDM845=y
@@ -462,6 +468,7 @@
CONFIG_ARM_SMMU=y
CONFIG_QCOM_LAZY_MAPPING=y
CONFIG_IOMMU_DEBUG=y
+CONFIG_IOMMU_DEBUG_TRACKING=y
CONFIG_IOMMU_TESTS=y
CONFIG_QCOM_CPUSS_DUMP=y
CONFIG_QCOM_RUN_QUEUE_STATS=y
@@ -501,6 +508,7 @@
CONFIG_ICNSS_DEBUG=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_MSM_ADSP_LOADER=y
+CONFIG_MSM_PERFORMANCE=y
CONFIG_MSM_CDSP_LOADER=y
CONFIG_MSM_AVTIMER=y
CONFIG_MSM_EVENT_TIMER=y
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 0363fe8..dc06a33 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -30,14 +30,20 @@
#include <asm/pgtable.h>
#include <asm/sysreg.h>
#include <asm/tlbflush.h>
+#include <linux/msm_rtb.h>
static inline void contextidr_thread_switch(struct task_struct *next)
{
+ pid_t pid = task_pid_nr(next);
+
if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
return;
- write_sysreg(task_pid_nr(next), contextidr_el1);
+ write_sysreg(pid, contextidr_el1);
isb();
+
+ uncached_logk(LOGK_CTXID, (void *)(u64)pid);
+
}
/*
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 837bbab..75088c00 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -943,6 +943,8 @@
.sync_single_for_device = __iommu_sync_single_for_device,
.sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
.sync_sg_for_device = __iommu_sync_sg_for_device,
+ .map_resource = iommu_dma_map_resource,
+ .unmap_resource = iommu_dma_unmap_resource,
.dma_supported = iommu_dma_supported,
.mapping_error = iommu_dma_mapping_error,
};
@@ -1847,6 +1849,45 @@
__dma_page_cpu_to_dev(page, offset, size, dir);
}
+static dma_addr_t arm_iommu_dma_map_resource(
+ struct device *dev, phys_addr_t phys_addr,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+ size_t offset = phys_addr & ~PAGE_MASK;
+ size_t len = PAGE_ALIGN(size + offset);
+ dma_addr_t dma_addr;
+ int prot;
+
+ dma_addr = __alloc_iova(mapping, len);
+ if (dma_addr == DMA_ERROR_CODE)
+ return dma_addr;
+
+ prot = __dma_direction_to_prot(dir);
+ prot |= IOMMU_MMIO;
+
+ if (iommu_map(mapping->domain, dma_addr, phys_addr - offset,
+ len, prot)) {
+ __free_iova(mapping, dma_addr, len);
+ return DMA_ERROR_CODE;
+ }
+ return dma_addr + offset;
+}
+
+static void arm_iommu_dma_unmap_resource(
+ struct device *dev, dma_addr_t addr,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+ size_t offset = addr & ~PAGE_MASK;
+ size_t len = PAGE_ALIGN(size + offset);
+
+ iommu_unmap(mapping->domain, addr - offset, len);
+ __free_iova(mapping, addr - offset, len);
+}
+
static int arm_iommu_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
@@ -1869,6 +1910,9 @@
.sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
.sync_sg_for_device = arm_iommu_sync_sg_for_device,
+ .map_resource = arm_iommu_dma_map_resource,
+ .unmap_resource = arm_iommu_dma_unmap_resource,
+
.set_dma_mask = arm_dma_set_mask,
.mapping_error = arm_iommu_mapping_error,
};
diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c
index 5fb870b..4efecef 100644
--- a/drivers/clk/qcom/clk-cpu-osm.c
+++ b/drivers/clk/qcom/clk-cpu-osm.c
@@ -154,6 +154,42 @@
#define OSM_CYCLE_COUNTER_STATUS_REG(n) (OSM_CYCLE_COUNTER_STATUS_REG_0 + \
(4 * n))
+/* ACD registers */
+#define ACD_HW_VERSION 0x0
+#define ACDCR 0x4
+#define ACDTD 0x8
+#define ACDSSCR 0x28
+#define ACD_EXTINT_CFG 0x30
+#define ACD_DCVS_SW 0x34
+#define ACD_GFMUX_CFG 0x3c
+#define ACD_READOUT_CFG 0x48
+#define ACD_AVG_CFG_0 0x4c
+#define ACD_AVG_CFG_1 0x50
+#define ACD_AVG_CFG_2 0x54
+#define ACD_AUTOXFER_CFG 0x80
+#define ACD_AUTOXFER 0x84
+#define ACD_AUTOXFER_CTL 0x88
+#define ACD_AUTOXFER_STATUS 0x8c
+#define ACD_WRITE_CTL 0x90
+#define ACD_WRITE_STATUS 0x94
+#define ACD_READOUT 0x98
+
+#define ACD_MASTER_ONLY_REG_ADDR 0x80
+#define ACD_1P1_MAX_REG_OFFSET 0x100
+#define ACD_WRITE_CTL_UPDATE_EN BIT(0)
+#define ACD_WRITE_CTL_SELECT_SHIFT 1
+#define ACD_GFMUX_CFG_SELECT BIT(0)
+#define ACD_AUTOXFER_START_CLEAR 0
+#define ACD_AUTOXFER_START_SET 1
+#define AUTO_XFER_DONE_MASK BIT(0)
+#define ACD_DCVS_SW_DCVS_IN_PRGR_SET BIT(0)
+#define ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR 0
+#define ACD_LOCAL_TRANSFER_TIMEOUT_NS 500
+
+#define ACD_REG_RELATIVE_ADDR(addr) (addr / 4)
+#define ACD_REG_RELATIVE_ADDR_BITMASK(addr) \
+ (1 << (ACD_REG_RELATIVE_ADDR(addr)))
+
static const struct regmap_config osm_qcom_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -166,6 +202,7 @@
PLL_BASE,
EFUSE_BASE,
SEQ_BASE,
+ ACD_BASE,
NUM_BASES,
};
@@ -187,6 +224,8 @@
long frequency;
};
+static struct dentry *osm_debugfs_base;
+
struct clk_osm {
struct clk_hw hw;
struct osm_entry osm_table[OSM_TABLE_SIZE];
@@ -236,12 +275,173 @@
u32 trace_periodic_timer;
bool trace_en;
bool wdog_trace_en;
+
+ bool acd_init;
+ u32 acd_td;
+ u32 acd_cr;
+ u32 acd_sscr;
+ u32 acd_extint0_cfg;
+ u32 acd_extint1_cfg;
+ u32 acd_autoxfer_ctl;
+ u32 acd_debugfs_addr;
+ bool acd_avg_init;
+ u32 acd_avg_cfg0;
+ u32 acd_avg_cfg1;
+ u32 acd_avg_cfg2;
};
static struct regulator *vdd_l3;
static struct regulator *vdd_pwrcl;
static struct regulator *vdd_perfcl;
+static inline int clk_osm_acd_mb(struct clk_osm *c)
+{
+ return readl_relaxed_no_log((char *)c->vbases[ACD_BASE] +
+ ACD_HW_VERSION);
+}
+
+static int clk_osm_acd_local_read_reg(struct clk_osm *c, u32 offset)
+{
+ u32 reg = 0;
+ int timeout;
+
+ if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
+ pr_err("ACD register at offset=0x%x not locally readable\n",
+ offset);
+ return -EINVAL;
+ }
+
+ /* Set select field in read control register */
+ writel_relaxed(ACD_REG_RELATIVE_ADDR(offset),
+ (char *)c->vbases[ACD_BASE] + ACD_READOUT_CFG);
+
+ /* Clear write control register */
+ writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
+
+ /* Set select and update_en fields in write control register */
+ reg = (ACD_REG_RELATIVE_ADDR(ACD_READOUT_CFG)
+ << ACD_WRITE_CTL_SELECT_SHIFT)
+ | ACD_WRITE_CTL_UPDATE_EN;
+ writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
+
+ /* Ensure writes complete before polling */
+ clk_osm_acd_mb(c);
+
+ /* Poll write status register */
+ for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
+ timeout -= 100) {
+ reg = readl_relaxed((char *)c->vbases[ACD_BASE]
+ + ACD_WRITE_STATUS);
+ if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(ACD_READOUT_CFG))))
+ break;
+ ndelay(100);
+ }
+
+ if (!timeout) {
+ pr_err("local read timed out, offset=0x%x status=0x%x\n",
+ offset, reg);
+ return -ETIMEDOUT;
+ }
+
+ reg = readl_relaxed((char *)c->vbases[ACD_BASE] + ACD_READOUT);
+ return reg;
+}
+
+static int clk_osm_acd_local_write_reg(struct clk_osm *c, u32 val, u32 offset)
+{
+ u32 reg = 0;
+ int timeout;
+
+ if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
+ pr_err("ACD register at offset=0x%x not transferrable\n",
+ offset);
+ return -EINVAL;
+ }
+
+ /* Clear write control register */
+ writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
+
+ /* Set select and update_en fields in write control register */
+ reg = (ACD_REG_RELATIVE_ADDR(offset) << ACD_WRITE_CTL_SELECT_SHIFT)
+ | ACD_WRITE_CTL_UPDATE_EN;
+ writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
+
+ /* Ensure writes complete before polling */
+ clk_osm_acd_mb(c);
+
+ /* Poll write status register */
+ for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
+ timeout -= 100) {
+ reg = readl_relaxed((char *)c->vbases[ACD_BASE]
+ + ACD_WRITE_STATUS);
+ if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(offset))))
+ break;
+ ndelay(100);
+ }
+
+ if (!timeout) {
+ pr_err("local write timed out, offset=0x%x val=0x%x status=0x%x\n",
+ offset, val, reg);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int clk_osm_acd_master_write_through_reg(struct clk_osm *c,
+ u32 val, u32 offset)
+{
+ writel_relaxed(val, (char *)c->vbases[ACD_BASE] + offset);
+
+ /* Ensure writes complete before transfer to local copy */
+ clk_osm_acd_mb(c);
+
+ return clk_osm_acd_local_write_reg(c, val, offset);
+}
+
+static int clk_osm_acd_auto_local_write_reg(struct clk_osm *c, u32 mask)
+{
+ u32 numregs, bitmask = mask;
+ u32 reg = 0;
+ int timeout;
+
+ /* count number of bits set in register mask */
+ for (numregs = 0; bitmask; numregs++)
+ bitmask &= bitmask - 1;
+
+ /* Program auto-transfer mask */
+ writel_relaxed(mask, (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER_CFG);
+
+ /* Clear start field in auto-transfer register */
+ writel_relaxed(ACD_AUTOXFER_START_CLEAR,
+ (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
+
+ /* Set start field in auto-transfer register */
+ writel_relaxed(ACD_AUTOXFER_START_SET,
+ (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
+
+ /* Ensure writes complete before polling */
+ clk_osm_acd_mb(c);
+
+ /* Poll auto-transfer status register */
+ for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS * numregs;
+ timeout > 0; timeout -= 100) {
+ reg = readl_relaxed((char *)c->vbases[ACD_BASE]
+ + ACD_AUTOXFER_STATUS);
+ if (reg & AUTO_XFER_DONE_MASK)
+ break;
+ ndelay(100);
+ }
+
+ if (!timeout) {
+ pr_err("local register auto-transfer timed out, mask=0x%x registers=%d status=0x%x\n",
+ mask, numregs, reg);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw)
{
return container_of(_hw, struct clk_osm, hw);
@@ -265,9 +465,10 @@
writel_relaxed(val, (char *)c->vbases[SEQ_BASE] + offset);
}
-static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset)
+static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset,
+ int base)
{
- writel_relaxed(val, (char *)c->vbases[OSM_BASE] + offset);
+ writel_relaxed(val, (char *)c->vbases[base] + offset);
}
static inline int clk_osm_read_reg(struct clk_osm *c, u32 offset)
@@ -356,7 +557,7 @@
{
struct clk_osm *cpuclk = to_clk_osm(hw);
- clk_osm_write_reg(cpuclk, 1, ENABLE_REG);
+ clk_osm_write_reg(cpuclk, 1, ENABLE_REG, OSM_BASE);
/* Make sure the write goes through before proceeding */
clk_osm_mb(cpuclk, OSM_BASE);
@@ -410,7 +611,8 @@
* TODO: Program INACTIVE_OS_REQUEST if needed.
*/
clk_osm_write_reg(parent, index,
- DCVS_PERF_STATE_DESIRED_REG(cpuclk->core_num));
+ DCVS_PERF_STATE_DESIRED_REG(cpuclk->core_num),
+ OSM_BASE);
/* Make sure the write goes through before proceeding */
clk_osm_mb(parent, OSM_BASE);
@@ -444,7 +646,8 @@
}
pr_debug("rate: %lu --> index %d\n", rate, index);
- clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG_0);
+ clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG_0,
+ OSM_BASE);
/* Make sure the write goes through before proceeding */
clk_osm_mb(cpuclk, OSM_BASE);
@@ -916,50 +1119,51 @@
if (c->red_fsm_en) {
val = clk_osm_read_reg(c, VMIN_REDUCTION_ENABLE_REG) | BIT(0);
val |= BVAL(6, 1, c->min_cpr_vc);
- clk_osm_write_reg(c, val, VMIN_REDUCTION_ENABLE_REG);
+ clk_osm_write_reg(c, val, VMIN_REDUCTION_ENABLE_REG,
+ OSM_BASE);
clk_osm_write_reg(c, clk_osm_count_ns(c, 10000),
- VMIN_REDUCTION_TIMER_REG);
+ VMIN_REDUCTION_TIMER_REG, OSM_BASE);
}
/* Boost FSM */
if (c->boost_fsm_en) {
val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
val |= DELTA_DEX_VAL | CC_BOOST_FSM_EN | IGNORE_PLL_LOCK;
- clk_osm_write_reg(c, val, PDN_FSM_CTRL_REG);
+ clk_osm_write_reg(c, val, PDN_FSM_CTRL_REG, OSM_BASE);
val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG0);
val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG0);
+ clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG0, OSM_BASE);
val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG1);
val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG1);
+ clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG1, OSM_BASE);
val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG2);
val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG2);
+ clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG2, OSM_BASE);
}
/* Safe Freq FSM */
if (c->safe_fsm_en) {
val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
clk_osm_write_reg(c, val | DCVS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG);
+ PDN_FSM_CTRL_REG, OSM_BASE);
val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG0);
val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG0);
+ clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG1);
val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG1);
+ clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG2);
val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG2);
+ clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
}
@@ -967,46 +1171,46 @@
if (c->ps_fsm_en) {
val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
clk_osm_write_reg(c, val | PS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG);
+ PDN_FSM_CTRL_REG, OSM_BASE);
val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG0);
val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG0);
+ clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG1);
val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG1);
+ clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG2);
val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG2);
+ clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
}
/* PLL signal timing control */
if (c->boost_fsm_en || c->safe_fsm_en || c->ps_fsm_en)
- clk_osm_write_reg(c, 0x2, BOOST_PROG_SYNC_DELAY_REG);
+ clk_osm_write_reg(c, 0x2, BOOST_PROG_SYNC_DELAY_REG, OSM_BASE);
/* DCVS droop FSM - only if RCGwRC is not used for di/dt control */
if (c->droop_fsm_en) {
val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
clk_osm_write_reg(c, val | DCVS_DROOP_FSM_EN_MASK,
- PDN_FSM_CTRL_REG);
+ PDN_FSM_CTRL_REG, OSM_BASE);
}
if (c->ps_fsm_en || c->droop_fsm_en) {
- clk_osm_write_reg(c, 0x1, DROOP_PROG_SYNC_DELAY_REG);
+ clk_osm_write_reg(c, 0x1, DROOP_PROG_SYNC_DELAY_REG, OSM_BASE);
clk_osm_write_reg(c, clk_osm_count_ns(c, 100),
- DROOP_RELEASE_TIMER_CTRL);
+ DROOP_RELEASE_TIMER_CTRL, OSM_BASE);
clk_osm_write_reg(c, clk_osm_count_ns(c, 150),
- DCVS_DROOP_TIMER_CTRL);
+ DCVS_DROOP_TIMER_CTRL, OSM_BASE);
/*
* TODO: Check if DCVS_DROOP_CODE used is correct. Also check
* if RESYNC_CTRL should be set for L3.
*/
val = BIT(31) | BVAL(22, 16, 0x2) | BVAL(6, 0, 0x8);
- clk_osm_write_reg(c, val, DROOP_CTRL_REG);
+ clk_osm_write_reg(c, val, DROOP_CTRL_REG, OSM_BASE);
}
}
@@ -1034,17 +1238,20 @@
} else {
val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&perfcl_clk,
array[perfcl_clk.cluster_num]);
clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
}
/*
@@ -1060,17 +1267,20 @@
} else {
val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
+ array[perfcl_clk.cluster_num]);
clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS);
+ LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
+ OSM_BASE);
}
/* Enable or disable honoring of LLM Voltage requests */
@@ -1084,11 +1294,11 @@
/* Enable or disable LLM VOLT DVCS */
regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
/* Wait for the writes to complete */
clk_osm_mb(&perfcl_clk, OSM_BASE);
@@ -1120,17 +1330,20 @@
rc);
} else {
val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_INC_HYSTERESIS);
+ clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS);
+ LLM_FREQ_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&perfcl_clk,
array[perfcl_clk.cluster_num]);
clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS);
+ LLM_FREQ_VOTE_INC_HYSTERESIS,
+ OSM_BASE);
}
/*
@@ -1145,17 +1358,18 @@
rc);
} else {
val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_DEC_HYSTERESIS);
+ clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_DEC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS);
+ LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
val = clk_osm_count_ns(&perfcl_clk,
array[perfcl_clk.cluster_num]);
clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS);
+ LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
}
/* Enable or disable honoring of LLM frequency requests */
@@ -1169,11 +1383,11 @@
/* Enable or disable LLM FREQ DVCS */
regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE);
+ clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
/* Wait for the write to complete */
clk_osm_mb(&perfcl_clk, OSM_BASE);
@@ -1201,15 +1415,18 @@
} else {
val = clk_osm_count_ns(&l3_clk,
array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_INC_HYSTERESIS);
+ clk_osm_write_reg(&l3_clk, val, SPM_CC_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_INC_HYSTERESIS);
+ clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_INC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&perfcl_clk,
array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_INC_HYSTERESIS);
+ clk_osm_write_reg(&perfcl_clk, val, SPM_CC_INC_HYSTERESIS,
+ OSM_BASE);
}
rc = of_property_read_u32_array(of, "qcom,down-timer",
@@ -1219,15 +1436,18 @@
} else {
val = clk_osm_count_ns(&l3_clk,
array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DEC_HYSTERESIS);
+ clk_osm_write_reg(&l3_clk, val, SPM_CC_DEC_HYSTERESIS,
+ OSM_BASE);
val = clk_osm_count_ns(&pwrcl_clk,
array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DEC_HYSTERESIS);
+ clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DEC_HYSTERESIS,
+ OSM_BASE);
clk_osm_count_ns(&perfcl_clk,
array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DEC_HYSTERESIS);
+ clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DEC_HYSTERESIS,
+ OSM_BASE);
}
/* OSM index override for cluster PC */
@@ -1236,15 +1456,18 @@
if (rc) {
dev_dbg(&pdev->dev, "No PC override index value, rc=%d\n",
rc);
- clk_osm_write_reg(&pwrcl_clk, 0, CC_ZERO_BEHAV_CTRL);
- clk_osm_write_reg(&perfcl_clk, 0, CC_ZERO_BEHAV_CTRL);
+ clk_osm_write_reg(&pwrcl_clk, 0, CC_ZERO_BEHAV_CTRL, OSM_BASE);
+ clk_osm_write_reg(&perfcl_clk, 0, CC_ZERO_BEHAV_CTRL,
+ OSM_BASE);
} else {
val = BVAL(6, 1, array[pwrcl_clk.cluster_num])
| ENABLE_OVERRIDE;
- clk_osm_write_reg(&pwrcl_clk, val, CC_ZERO_BEHAV_CTRL);
+ clk_osm_write_reg(&pwrcl_clk, val, CC_ZERO_BEHAV_CTRL,
+ OSM_BASE);
val = BVAL(6, 1, array[perfcl_clk.cluster_num])
| ENABLE_OVERRIDE;
- clk_osm_write_reg(&perfcl_clk, val, CC_ZERO_BEHAV_CTRL);
+ clk_osm_write_reg(&perfcl_clk, val, CC_ZERO_BEHAV_CTRL,
+ OSM_BASE);
}
/* Wait for the writes to complete */
@@ -1256,15 +1479,18 @@
val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(2);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(2);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(2);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
}
rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-c2-active");
@@ -1273,15 +1499,18 @@
val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(1);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(1);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
val &= ~BIT(1);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING);
+ clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
+ OSM_BASE);
}
rc = of_property_read_bool(pdev->dev.of_node, "qcom,disable-cc-dvcs");
@@ -1291,9 +1520,9 @@
} else
val = 0;
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DCVS_DISABLE);
+ clk_osm_write_reg(&l3_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
+ clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
+ clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
/* Wait for the writes to complete */
clk_osm_mb(&perfcl_clk, OSM_BASE);
@@ -1335,8 +1564,9 @@
u32 lval = 0xFF, val;
int i;
- clk_osm_write_reg(c, BVAL(23, 16, 0xF), SPM_CORE_COUNT_CTRL);
- clk_osm_write_reg(c, PLL_MIN_LVAL, PLL_MIN_FREQ_REG);
+ clk_osm_write_reg(c, BVAL(23, 16, 0xF), SPM_CORE_COUNT_CTRL,
+ OSM_BASE);
+ clk_osm_write_reg(c, PLL_MIN_LVAL, PLL_MIN_FREQ_REG, OSM_BASE);
/* Pattern to set/clear PLL lock in PDN_FSM_CTRL_REG */
val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
@@ -1396,10 +1626,12 @@
}
table_entry_offset = i * OSM_REG_SIZE;
- clk_osm_write_reg(c, freq_val, FREQ_REG + table_entry_offset);
- clk_osm_write_reg(c, volt_val, VOLT_REG + table_entry_offset);
+ clk_osm_write_reg(c, freq_val, FREQ_REG + table_entry_offset,
+ OSM_BASE);
+ clk_osm_write_reg(c, volt_val, VOLT_REG + table_entry_offset,
+ OSM_BASE);
clk_osm_write_reg(c, override_val, OVERRIDE_REG +
- table_entry_offset);
+ table_entry_offset, OSM_BASE);
}
/* Make sure all writes go through */
@@ -1575,7 +1807,7 @@
do_div(ratio, c->xo_clk_rate);
val |= BVAL(5, 1, ratio - 1) | OSM_CYCLE_COUNTER_USE_XO_EDGE_EN;
- clk_osm_write_reg(c, val, OSM_CYCLE_COUNTER_CTRL_REG);
+ clk_osm_write_reg(c, val, OSM_CYCLE_COUNTER_CTRL_REG, OSM_BASE);
pr_debug("OSM to XO clock ratio: %d\n", ratio);
}
@@ -1750,6 +1982,149 @@
return rc;
}
+static int clk_osm_parse_acd_dt_configs(struct platform_device *pdev)
+{
+ struct device_node *of = pdev->dev.of_node;
+ u32 *array;
+ int rc = 0;
+
+ array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
+ GFP_KERNEL);
+ if (!array)
+ return -ENOMEM;
+
+ l3_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "l3_acd") != NULL ? true : false;
+ pwrcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pwrcl_acd") != NULL ? true : false;
+ perfcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "perfcl_acd") != NULL ? true : false;
+
+ if (pwrcl_clk.acd_init || perfcl_clk.acd_init || l3_clk.acd_init) {
+ rc = of_property_read_u32_array(of, "qcom,acdtd-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdtd-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_td = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_td = array[perfcl_clk.cluster_num];
+ l3_clk.acd_td = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdcr-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdcr-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_cr = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_cr = array[perfcl_clk.cluster_num];
+ l3_clk.acd_cr = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdsscr-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdsscr-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_sscr = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_sscr = array[perfcl_clk.cluster_num];
+ l3_clk.acd_sscr = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdextint0-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdextint0-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_extint0_cfg = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_extint0_cfg = array[perfcl_clk.cluster_num];
+ l3_clk.acd_extint0_cfg = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdextint1-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdextint1-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_extint1_cfg = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_extint1_cfg = array[perfcl_clk.cluster_num];
+ l3_clk.acd_extint1_cfg = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdautoxfer-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdautoxfer-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+
+ pwrcl_clk.acd_autoxfer_ctl = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_autoxfer_ctl = array[perfcl_clk.cluster_num];
+ l3_clk.acd_autoxfer_ctl = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdavg-init",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdavg-init property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+ pwrcl_clk.acd_avg_init = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_avg_init = array[perfcl_clk.cluster_num];
+ l3_clk.acd_avg_init = array[l3_clk.cluster_num];
+ }
+
+ if (pwrcl_clk.acd_avg_init || perfcl_clk.acd_avg_init ||
+ l3_clk.acd_avg_init) {
+ rc = of_property_read_u32_array(of, "qcom,acdavgcfg0-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdavgcfg0-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+ pwrcl_clk.acd_avg_cfg0 = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_avg_cfg0 = array[perfcl_clk.cluster_num];
+ l3_clk.acd_avg_cfg0 = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdavgcfg1-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdavgcfg1-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+ pwrcl_clk.acd_avg_cfg1 = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_avg_cfg1 = array[perfcl_clk.cluster_num];
+ l3_clk.acd_avg_cfg1 = array[l3_clk.cluster_num];
+
+ rc = of_property_read_u32_array(of, "qcom,acdavgcfg2-val",
+ array, MAX_CLUSTER_CNT);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to find qcom,acdavgcfg2-val property, rc=%d\n",
+ rc);
+ return -EINVAL;
+ }
+ pwrcl_clk.acd_avg_cfg2 = array[pwrcl_clk.cluster_num];
+ perfcl_clk.acd_avg_cfg2 = array[perfcl_clk.cluster_num];
+ l3_clk.acd_avg_cfg2 = array[l3_clk.cluster_num];
+ }
+
+ devm_kfree(&pdev->dev, array);
+ return rc;
+}
+
static int clk_osm_parse_dt_configs(struct platform_device *pdev)
{
struct device_node *of = pdev->dev.of_node;
@@ -1938,7 +2313,7 @@
resource_size(res));
if (!l3_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map in l3_sequencer base\n");
+ dev_err(&pdev->dev, "Unable to map l3_sequencer base\n");
return -ENOMEM;
}
@@ -1955,7 +2330,7 @@
resource_size(res));
if (!pwrcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map in pwrcl_sequencer base\n");
+ dev_err(&pdev->dev, "Unable to map pwrcl_sequencer base\n");
return -ENOMEM;
}
@@ -1972,7 +2347,7 @@
resource_size(res));
if (!perfcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map in perfcl_sequencer base\n");
+ dev_err(&pdev->dev, "Unable to map perfcl_sequencer base\n");
return -ENOMEM;
}
@@ -2038,6 +2413,57 @@
return rc;
}
+static int clk_osm_acd_resources_init(struct platform_device *pdev)
+{
+ struct resource *res;
+ unsigned long pbase;
+ void *vbase;
+ int rc = 0;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pwrcl_acd");
+ if (res) {
+ pbase = (unsigned long)res->start;
+ vbase = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!vbase) {
+ dev_err(&pdev->dev, "Unable to map pwrcl_acd base\n");
+ return -ENOMEM;
+ }
+ pwrcl_clk.pbases[ACD_BASE] = pbase;
+ pwrcl_clk.vbases[ACD_BASE] = vbase;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "perfcl_acd");
+ if (res) {
+ pbase = (unsigned long)res->start;
+ vbase = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!vbase) {
+ dev_err(&pdev->dev, "Unable to map perfcl_acd base\n");
+ return -ENOMEM;
+ }
+ perfcl_clk.pbases[ACD_BASE] = pbase;
+ perfcl_clk.vbases[ACD_BASE] = vbase;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "l3_acd");
+ if (res) {
+ pbase = (unsigned long)res->start;
+ vbase = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!vbase) {
+ dev_err(&pdev->dev, "Unable to map l3_acd base\n");
+ return -ENOMEM;
+ }
+ l3_clk.pbases[ACD_BASE] = pbase;
+ l3_clk.vbases[ACD_BASE] = vbase;
+ }
+ return rc;
+}
+
static int clk_osm_resources_init(struct platform_device *pdev)
{
struct device_node *node;
@@ -2059,7 +2485,7 @@
resource_size(res));
if (!l3_clk.vbases[OSM_BASE]) {
- dev_err(&pdev->dev, "Unable to map in osm_l3_base base\n");
+ dev_err(&pdev->dev, "Unable to map osm_l3_base base\n");
return -ENOMEM;
}
@@ -2075,7 +2501,7 @@
pwrcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pwrcl_clk.vbases[OSM_BASE]) {
- dev_err(&pdev->dev, "Unable to map in osm_pwrcl_base base\n");
+ dev_err(&pdev->dev, "Unable to map osm_pwrcl_base base\n");
return -ENOMEM;
}
@@ -2092,7 +2518,7 @@
resource_size(res));
if (!perfcl_clk.vbases[OSM_BASE]) {
- dev_err(&pdev->dev, "Unable to map in osm_perfcl_base base\n");
+ dev_err(&pdev->dev, "Unable to map osm_perfcl_base base\n");
return -ENOMEM;
}
@@ -2169,7 +2595,7 @@
vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!vbase) {
- dev_err(&pdev->dev, "Unable to map in pwrcl_efuse base\n");
+ dev_err(&pdev->dev, "Unable to map pwrcl_efuse base\n");
return -ENOMEM;
}
pwrcl_clk.pbases[EFUSE_BASE] = pbase;
@@ -2183,7 +2609,7 @@
vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!vbase) {
- dev_err(&pdev->dev, "Unable to map in perfcl_efuse base\n");
+ dev_err(&pdev->dev, "Unable to map perfcl_efuse base\n");
return -ENOMEM;
}
perfcl_clk.pbases[EFUSE_BASE] = pbase;
@@ -2259,6 +2685,207 @@
return 0;
}
+static int debugfs_get_debug_reg(void *data, u64 *val)
+{
+ struct clk_osm *c = data;
+
+ if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
+ *val = readl_relaxed((char *)c->vbases[ACD_BASE] +
+ c->acd_debugfs_addr);
+ else
+ *val = clk_osm_acd_local_read_reg(c, c->acd_debugfs_addr);
+ return 0;
+}
+
+static int debugfs_set_debug_reg(void *data, u64 val)
+{
+ struct clk_osm *c = data;
+
+ if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
+ clk_osm_write_reg(c, val, c->acd_debugfs_addr, ACD_BASE);
+ else
+ clk_osm_acd_master_write_through_reg(c, val,
+ c->acd_debugfs_addr);
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_fops,
+ debugfs_get_debug_reg,
+ debugfs_set_debug_reg,
+ "0x%llx\n");
+
+static int debugfs_get_debug_reg_addr(void *data, u64 *val)
+{
+ struct clk_osm *c = data;
+
+ *val = c->acd_debugfs_addr;
+ return 0;
+}
+
+static int debugfs_set_debug_reg_addr(void *data, u64 val)
+{
+ struct clk_osm *c = data;
+
+ if (val > ACD_1P1_MAX_REG_OFFSET) {
+ pr_err("invalid ACD register address offset, must be between 0-0x%x\n",
+ ACD_1P1_MAX_REG_OFFSET);
+ return 0;
+ }
+
+ c->acd_debugfs_addr = val;
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_addr_fops,
+ debugfs_get_debug_reg_addr,
+ debugfs_set_debug_reg_addr,
+ "%llu\n");
+
+static void populate_debugfs_dir(struct clk_osm *c)
+{
+ struct dentry *temp;
+
+ if (osm_debugfs_base == NULL) {
+ osm_debugfs_base = debugfs_create_dir("osm", NULL);
+ if (IS_ERR_OR_NULL(osm_debugfs_base)) {
+ pr_err("osm debugfs base directory creation failed\n");
+ osm_debugfs_base = NULL;
+ return;
+ }
+ }
+
+ c->debugfs = debugfs_create_dir(clk_hw_get_name(&c->hw),
+ osm_debugfs_base);
+ if (IS_ERR_OR_NULL(c->debugfs)) {
+ pr_err("osm debugfs directory creation failed\n");
+ return;
+ }
+
+ temp = debugfs_create_file("acd_debug_reg",
+ 0644,
+ c->debugfs, c,
+ &debugfs_acd_debug_reg_fops);
+ if (IS_ERR_OR_NULL(temp)) {
+ pr_err("debugfs_acd_debug_reg_fops debugfs file creation failed\n");
+ goto exit;
+ }
+
+ temp = debugfs_create_file("acd_debug_reg_addr",
+ 0644,
+ c->debugfs, c,
+ &debugfs_acd_debug_reg_addr_fops);
+ if (IS_ERR_OR_NULL(temp)) {
+ pr_err("debugfs_acd_debug_reg_addr_fops debugfs file creation failed\n");
+ goto exit;
+ }
+
+exit:
+ if (IS_ERR_OR_NULL(temp))
+ debugfs_remove_recursive(c->debugfs);
+}
+
+static int clk_osm_acd_init(struct clk_osm *c)
+{
+
+ int rc = 0;
+ u32 auto_xfer_mask = 0;
+
+ if (c->secure_init) {
+ clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACDCR,
+ DATA_MEM(115), OSM_BASE);
+ clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACD_WRITE_CTL,
+ DATA_MEM(116), OSM_BASE);
+ }
+
+ if (!c->acd_init)
+ return 0;
+
+ c->acd_debugfs_addr = ACD_HW_VERSION;
+
+ /* Program ACD tunable-length delay register */
+ clk_osm_write_reg(c, c->acd_td, ACDTD, ACD_BASE);
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDTD);
+
+ /* Program ACD control register */
+ clk_osm_write_reg(c, c->acd_cr, ACDCR, ACD_BASE);
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDCR);
+
+ /* Program ACD soft start control register */
+ clk_osm_write_reg(c, c->acd_sscr, ACDSSCR, ACD_BASE);
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDSSCR);
+
+ /* Program initial ACD external interface configuration register */
+ clk_osm_write_reg(c, c->acd_extint0_cfg, ACD_EXTINT_CFG, ACD_BASE);
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_EXTINT_CFG);
+
+ /* Program ACD auto-register transfer control register */
+ clk_osm_write_reg(c, c->acd_autoxfer_ctl, ACD_AUTOXFER_CTL, ACD_BASE);
+
+ /* Ensure writes complete before transfers to local copy */
+ clk_osm_acd_mb(c);
+
+ /* Transfer master copies */
+ rc = clk_osm_acd_auto_local_write_reg(c, auto_xfer_mask);
+ if (rc)
+ return rc;
+
+ /* Switch CPUSS clock source to ACD clock */
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_GFMUX_CFG);
+ rc = clk_osm_acd_master_write_through_reg(c, ACD_GFMUX_CFG_SELECT,
+ ACD_GFMUX_CFG);
+ if (rc)
+ return rc;
+
+ /* Program ACD_DCVS_SW */
+ rc = clk_osm_acd_master_write_through_reg(c,
+ ACD_DCVS_SW_DCVS_IN_PRGR_SET,
+ ACD_DCVS_SW);
+ if (rc)
+ return rc;
+
+ rc = clk_osm_acd_master_write_through_reg(c,
+ ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR,
+ ACD_DCVS_SW);
+ if (rc)
+ return rc;
+
+ udelay(1);
+
+ /* Program final ACD external interface configuration register */
+ rc = clk_osm_acd_master_write_through_reg(c, c->acd_extint1_cfg,
+ ACD_EXTINT_CFG);
+ if (rc)
+ return rc;
+
+ if (c->acd_avg_init) {
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_2);
+ rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg2,
+ ACD_AVG_CFG_2);
+ if (rc)
+ return rc;
+
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_1);
+ rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg1,
+ ACD_AVG_CFG_1);
+ if (rc)
+ return rc;
+
+ auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_0);
+ rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg0,
+ ACD_AVG_CFG_0);
+ if (rc)
+ return rc;
+ }
+
+ /*
+ * ACDCR, ACDTD, ACDSSCR, ACD_EXTINT_CFG, ACD_GFMUX_CFG
+ * must be copied from master to local copy on PC exit.
+ * Also, ACD_AVG_CFG0, ACF_AVG_CFG1, and ACD_AVG_CFG2 when
+ * AVG is enabled.
+ */
+ clk_osm_write_reg(c, auto_xfer_mask, ACD_AUTOXFER_CFG, ACD_BASE);
+ return 0;
+}
+
static unsigned long init_rate = 300000000;
static int clk_cpu_osm_driver_probe(struct platform_device *pdev)
@@ -2303,15 +2930,28 @@
rc = clk_osm_parse_dt_configs(pdev);
if (rc) {
- dev_err(&pdev->dev, "Unable to parse device tree configurations\n");
+ dev_err(&pdev->dev, "Unable to parse OSM device tree configurations\n");
+ return rc;
+ }
+
+ rc = clk_osm_parse_acd_dt_configs(pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to parse ACD device tree configurations\n");
return rc;
}
rc = clk_osm_resources_init(pdev);
if (rc) {
if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "resources init failed, rc=%d\n",
- rc);
+ dev_err(&pdev->dev, "OSM resources init failed, rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ rc = clk_osm_acd_resources_init(pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "ACD resources init failed, rc=%d\n",
+ rc);
return rc;
}
@@ -2466,7 +3106,7 @@
/* Program VC at which the array power supply needs to be switched */
clk_osm_write_reg(&perfcl_clk, perfcl_clk.apm_threshold_vc,
- APM_CROSSOVER_VC);
+ APM_CROSSOVER_VC, OSM_BASE);
if (perfcl_clk.secure_init) {
clk_osm_write_seq_reg(&perfcl_clk, perfcl_clk.apm_crossover_vc,
DATA_MEM(77));
@@ -2510,11 +3150,11 @@
if (pwrcl_clk.per_core_dcvs) {
val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
val |= BIT(0);
- clk_osm_write_reg(&pwrcl_clk, val, CORE_DCVS_CTRL);
+ clk_osm_write_reg(&pwrcl_clk, val, CORE_DCVS_CTRL, OSM_BASE);
val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
val |= BIT(0);
- clk_osm_write_reg(&perfcl_clk, val, CORE_DCVS_CTRL);
+ clk_osm_write_reg(&perfcl_clk, val, CORE_DCVS_CTRL, OSM_BASE);
}
clk_ops_core = clk_dummy_ops;
@@ -2522,6 +3162,22 @@
clk_ops_core.round_rate = cpu_clk_round_rate;
clk_ops_core.recalc_rate = cpu_clk_recalc_rate;
+ rc = clk_osm_acd_init(&l3_clk);
+ if (rc) {
+ pr_err("failed to initialize ACD for L3, rc=%d\n", rc);
+ goto exit;
+ }
+ rc = clk_osm_acd_init(&pwrcl_clk);
+ if (rc) {
+ pr_err("failed to initialize ACD for pwrcl, rc=%d\n", rc);
+ goto exit;
+ }
+ rc = clk_osm_acd_init(&perfcl_clk);
+ if (rc) {
+ pr_err("failed to initialize ACD for perfcl, rc=%d\n", rc);
+ goto exit;
+ }
+
spin_lock_init(&l3_clk.lock);
spin_lock_init(&pwrcl_clk.lock);
spin_lock_init(&perfcl_clk.lock);
@@ -2595,6 +3251,9 @@
clk_prepare_enable(perfcl_clk.hw.clk);
populate_opp_table(pdev);
+ populate_debugfs_dir(&l3_clk);
+ populate_debugfs_dir(&pwrcl_clk);
+ populate_debugfs_dir(&perfcl_clk);
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
register_cpu_cycle_counter_cb(&cb);
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
index 1015da8..7671649 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.c
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -27,6 +27,21 @@
#include "sde_crtc.h"
#include "sde_core_perf.h"
+#define SDE_PERF_MODE_STRING_SIZE 128
+
+/**
+ * enum sde_perf_mode - performance tuning mode
+ * @SDE_PERF_MODE_NORMAL: performance controlled by user mode client
+ * @SDE_PERF_MODE_MINIMUM: performance bounded by minimum setting
+ * @SDE_PERF_MODE_FIXED: performance bounded by fixed setting
+ */
+enum sde_perf_mode {
+ SDE_PERF_MODE_NORMAL,
+ SDE_PERF_MODE_MINIMUM,
+ SDE_PERF_MODE_FIXED,
+ SDE_PERF_MODE_MAX
+};
+
static struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
{
struct msm_drm_private *priv;
@@ -72,6 +87,31 @@
return intf_connected;
}
+static void _sde_core_perf_calc_crtc(struct drm_crtc *crtc,
+ struct drm_crtc_state *state,
+ struct sde_core_perf_params *perf)
+{
+ struct sde_crtc_state *sde_cstate;
+
+ if (!crtc || !state || !perf) {
+ SDE_ERROR("invalid parameters\n");
+ return;
+ }
+
+ sde_cstate = to_sde_crtc_state(state);
+ memset(perf, 0, sizeof(struct sde_core_perf_params));
+
+ perf->bw_ctl = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+ perf->max_per_pipe_ib =
+ sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_IB);
+ perf->core_clk_rate =
+ sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_CLK);
+
+ SDE_DEBUG("crtc=%d clk_rate=%llu ib=%llu ab=%llu\n",
+ crtc->base.id, perf->core_clk_rate,
+ perf->max_per_pipe_ib, perf->bw_ctl);
+}
+
int sde_core_perf_crtc_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -100,7 +140,11 @@
sde_cstate = to_sde_crtc_state(state);
- bw_sum_of_intfs = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+ /* swap state and obtain new values */
+ sde_cstate->cur_perf = sde_cstate->new_perf;
+ _sde_core_perf_calc_crtc(crtc, state, &sde_cstate->new_perf);
+
+ bw_sum_of_intfs = sde_cstate->new_perf.bw_ctl;
curr_client_type = sde_crtc_get_client_type(crtc);
drm_for_each_crtc(tmp_crtc, crtc->dev) {
@@ -110,7 +154,7 @@
struct sde_crtc_state *tmp_cstate =
to_sde_crtc_state(tmp_crtc->state);
- bw_sum_of_intfs += tmp_cstate->cur_perf.bw_ctl;
+ bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
}
}
@@ -126,11 +170,11 @@
SDE_DEBUG("final threshold bw limit = %d\n", threshold);
if (!threshold) {
- sde_cstate->cur_perf.bw_ctl = 0;
+ sde_cstate->new_perf = sde_cstate->cur_perf;
SDE_ERROR("no bandwidth limits specified\n");
return -E2BIG;
} else if (bw > threshold) {
- sde_cstate->cur_perf.bw_ctl = 0;
+ sde_cstate->new_perf = sde_cstate->cur_perf;
SDE_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw, threshold);
return -E2BIG;
}
@@ -138,26 +182,6 @@
return 0;
}
-static void _sde_core_perf_calc_crtc(struct sde_kms *kms,
- struct drm_crtc *crtc,
- struct sde_core_perf_params *perf)
-{
- struct sde_crtc_state *sde_cstate;
-
- sde_cstate = to_sde_crtc_state(crtc->state);
- memset(perf, 0, sizeof(struct sde_core_perf_params));
-
- perf->bw_ctl = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
- perf->max_per_pipe_ib =
- sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_IB);
- perf->core_clk_rate =
- sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_CLK);
-
- SDE_DEBUG("crtc=%d clk_rate=%u ib=%llu ab=%llu\n",
- crtc->base.id, perf->core_clk_rate,
- perf->max_per_pipe_ib, perf->bw_ctl);
-}
-
static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
struct drm_crtc *crtc)
{
@@ -175,19 +199,24 @@
sde_cstate = to_sde_crtc_state(tmp_crtc->state);
perf.max_per_pipe_ib = max(perf.max_per_pipe_ib,
- sde_cstate->cur_perf.max_per_pipe_ib);
+ sde_cstate->new_perf.max_per_pipe_ib);
- bw_sum_of_intfs += sde_cstate->cur_perf.bw_ctl;
+ bw_sum_of_intfs += sde_cstate->new_perf.bw_ctl;
SDE_DEBUG("crtc=%d bw=%llu\n",
tmp_crtc->base.id,
- sde_cstate->cur_perf.bw_ctl);
+ sde_cstate->new_perf.bw_ctl);
}
}
bus_ab_quota = max(bw_sum_of_intfs, kms->perf.perf_tune.min_bus_vote);
bus_ib_quota = perf.max_per_pipe_ib;
+ if (kms->perf.perf_tune.mode == SDE_PERF_MODE_FIXED) {
+ bus_ab_quota = kms->perf.fix_core_ab_vote;
+ bus_ib_quota = kms->perf.fix_core_ib_vote;
+ }
+
switch (curr_client_type) {
case NRT_CLIENT:
sde_power_data_bus_set_quota(&priv->phandle, kms->core_client,
@@ -273,22 +302,25 @@
}
}
-static u32 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms)
+static u64 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms)
{
- u32 clk_rate = 0;
+ u64 clk_rate = kms->perf.perf_tune.min_core_clk;
struct drm_crtc *crtc;
struct sde_crtc_state *sde_cstate;
drm_for_each_crtc(crtc, kms->dev) {
if (_sde_core_perf_crtc_is_power_on(crtc)) {
sde_cstate = to_sde_crtc_state(crtc->state);
- clk_rate = max(sde_cstate->cur_perf.core_clk_rate,
+ clk_rate = max(sde_cstate->new_perf.core_clk_rate,
clk_rate);
clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
}
}
- SDE_DEBUG("clk:%u\n", clk_rate);
+ if (kms->perf.perf_tune.mode == SDE_PERF_MODE_FIXED)
+ clk_rate = kms->perf.fix_core_clk_rate;
+
+ SDE_DEBUG("clk:%llu\n", clk_rate);
return clk_rate;
}
@@ -298,7 +330,7 @@
{
struct sde_core_perf_params *new, *old;
int update_bus = 0, update_clk = 0;
- u32 clk_rate = 0;
+ u64 clk_rate = 0;
struct sde_crtc *sde_crtc;
struct sde_crtc_state *sde_cstate;
int ret;
@@ -320,16 +352,13 @@
sde_crtc = to_sde_crtc(crtc);
sde_cstate = to_sde_crtc_state(crtc->state);
- SDE_DEBUG("crtc:%d stop_req:%d core_clk:%u\n",
+ SDE_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
crtc->base.id, stop_req, kms->perf.core_clk_rate);
old = &sde_cstate->cur_perf;
new = &sde_cstate->new_perf;
if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {
- if (params_changed)
- _sde_core_perf_calc_crtc(kms, crtc, new);
-
/*
* cases for bus bandwidth update.
* 1. new bandwidth vote or writeback output vote
@@ -376,13 +405,13 @@
ret = sde_power_clk_set_rate(&priv->phandle,
kms->perf.clk_name, clk_rate);
if (ret) {
- SDE_ERROR("failed to set %s clock rate %u\n",
+ SDE_ERROR("failed to set %s clock rate %llu\n",
kms->perf.clk_name, clk_rate);
return;
}
kms->perf.core_clk_rate = clk_rate;
- SDE_DEBUG("update clk rate = %d HZ\n", clk_rate);
+ SDE_DEBUG("update clk rate = %lld HZ\n", clk_rate);
}
}
@@ -393,7 +422,7 @@
{
struct sde_core_perf *perf = file->private_data;
struct sde_perf_cfg *cfg = &perf->catalog->perf;
- int perf_mode = 0;
+ u32 perf_mode = 0;
char buf[10];
if (!perf)
@@ -407,19 +436,28 @@
buf[count] = 0; /* end of string */
- if (kstrtoint(buf, 0, &perf_mode))
+ if (kstrtouint(buf, 0, &perf_mode))
return -EFAULT;
- if (perf_mode) {
+ if (perf_mode >= SDE_PERF_MODE_MAX)
+ return -EFAULT;
+
+ if (perf_mode == SDE_PERF_MODE_FIXED) {
+ DRM_INFO("fix performance mode\n");
+ } else if (perf_mode == SDE_PERF_MODE_MINIMUM) {
/* run the driver with max clk and BW vote */
perf->perf_tune.min_core_clk = perf->max_core_clk_rate;
perf->perf_tune.min_bus_vote =
(u64) cfg->max_bw_high * 1000;
- } else {
+ DRM_INFO("minimum performance mode\n");
+ } else if (perf_mode == SDE_PERF_MODE_NORMAL) {
/* reset the perf tune params to 0 */
perf->perf_tune.min_core_clk = 0;
perf->perf_tune.min_bus_vote = 0;
+ DRM_INFO("normal performance mode\n");
}
+ perf->perf_tune.mode = perf_mode;
+
return count;
}
@@ -428,7 +466,7 @@
{
struct sde_core_perf *perf = file->private_data;
int len = 0;
- char buf[40] = {'\0'};
+ char buf[SDE_PERF_MODE_STRING_SIZE] = {'\0'};
if (!perf)
return -ENODEV;
@@ -436,7 +474,9 @@
if (*ppos)
return 0; /* the end */
- len = snprintf(buf, sizeof(buf), "min_mdp_clk %lu min_bus_vote %llu\n",
+ len = snprintf(buf, sizeof(buf),
+ "mode %d min_mdp_clk %llu min_bus_vote %llu\n",
+ perf->perf_tune.mode,
perf->perf_tune.min_core_clk,
perf->perf_tune.min_bus_vote);
if (len < 0 || len >= sizeof(buf))
@@ -485,7 +525,7 @@
debugfs_create_u64("max_core_clk_rate", 0644, perf->debugfs_root,
&perf->max_core_clk_rate);
- debugfs_create_u32("core_clk_rate", 0644, perf->debugfs_root,
+ debugfs_create_u64("core_clk_rate", 0644, perf->debugfs_root,
&perf->core_clk_rate);
debugfs_create_u32("enable_bw_release", 0644, perf->debugfs_root,
(u32 *)&perf->enable_bw_release);
@@ -495,6 +535,12 @@
(u32 *)&catalog->perf.max_bw_high);
debugfs_create_file("perf_mode", 0644, perf->debugfs_root,
(u32 *)perf, &sde_core_perf_mode_fops);
+ debugfs_create_u64("fix_core_clk_rate", 0644, perf->debugfs_root,
+ &perf->fix_core_clk_rate);
+ debugfs_create_u64("fix_core_ib_vote", 0644, perf->debugfs_root,
+ &perf->fix_core_ib_vote);
+ debugfs_create_u64("fix_core_ab_vote", 0644, perf->debugfs_root,
+ &perf->fix_core_ab_vote);
return 0;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.h b/drivers/gpu/drm/msm/sde/sde_core_perf.h
index c61c9a7..31851be 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.h
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.h
@@ -34,16 +34,18 @@
struct sde_core_perf_params {
u64 max_per_pipe_ib;
u64 bw_ctl;
- u32 core_clk_rate;
+ u64 core_clk_rate;
};
/**
* struct sde_core_perf_tune - definition of performance tuning control
+ * @mode: performance mode
* @min_core_clk: minimum core clock
* @min_bus_vote: minimum bus vote
*/
struct sde_core_perf_tune {
- unsigned long min_core_clk;
+ u32 mode;
+ u64 min_core_clk;
u64 min_bus_vote;
};
@@ -61,6 +63,9 @@
* @max_core_clk_rate: maximum allowable core clock rate
* @perf_tune: debug control for performance tuning
* @enable_bw_release: debug control for bandwidth release
+ * @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
+ * @fix_core_ib_vote: fixed core ib vote in bps used in mode 2
+ * @fix_core_ab_vote: fixed core ab vote in bps used in mode 2
*/
struct sde_core_perf {
struct drm_device *dev;
@@ -71,10 +76,13 @@
struct sde_power_client *pclient;
char *clk_name;
struct clk *core_clk;
- u32 core_clk_rate;
+ u64 core_clk_rate;
u64 max_core_clk_rate;
struct sde_core_perf_tune perf_tune;
u32 enable_bw_release;
+ u64 fix_core_clk_rate;
+ u64 fix_core_ib_vote;
+ u64 fix_core_ab_vote;
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 4845c43..d80a305 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -731,7 +731,6 @@
struct sde_crtc *sde_crtc;
struct sde_crtc_state *crtc_state;
struct sde_rect *crtc_roi;
- struct drm_clip_rect crtc_clip, *user_rect;
int i, num_attached_conns = 0;
if (!crtc || !state)
@@ -741,12 +740,6 @@
crtc_state = to_sde_crtc_state(state);
crtc_roi = &crtc_state->crtc_roi;
- /* init to invalid range maxes */
- crtc_clip.x1 = ~0;
- crtc_clip.y1 = ~0;
- crtc_clip.x2 = 0;
- crtc_clip.y2 = 0;
-
for_each_connector_in_state(state->state, conn, conn_state, i) {
struct sde_connector_state *sde_conn_state;
@@ -771,36 +764,7 @@
}
}
- /* aggregate all clipping rectangles together for overall crtc roi */
- for (i = 0; i < crtc_state->user_roi_list.num_rects; i++) {
- user_rect = &crtc_state->user_roi_list.roi[i];
-
- crtc_clip.x1 = min(crtc_clip.x1, user_rect->x1);
- crtc_clip.y1 = min(crtc_clip.y1, user_rect->y1);
- crtc_clip.x2 = max(crtc_clip.x2, user_rect->x2);
- crtc_clip.y2 = max(crtc_clip.y2, user_rect->y2);
-
- SDE_DEBUG(
- "%s: conn%d roi%d (%d,%d),(%d,%d) -> crtc (%d,%d),(%d,%d)\n",
- sde_crtc->name, DRMID(crtc), i,
- user_rect->x1, user_rect->y1,
- user_rect->x2, user_rect->y2,
- crtc_clip.x1, crtc_clip.y1,
- crtc_clip.x2, crtc_clip.y2);
-
- }
-
- if (crtc_clip.x2 && crtc_clip.y2) {
- crtc_roi->x = crtc_clip.x1;
- crtc_roi->y = crtc_clip.y1;
- crtc_roi->w = crtc_clip.x2 - crtc_clip.x1;
- crtc_roi->h = crtc_clip.y2 - crtc_clip.y1;
- } else {
- crtc_roi->x = 0;
- crtc_roi->y = 0;
- crtc_roi->w = 0;
- crtc_roi->h = 0;
- }
+ sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
@@ -1399,6 +1363,7 @@
struct sde_crtc_frame_event *fevent;
struct drm_crtc *crtc;
struct sde_crtc *sde_crtc;
+ struct sde_crtc_state *cstate;
struct sde_kms *sde_kms;
unsigned long flags;
@@ -1408,13 +1373,14 @@
}
fevent = container_of(work, struct sde_crtc_frame_event, work);
- if (!fevent->crtc) {
+ if (!fevent->crtc || !fevent->crtc->state) {
SDE_ERROR("invalid crtc\n");
return;
}
crtc = fevent->crtc;
sde_crtc = to_sde_crtc(crtc);
+ cstate = to_sde_crtc_state(crtc->state);
sde_kms = _sde_crtc_get_kms(crtc);
if (!sde_kms) {
@@ -1453,6 +1419,9 @@
SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
SDE_EVTLOG_FUNC_CASE3);
}
+
+ if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE)
+ sde_core_perf_crtc_update(crtc, 0, false);
} else {
SDE_ERROR("crtc%d ts:%lld unknown event %u\n", crtc->base.id,
ktime_to_ns(fevent->ts),
@@ -3233,7 +3202,7 @@
seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc));
seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
- seq_printf(s, "core_clk_rate: %u\n", cstate->cur_perf.core_clk_rate);
+ seq_printf(s, "core_clk_rate: %llu\n", cstate->cur_perf.core_clk_rate);
seq_printf(s, "max_per_pipe_ib: %llu\n",
cstate->cur_perf.max_per_pipe_ib);
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index ec5ec1d..6a22115 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -420,6 +420,19 @@
}
/**
+ * sde_crtc_get_inline_prefill - get current inline rotation prefill
+ * @crtc: Pointer to crtc
+ * return: number of prefill lines
+ */
+static inline u32 sde_crtc_get_inline_prefill(struct drm_crtc *crtc)
+{
+ if (!crtc || !crtc->state)
+ return 0;
+
+ return to_sde_crtc_state(crtc->state)->sbuf_prefill_line;
+}
+
+/**
* sde_crtc_event_queue - request event callback
* @crtc: Pointer to drm crtc structure
* @func: Pointer to callback function
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 39127e0..f11ba51 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -154,6 +154,7 @@
* clks and resources after IDLE_TIMEOUT time.
* @topology: topology of the display
* @mode_set_complete: flag to indicate modeset completion
+ * @rsc_cfg: rsc configuration
*/
struct sde_encoder_virt {
struct drm_encoder base;
@@ -192,6 +193,8 @@
struct delayed_work delayed_off_work;
struct msm_display_topology topology;
bool mode_set_complete;
+
+ struct sde_encoder_rsc_config rsc_cfg;
};
#define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
@@ -760,7 +763,8 @@
}
static int sde_encoder_update_rsc_client(
- struct drm_encoder *drm_enc, bool enable)
+ struct drm_encoder *drm_enc,
+ struct sde_encoder_rsc_config *config, bool enable)
{
struct sde_encoder_virt *sde_enc;
enum sde_rsc_state rsc_state;
@@ -791,14 +795,22 @@
disp_info->is_primary) ? SDE_RSC_CMD_STATE :
SDE_RSC_VID_STATE) : SDE_RSC_IDLE_STATE;
+ if (config && memcmp(&sde_enc->rsc_cfg, config,
+ sizeof(sde_enc->rsc_cfg)))
+ sde_enc->rsc_state_init = false;
+
if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
&& disp_info->is_primary) {
rsc_config.fps = disp_info->frame_rate;
rsc_config.vtotal = disp_info->vtotal;
rsc_config.prefill_lines = disp_info->prefill_lines;
rsc_config.jitter = disp_info->jitter;
+ rsc_config.prefill_lines += config ?
+ config->inline_rotate_prefill : 0;
/* update it only once */
sde_enc->rsc_state_init = true;
+ if (config)
+ sde_enc->rsc_cfg = *config;
ret = sde_rsc_client_state_update(sde_enc->rsc_client,
rsc_state, &rsc_config,
@@ -835,6 +847,7 @@
struct msm_drm_private *priv;
struct sde_kms *sde_kms;
struct sde_encoder_virt *sde_enc;
+ struct sde_encoder_rsc_config rsc_cfg = { 0 };
int i;
sde_enc = to_sde_encoder_virt(drm_enc);
@@ -865,13 +878,16 @@
phys->ops.irq_control(phys, true);
}
+ rsc_cfg.inline_rotate_prefill =
+ sde_crtc_get_inline_prefill(drm_enc->crtc);
+
/* enable RSC */
- sde_encoder_update_rsc_client(drm_enc, true);
+ sde_encoder_update_rsc_client(drm_enc, &rsc_cfg, true);
} else {
/* disable RSC */
- sde_encoder_update_rsc_client(drm_enc, false);
+ sde_encoder_update_rsc_client(drm_enc, NULL, false);
/* disable all the irq */
for (i = 0; i < sde_enc->num_phys_encs; i++) {
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index b756313..7292a12 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -57,6 +57,14 @@
};
/**
+ * sde_encoder_rsc_config - rsc configuration for encoder
+ * @inline_rotate_prefill: number of lines to prefill for inline rotation
+ */
+struct sde_encoder_rsc_config {
+ u32 inline_rotate_prefill;
+};
+
+/**
* sde_encoder_get_hw_resources - Populate table of required hardware resources
* @encoder: encoder pointer
* @hw_res: resource table to populate with encoder required resources
@@ -141,24 +149,6 @@
void sde_encoder_virt_restore(struct drm_encoder *encoder);
/**
- * enum sde_encoder_property - property tags for sde enoder
- * @SDE_ENCODER_PROPERTY_INLINE_ROTATE_REFILL: # of prefill line, 0 to disable
- */
-enum sde_encoder_property {
- SDE_ENCODER_PROPERTY_INLINE_ROTATE_PREFILL,
- SDE_ENCODER_PROPERTY_MAX,
-};
-
-/*
- * sde_encoder_set_property - set the property tag to the given value
- * @encoder: Pointer to drm encoder object
- * @tag: property tag
- * @val: property value
- * return: 0 if success; errror code otherwise
- */
-int sde_encoder_set_property(struct drm_encoder *encoder, u32 tag, u64 val);
-
-/**
* sde_encoder_init - initialize virtual encoder object
* @dev: Pointer to drm device structure
* @disp_info: Pointer to display information structure
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 5118a79..1faa46e2 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -528,37 +528,6 @@
* static API list
*************************************************************/
-/**
- * _sde_copy_formats - copy formats from src_list to dst_list
- * @dst_list: pointer to destination list where to copy formats
- * @dst_list_size: size of destination list
- * @dst_list_pos: starting position on the list where to copy formats
- * @src_list: pointer to source list where to copy formats from
- * @src_list_size: size of source list
- * Return: number of elements populated
- */
-static uint32_t _sde_copy_formats(
- struct sde_format_extended *dst_list,
- uint32_t dst_list_size,
- uint32_t dst_list_pos,
- const struct sde_format_extended *src_list,
- uint32_t src_list_size)
-{
- uint32_t cur_pos, i;
-
- if (!dst_list || !src_list || (dst_list_pos >= (dst_list_size - 1)))
- return 0;
-
- for (i = 0, cur_pos = dst_list_pos;
- (cur_pos < (dst_list_size - 1)) && (i < src_list_size)
- && src_list[i].fourcc_format; ++i, ++cur_pos)
- dst_list[cur_pos] = src_list[i];
-
- dst_list[cur_pos].fourcc_format = 0;
-
- return i;
-}
-
static int _parse_dt_u32_handler(struct device_node *np,
char *prop_name, u32 *offsets, int len, bool mandatory)
{
@@ -1513,7 +1482,13 @@
wb->clk_ctrl = SDE_CLK_CTRL_WB0 +
PROP_VALUE_ACCESS(prop_value, WB_ID, i);
wb->xin_id = PROP_VALUE_ACCESS(prop_value, WB_XIN_ID, i);
- wb->vbif_idx = VBIF_NRT;
+
+ if (IS_SDE_MAJOR_MINOR_SAME((sde_cfg->hwversion),
+ SDE_HW_VER_170))
+ wb->vbif_idx = VBIF_NRT;
+ else
+ wb->vbif_idx = VBIF_RT;
+
wb->len = PROP_VALUE_ACCESS(prop_value, WB_LEN, 0);
if (!prop_exists[WB_LEN])
wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
@@ -2439,7 +2414,7 @@
rc = -ENOMEM;
goto end;
}
- index = _sde_copy_formats(sde_cfg->cursor_formats,
+ index = sde_copy_formats(sde_cfg->cursor_formats,
cursor_list_size, 0, cursor_formats,
ARRAY_SIZE(cursor_formats));
}
@@ -2480,34 +2455,34 @@
goto end;
}
- index = _sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
+ index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
0, plane_formats, ARRAY_SIZE(plane_formats));
- index += _sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
+ index += sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
index, rgb_10bit_formats,
ARRAY_SIZE(rgb_10bit_formats));
- index = _sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
+ index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
0, plane_formats_yuv, ARRAY_SIZE(plane_formats_yuv));
- index += _sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
+ index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
index, rgb_10bit_formats,
ARRAY_SIZE(rgb_10bit_formats));
- index += _sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
+ index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
index, p010_formats, ARRAY_SIZE(p010_formats));
if (IS_SDE_MAJOR_MINOR_SAME((hw_rev), SDE_HW_VER_400))
- index += _sde_copy_formats(sde_cfg->vig_formats,
+ index += sde_copy_formats(sde_cfg->vig_formats,
vig_list_size, index, p010_ubwc_formats,
ARRAY_SIZE(p010_ubwc_formats));
- index += _sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
+ index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
index, tp10_ubwc_formats,
ARRAY_SIZE(tp10_ubwc_formats));
- index = _sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
+ index = sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
0, wb2_formats, ARRAY_SIZE(wb2_formats));
- index += _sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
+ index += sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
index, rgb_10bit_formats,
ARRAY_SIZE(rgb_10bit_formats));
- index += _sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
+ index += sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
index, tp10_ubwc_formats,
ARRAY_SIZE(tp10_ubwc_formats));
end:
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.c b/drivers/gpu/drm/msm/sde/sde_hw_util.c
index b899f0c..7df5736 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.c
@@ -91,3 +91,33 @@
SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
}
+/**
+ * _sde_copy_formats - copy formats from src_list to dst_list
+ * @dst_list: pointer to destination list where to copy formats
+ * @dst_list_size: size of destination list
+ * @dst_list_pos: starting position on the list where to copy formats
+ * @src_list: pointer to source list where to copy formats from
+ * @src_list_size: size of source list
+ * Return: number of elements populated
+ */
+uint32_t sde_copy_formats(
+ struct sde_format_extended *dst_list,
+ uint32_t dst_list_size,
+ uint32_t dst_list_pos,
+ const struct sde_format_extended *src_list,
+ uint32_t src_list_size)
+{
+ uint32_t cur_pos, i;
+
+ if (!dst_list || !src_list || (dst_list_pos >= (dst_list_size - 1)))
+ return 0;
+
+ for (i = 0, cur_pos = dst_list_pos;
+ (cur_pos < (dst_list_size - 1)) && (i < src_list_size)
+ && src_list[i].fourcc_format; ++i, ++cur_pos)
+ dst_list[cur_pos] = src_list[i];
+
+ dst_list[cur_pos].fourcc_format = 0;
+
+ return i;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_util.h b/drivers/gpu/drm/msm/sde/sde_hw_util.h
index c1bfb79..8f469b2 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_util.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_util.h
@@ -17,6 +17,8 @@
#include <linux/slab.h>
#include "sde_hw_mdss.h"
+struct sde_format_extended;
+
/*
* This is the common struct maintained by each sub block
* for mapping the register offsets in this block to the
@@ -59,5 +61,11 @@
u32 csc_reg_off,
struct sde_csc_cfg *data, bool csc10);
-#endif /* _SDE_HW_UTIL_H */
+uint32_t sde_copy_formats(
+ struct sde_format_extended *dst_list,
+ uint32_t dst_list_size,
+ uint32_t dst_list_pos,
+ const struct sde_format_extended *src_list,
+ uint32_t src_list_size);
+#endif /* _SDE_HW_UTIL_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.h b/drivers/gpu/drm/msm/sde/sde_kms.h
index 01a5535..1f56d73 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.h
+++ b/drivers/gpu/drm/msm/sde/sde_kms.h
@@ -407,6 +407,14 @@
struct sde_rect *result);
/**
+ * sde_kms_rect_merge_rectangles - merge a rectangle list into one rect
+ * @rois: pointer to the list of rois
+ * @result: output rectangle, all 0 on error
+ */
+void sde_kms_rect_merge_rectangles(const struct msm_roi_list *rois,
+ struct sde_rect *result);
+
+/**
* sde_kms_rect_is_equal - compares two rects
* @r1: rect value to compare
* @r2: rect value to compare
diff --git a/drivers/gpu/drm/msm/sde/sde_kms_utils.c b/drivers/gpu/drm/msm/sde/sde_kms_utils.c
index b956be5..dcc0bd5 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms_utils.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms_utils.c
@@ -175,3 +175,46 @@
result->h = b - t;
}
}
+
+void sde_kms_rect_merge_rectangles(const struct msm_roi_list *rois,
+ struct sde_rect *result)
+{
+ struct drm_clip_rect clip;
+ const struct drm_clip_rect *roi_rect;
+ int i;
+
+ if (!rois || !result)
+ return;
+
+ memset(result, 0, sizeof(*result));
+
+ /* init to invalid range maxes */
+ clip.x1 = ~0;
+ clip.y1 = ~0;
+ clip.x2 = 0;
+ clip.y2 = 0;
+
+ /* aggregate all clipping rectangles together for overall roi */
+ for (i = 0; i < rois->num_rects; i++) {
+ roi_rect = &rois->roi[i];
+
+ clip.x1 = min(clip.x1, roi_rect->x1);
+ clip.y1 = min(clip.y1, roi_rect->y1);
+ clip.x2 = max(clip.x2, roi_rect->x2);
+ clip.y2 = max(clip.y2, roi_rect->y2);
+
+ SDE_DEBUG("roi%d (%d,%d),(%d,%d) -> crtc (%d,%d),(%d,%d)\n", i,
+ roi_rect->x1, roi_rect->y1,
+ roi_rect->x2, roi_rect->y2,
+ clip.x1, clip.y1,
+ clip.x2, clip.y2);
+ }
+
+ if (clip.x2 && clip.y2) {
+ result->x = clip.x1;
+ result->y = clip.y1;
+ result->w = clip.x2 - clip.x1;
+ result->h = clip.y2 - clip.y1;
+ }
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index cf03a47..deca83e 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -3028,6 +3028,7 @@
{SDE_DRM_DEINTERLACE, "deinterlace"}
};
const struct sde_format_extended *format_list;
+ struct sde_format_extended *virt_format_list = NULL;
struct sde_kms_info *info;
struct sde_plane *psde = to_sde_plane(plane);
int zpos_max = 255;
@@ -3166,9 +3167,28 @@
format_list = psde->pipe_sblk->format_list;
if (master_plane_id) {
+ int index, array_size;
+
+ array_size = ARRAY_SIZE(plane_formats)
+ + ARRAY_SIZE(rgb_10bit_formats);
+ virt_format_list = kcalloc(array_size,
+ sizeof(struct sde_format_extended), GFP_KERNEL);
+ if (!virt_format_list) {
+ SDE_ERROR(
+ "failed to allocate virtual pipe format list\n");
+ return;
+ }
+
+ index = sde_copy_formats(virt_format_list, array_size,
+ 0, plane_formats, ARRAY_SIZE(plane_formats));
+ sde_copy_formats(virt_format_list, array_size,
+ index, rgb_10bit_formats,
+ ARRAY_SIZE(rgb_10bit_formats));
+
+ format_list = virt_format_list;
+
sde_kms_info_add_keyint(info, "primary_smart_plane_id",
- master_plane_id);
- format_list = plane_formats;
+ master_plane_id);
}
if (format_list) {
@@ -3198,6 +3218,7 @@
info->data, info->len, PLANE_PROP_INFO);
kfree(info);
+ kfree(virt_format_list);
if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
snprintf(feature_name, sizeof(feature_name), "%s%d",
@@ -3915,6 +3936,7 @@
{
struct drm_plane *plane = NULL;
const struct sde_format_extended *format_list;
+ struct sde_format_extended *virt_format_list = NULL;
struct sde_plane *psde;
struct msm_drm_private *priv;
struct sde_kms *kms;
@@ -3989,8 +4011,28 @@
format_list = psde->pipe_sblk->format_list;
- if (master_plane_id)
- format_list = plane_formats;
+ if (master_plane_id) {
+ int index, array_size;
+
+ array_size = ARRAY_SIZE(plane_formats)
+ + ARRAY_SIZE(rgb_10bit_formats);
+ virt_format_list = kcalloc(array_size,
+ sizeof(struct sde_format_extended),
+ GFP_KERNEL);
+ if (!virt_format_list) {
+ SDE_ERROR(
+ "failed to allocate virtual pipe format list\n");
+ goto clean_sspp;
+ }
+
+ index = sde_copy_formats(virt_format_list, array_size,
+ 0, plane_formats, ARRAY_SIZE(plane_formats));
+ sde_copy_formats(virt_format_list, array_size,
+ index, rgb_10bit_formats,
+ ARRAY_SIZE(rgb_10bit_formats));
+
+ format_list = virt_format_list;
+ }
psde->nformats = sde_populate_formats(format_list,
psde->formats,
@@ -4041,5 +4083,6 @@
clean_plane:
kfree(psde);
exit:
+ kfree(virt_format_list);
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/sde_power_handle.h b/drivers/gpu/drm/msm/sde_power_handle.h
index d753f0a..da68139 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.h
+++ b/drivers/gpu/drm/msm/sde_power_handle.h
@@ -16,9 +16,9 @@
#define MAX_CLIENT_NAME_LEN 128
-#define SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 2000000000
+#define SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 2000000
#define SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA 0
-#define SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 2000000000
+#define SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 2000000
#define SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0
#include <linux/sde_io_util.h>
diff --git a/drivers/gpu/drm/msm/sde_rsc.c b/drivers/gpu/drm/msm/sde_rsc.c
index 3413ee7..50710cd 100644
--- a/drivers/gpu/drm/msm/sde_rsc.c
+++ b/drivers/gpu/drm/msm/sde_rsc.c
@@ -416,6 +416,11 @@
if (config)
sde_rsc_timer_calculate(rsc, config);
+ if (rsc->current_state == SDE_RSC_CMD_STATE) {
+ rc = 0;
+ goto vsync_wait;
+ }
+
/* any one client in video state blocks the cmd state switch */
list_for_each_entry(client, &rsc->client_list, list)
if (client->current_state == SDE_RSC_VID_STATE)
@@ -427,8 +432,10 @@
rpmh_mode_solver_set(rsc->disp_rsc, true);
}
- /* wait for vsync for vid to cmd state switch */
- if (!rc && (rsc->current_state == SDE_RSC_VID_STATE))
+vsync_wait:
+ /* wait for vsync for vid to cmd state switch and config update */
+ if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
+ rsc->current_state == SDE_RSC_CMD_STATE))
drm_wait_one_vblank(rsc->master_drm,
rsc->primary_client->crtc_id);
end:
@@ -470,6 +477,10 @@
if (config && (caller_client == rsc->primary_client))
sde_rsc_timer_calculate(rsc, config);
+ /* early exit without vsync wait for vid state */
+ if (rsc->current_state == SDE_RSC_VID_STATE)
+ goto end;
+
/* video state switch should be done immediately */
if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_VID_STATE);
@@ -482,6 +493,8 @@
(rsc->current_state == SDE_RSC_CMD_STATE))
drm_wait_one_vblank(rsc->master_drm,
rsc->primary_client->crtc_id);
+
+end:
return rc;
}
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 475ea75..9bdde0b 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -940,8 +940,6 @@
int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
{
unsigned long flags;
- dma_addr_t paddr;
- void __iomem *vaddr = NULL;
/* config types are set a boot time and never change */
if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
@@ -959,21 +957,12 @@
*/
tmc_etr_enable_hw(drvdata);
} else {
- /*
- * The ETR is not tracing and the buffer was just read.
- * As such prepare to free the trace buffer.
- */
- vaddr = drvdata->vaddr;
- paddr = drvdata->paddr;
- drvdata->buf = drvdata->vaddr = NULL;
+ tmc_etr_free_mem(drvdata);
+ drvdata->buf = NULL;
}
drvdata->reading = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- /* Free allocated memory out side of the spinlock */
- if (vaddr)
- dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr);
-
return 0;
}
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 58e8850..622ccbc 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -20,6 +20,7 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/qcom-geni-se.h>
@@ -50,9 +51,12 @@
#define SLV_ADDR_MSK (GENMASK(15, 9))
#define SLV_ADDR_SHFT (9)
+#define I2C_CORE2X_VOTE (10000)
+
struct geni_i2c_dev {
struct device *dev;
void __iomem *base;
+ unsigned int tx_wm;
int irq;
int err;
struct i2c_adapter adap;
@@ -61,6 +65,7 @@
struct se_geni_rsc i2c_rsc;
int cur_wr;
int cur_rd;
+ struct device *wrapper_dev;
};
static inline void qcom_geni_i2c_conf(void __iomem *base, int dfs, int div)
@@ -114,7 +119,7 @@
}
} else if ((m_stat & M_TX_FIFO_WATERMARK_EN) &&
!(cur->flags & I2C_M_RD)) {
- for (j = 0; j < 0x1f; j++) {
+ for (j = 0; j < gi2c->tx_wm; j++) {
u32 temp = 0;
int p;
@@ -163,9 +168,7 @@
pm_runtime_set_suspended(gi2c->dev);
return ret;
}
- geni_se_init(gi2c->base, FIFO_MODE, 0xF, 0x10);
qcom_geni_i2c_conf(gi2c->base, 0, 2);
- se_config_packing(gi2c->base, 8, 4, true);
dev_dbg(gi2c->dev, "i2c xfer:num:%d, msgs:len:%d,flg:%d\n",
num, msgs[0].len, msgs[0].flags);
for (i = 0; i < num; i++) {
@@ -237,6 +240,8 @@
{
struct geni_i2c_dev *gi2c;
struct resource *res;
+ struct platform_device *wrapper_pdev;
+ struct device_node *wrapper_ph_node;
int ret;
gi2c = devm_kzalloc(&pdev->dev, sizeof(*gi2c), GFP_KERNEL);
@@ -249,6 +254,29 @@
if (!res)
return -EINVAL;
+ wrapper_ph_node = of_parse_phandle(pdev->dev.of_node,
+ "qcom,wrapper-core", 0);
+ if (IS_ERR_OR_NULL(wrapper_ph_node)) {
+ ret = PTR_ERR(wrapper_ph_node);
+ dev_err(&pdev->dev, "No wrapper core defined\n");
+ return ret;
+ }
+ wrapper_pdev = of_find_device_by_node(wrapper_ph_node);
+ of_node_put(wrapper_ph_node);
+ if (IS_ERR_OR_NULL(wrapper_pdev)) {
+ ret = PTR_ERR(wrapper_pdev);
+ dev_err(&pdev->dev, "Cannot retrieve wrapper device\n");
+ return ret;
+ }
+ gi2c->wrapper_dev = &wrapper_pdev->dev;
+ gi2c->i2c_rsc.wrapper_dev = &wrapper_pdev->dev;
+ ret = geni_se_resources_init(&gi2c->i2c_rsc, I2C_CORE2X_VOTE,
+ (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH));
+ if (ret) {
+ dev_err(gi2c->dev, "geni_se_resources_init\n");
+ return ret;
+ }
+
gi2c->i2c_rsc.se_clk = devm_clk_get(&pdev->dev, "se-clk");
if (IS_ERR(gi2c->i2c_rsc.se_clk)) {
ret = PTR_ERR(gi2c->i2c_rsc.se_clk);
@@ -360,6 +388,14 @@
if (ret)
return ret;
+ if (unlikely(!gi2c->tx_wm)) {
+ int gi2c_tx_depth = get_tx_fifo_depth(gi2c->base);
+
+ gi2c->tx_wm = gi2c_tx_depth - 1;
+ geni_se_init(gi2c->base, gi2c->tx_wm, gi2c_tx_depth);
+ geni_se_select_mode(gi2c->base, FIFO_MODE);
+ se_config_packing(gi2c->base, 8, 4, true);
+ }
enable_irq(gi2c->irq);
return 0;
}
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index fbab1f1..d52b534 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -421,7 +421,6 @@
config IOMMU_DEBUG_TRACKING
bool "Track key IOMMU events"
- depends on BROKEN
select IOMMU_API
help
Enables additional debug tracking in the IOMMU framework code.
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index c5ab866..2db0d64 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -432,13 +432,12 @@
return ret;
}
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, int prot)
+static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
+ size_t size, int prot)
{
dma_addr_t dma_addr;
struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
struct iova_domain *iovad = cookie_iovad(domain);
- phys_addr_t phys = page_to_phys(page) + offset;
size_t iova_off = iova_offset(iovad, phys);
size_t len = iova_align(iovad, size + iova_off);
struct iova *iova = __alloc_iova(domain, len, dma_get_mask(dev));
@@ -454,6 +453,12 @@
return dma_addr + iova_off;
}
+dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size, int prot)
+{
+ return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot);
+}
+
void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
enum dma_data_direction dir, unsigned long attrs)
{
@@ -624,6 +629,19 @@
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), sg_dma_address(sg));
}
+dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+ return __iommu_dma_map(dev, phys, size,
+ dma_direction_to_prot(dir, false) | IOMMU_MMIO);
+}
+
+void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+ __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle);
+}
+
int iommu_dma_supported(struct device *dev, u64 mask)
{
/*
diff --git a/drivers/iommu/dma-mapping-fast.c b/drivers/iommu/dma-mapping-fast.c
index 8ba6da4..ac3059d 100644
--- a/drivers/iommu/dma-mapping-fast.c
+++ b/drivers/iommu/dma-mapping-fast.c
@@ -611,6 +611,55 @@
return ret;
}
+static dma_addr_t fast_smmu_dma_map_resource(
+ struct device *dev, phys_addr_t phys_addr,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ struct dma_fast_smmu_mapping *mapping = dev->archdata.mapping->fast;
+ size_t offset = phys_addr & ~FAST_PAGE_MASK;
+ size_t len = round_up(size + offset, FAST_PAGE_SIZE);
+ dma_addr_t dma_addr;
+ int prot;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mapping->lock, flags);
+ dma_addr = __fast_smmu_alloc_iova(mapping, attrs, len);
+ spin_unlock_irqrestore(&mapping->lock, flags);
+
+ if (dma_addr == DMA_ERROR_CODE)
+ return dma_addr;
+
+ prot = __fast_dma_direction_to_prot(dir);
+ prot |= IOMMU_MMIO;
+
+ if (iommu_map(mapping->domain, dma_addr, phys_addr - offset,
+ len, prot)) {
+ spin_lock_irqsave(&mapping->lock, flags);
+ __fast_smmu_free_iova(mapping, dma_addr, len);
+ spin_unlock_irqrestore(&mapping->lock, flags);
+ return DMA_ERROR_CODE;
+ }
+ return dma_addr + offset;
+}
+
+static void fast_smmu_dma_unmap_resource(
+ struct device *dev, dma_addr_t addr,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ struct dma_fast_smmu_mapping *mapping = dev->archdata.mapping->fast;
+ size_t offset = addr & ~FAST_PAGE_MASK;
+ size_t len = round_up(size + offset, FAST_PAGE_SIZE);
+ unsigned long flags;
+
+ iommu_unmap(mapping->domain, addr - offset, len);
+ spin_lock_irqsave(&mapping->lock, flags);
+ __fast_smmu_free_iova(mapping, addr, len);
+ spin_unlock_irqrestore(&mapping->lock, flags);
+}
+
+
static int fast_smmu_dma_supported(struct device *dev, u64 mask)
{
return mask <= 0xffffffff;
@@ -667,6 +716,8 @@
.unmap_sg = fast_smmu_unmap_sg,
.sync_sg_for_cpu = fast_smmu_sync_sg_for_cpu,
.sync_sg_for_device = fast_smmu_sync_sg_for_device,
+ .map_resource = fast_smmu_dma_map_resource,
+ .unmap_resource = fast_smmu_dma_unmap_resource,
.dma_supported = fast_smmu_dma_supported,
.mapping_error = fast_smmu_mapping_error,
};
diff --git a/drivers/media/platform/msm/camera/cam_utils/Makefile b/drivers/media/platform/msm/camera/cam_utils/Makefile
index 6f9525e..f22115c 100644
--- a/drivers/media/platform/msm/camera/cam_utils/Makefile
+++ b/drivers/media/platform/msm/camera/cam_utils/Makefile
@@ -1 +1,3 @@
-obj-$(CONFIG_SPECTRA_CAMERA) += cam_soc_util.o cam_io_util.o
+ccflags-y += -Idrivers/media/platform/msm/camera/cam_req_mgr/
+
+obj-$(CONFIG_SPECTRA_CAMERA) += cam_soc_util.o cam_io_util.o cam_packet_util.o
diff --git a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c
new file mode 100644
index 0000000..6d90c1e
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c
@@ -0,0 +1,78 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include "cam_mem_mgr.h"
+#include "cam_packet_util.h"
+
+#undef CDBG
+#define CDBG(fmt, args...) pr_debug(fmt, ##args)
+
+int cam_packet_util_process_patches(struct cam_packet *packet,
+ int32_t iommu_hdl)
+{
+ struct cam_patch_desc *patch_desc = NULL;
+ uint64_t iova_addr;
+ uint64_t cpu_addr;
+ uint32_t temp;
+ uint32_t *dst_cpu_addr;
+ uint32_t *src_buf_iova_addr;
+ size_t dst_buf_len;
+ size_t src_buf_size;
+ int i;
+ int rc = 0;
+
+ /* process patch descriptor */
+ patch_desc = (struct cam_patch_desc *)
+ ((uint32_t *) &packet->payload +
+ packet->patch_offset/4);
+ CDBG("packet = %pK patch_desc = %pK size = %lu\n",
+ (void *)packet, (void *)patch_desc,
+ sizeof(struct cam_patch_desc));
+
+ for (i = 0; i < packet->num_patches; i++) {
+ rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl,
+ iommu_hdl, &iova_addr, &src_buf_size);
+ if (rc < 0) {
+ pr_err("unable to get src buf address\n");
+ return rc;
+ }
+ src_buf_iova_addr = (uint32_t *)iova_addr;
+ temp = iova_addr;
+
+ rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
+ &cpu_addr, &dst_buf_len);
+ if (rc < 0) {
+ pr_err("unable to get dst buf address\n");
+ return rc;
+ }
+ dst_cpu_addr = (uint32_t *)cpu_addr;
+
+ CDBG("i = %d patch info = %x %x %x %x\n", i,
+ patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset,
+ patch_desc[i].src_buf_hdl, patch_desc[i].src_offset);
+
+ dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
+ patch_desc[i].dst_offset);
+ temp += patch_desc[i].src_offset;
+
+ *dst_cpu_addr = temp;
+
+ CDBG("patch is done for dst %pK with src %pK value %llx\n",
+ dst_cpu_addr, src_buf_iova_addr,
+ *((uint64_t *)dst_cpu_addr));
+ }
+
+ return rc;
+}
+
diff --git a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h
new file mode 100644
index 0000000..614e868
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_PACKET_UTIL_H_
+#define _CAM_PACKET_UTIL_H_
+
+#include <uapi/media/cam_defs.h>
+
+/**
+ * cam_packet_util_process_patches()
+ *
+ * @brief: Replace the handle in Packet to Address using the
+ * information from patches.
+ *
+ * @packet: Input packet containing Command Buffers and Patches
+ * @iommu_hdl: IOMMU handle of the HW Device that received the packet
+ *
+ * @return: 0: Success
+ * Negative: Failure
+ */
+int cam_packet_util_process_patches(struct cam_packet *packet,
+ int32_t iommu_hdl);
+
+#endif /* _CAM_PACKET_UTIL_H_ */
diff --git a/drivers/media/platform/msm/camera/icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/media/platform/msm/camera/icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
index 489ded1..2fa39c8 100644
--- a/drivers/media/platform/msm/camera/icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
+++ b/drivers/media/platform/msm/camera/icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
@@ -27,6 +27,7 @@
#include <media/cam_defs.h>
#include <media/cam_icp.h>
#include "cam_sync_api.h"
+#include "cam_packet_util.h"
#include "cam_hw.h"
#include "cam_hw_mgr_intf.h"
#include "cam_icp_hw_mgr_intf.h"
@@ -1175,14 +1176,9 @@
int ctx_id = 0;
uint32_t fw_handle;
int32_t idx;
- uint64_t iova_addr, cpu_addr;
+ uint64_t iova_addr;
uint32_t fw_cmd_buf_iova_addr;
- uint32_t temp;
- uint32_t *dst_cpu_addr;
- uint32_t *src_buf_iova_addr;
size_t fw_cmd_buf_len;
- size_t dst_buf_len;
- size_t src_buf_size;
int32_t sync_in_obj[CAM_ICP_IPE_IMAGE_MAX];
int32_t merged_sync_in_obj;
@@ -1194,7 +1190,6 @@
struct cam_packet *packet = NULL;
struct cam_cmd_buf_desc *cmd_desc = NULL;
struct cam_buf_io_cfg *io_cfg_ptr = NULL;
- struct cam_patch_desc *patch_desc = NULL;
struct hfi_cmd_ipebps_async *hfi_cmd = NULL;
if ((!prepare_args) || (!hw_mgr)) {
@@ -1279,45 +1274,11 @@
fw_cmd_buf_iova_addr = iova_addr;
fw_cmd_buf_iova_addr = (fw_cmd_buf_iova_addr + cmd_desc->offset);
- /* process patch descriptor */
- patch_desc = (struct cam_patch_desc *)
- ((uint32_t *) &packet->payload +
- packet->patch_offset/4);
- ICP_DBG("packet = %pK patch_desc = %pK size = %lu\n",
- (void *)packet, (void *)patch_desc,
- sizeof(struct cam_patch_desc));
-
- for (i = 0; i < packet->num_patches; i++) {
- rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl,
- hw_mgr->iommu_hdl, &iova_addr, &src_buf_size);
- if (rc < 0) {
- pr_err("unable to get src buf address\n");
- return rc;
- }
- src_buf_iova_addr = (uint32_t *)iova_addr;
- temp = iova_addr;
-
- rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
- &cpu_addr, &dst_buf_len);
- if (rc < 0) {
- pr_err("unable to get dst buf address\n");
- return rc;
- }
- dst_cpu_addr = (uint32_t *)cpu_addr;
-
- ICP_DBG("i = %d patch info = %x %x %x %x\n", i,
- patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset,
- patch_desc[i].src_buf_hdl, patch_desc[i].src_offset);
-
- dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
- patch_desc[i].dst_offset);
- temp += patch_desc[i].src_offset;
-
- *dst_cpu_addr = temp;
-
- ICP_DBG("patch is done for dst %pK with src %pK value %llx\n",
- dst_cpu_addr, src_buf_iova_addr,
- *((uint64_t *)dst_cpu_addr));
+ /* Update Buffer Address from handles and patch information */
+ rc = cam_packet_util_process_patches(packet, hw_mgr->iommu_hdl);
+ if (rc) {
+ pr_err("Patch processing failed\n");
+ return rc;
}
/* process io config out descriptors */
diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c
index c42d7aa..053d748 100644
--- a/drivers/media/platform/msm/vidc/msm_vdec.c
+++ b/drivers/media/platform/msm/vidc/msm_vdec.c
@@ -639,6 +639,7 @@
int msm_vdec_inst_init(struct msm_vidc_inst *inst)
{
int rc = 0;
+ struct msm_vidc_format *fmt = NULL;
if (!inst) {
dprintk(VIDC_ERR, "Invalid input = %pK\n", inst);
@@ -661,10 +662,31 @@
inst->bufq[CAPTURE_PORT].num_planes = 1;
inst->prop.fps = DEFAULT_FPS;
inst->clk_data.operating_rate = 0;
- memcpy(&inst->fmts[OUTPUT_PORT], &vdec_formats[2],
+
+ /* By default, initialize CAPTURE port to UBWC YUV format */
+ fmt = msm_comm_get_pixel_fmt_fourcc(vdec_formats,
+ ARRAY_SIZE(vdec_formats), V4L2_PIX_FMT_NV12_UBWC,
+ CAPTURE_PORT);
+ if (!fmt || fmt->type != CAPTURE_PORT) {
+ dprintk(VIDC_ERR,
+ "vdec_formats corrupted\n");
+ return -EINVAL;
+ }
+ memcpy(&inst->fmts[fmt->type], fmt,
sizeof(struct msm_vidc_format));
- memcpy(&inst->fmts[CAPTURE_PORT], &vdec_formats[0],
+
+ /* By default, initialize OUTPUT port to H264 decoder */
+ fmt = msm_comm_get_pixel_fmt_fourcc(vdec_formats,
+ ARRAY_SIZE(vdec_formats), V4L2_PIX_FMT_H264,
+ OUTPUT_PORT);
+ if (!fmt || fmt->type != OUTPUT_PORT) {
+ dprintk(VIDC_ERR,
+ "vdec_formats corrupted\n");
+ return -EINVAL;
+ }
+ memcpy(&inst->fmts[fmt->type], fmt,
sizeof(struct msm_vidc_format));
+
return rc;
}
diff --git a/drivers/media/platform/msm/vidc/msm_venc.c b/drivers/media/platform/msm/vidc/msm_venc.c
index e3d52bf..8906027 100644
--- a/drivers/media/platform/msm/vidc/msm_venc.c
+++ b/drivers/media/platform/msm/vidc/msm_venc.c
@@ -2096,6 +2096,7 @@
int msm_venc_inst_init(struct msm_vidc_inst *inst)
{
int rc = 0;
+ struct msm_vidc_format *fmt = NULL;
if (!inst) {
dprintk(VIDC_ERR, "Invalid input = %pK\n", inst);
@@ -2120,10 +2121,30 @@
inst->bufq[CAPTURE_PORT].num_planes = 1;
inst->clk_data.operating_rate = 0;
- memcpy(&inst->fmts[CAPTURE_PORT], &venc_formats[4],
+ /* By default, initialize OUTPUT port to UBWC YUV format */
+ fmt = msm_comm_get_pixel_fmt_fourcc(venc_formats,
+ ARRAY_SIZE(venc_formats), V4L2_PIX_FMT_NV12_UBWC,
+ OUTPUT_PORT);
+ if (!fmt || fmt->type != OUTPUT_PORT) {
+ dprintk(VIDC_ERR,
+ "venc_formats corrupted\n");
+ return -EINVAL;
+ }
+ memcpy(&inst->fmts[fmt->type], fmt,
sizeof(struct msm_vidc_format));
- memcpy(&inst->fmts[OUTPUT_PORT], &venc_formats[0],
+
+ /* By default, initialize CAPTURE port to H264 encoder */
+ fmt = msm_comm_get_pixel_fmt_fourcc(venc_formats,
+ ARRAY_SIZE(venc_formats), V4L2_PIX_FMT_H264,
+ CAPTURE_PORT);
+ if (!fmt || fmt->type != CAPTURE_PORT) {
+ dprintk(VIDC_ERR,
+ "venc_formats corrupted\n");
+ return -EINVAL;
+ }
+ memcpy(&inst->fmts[fmt->type], fmt,
sizeof(struct msm_vidc_format));
+
return rc;
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index 1cab039..89da0a1 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -909,7 +909,7 @@
switch (found_buf) {
case 0:
- dprintk(VIDC_WARN,
+ dprintk(VIDC_DBG,
"%s: No buffer(type: %d) found for index %d\n",
__func__, buffer_type, buffer_index);
break;
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
index b80aa08..25cc1e4 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
@@ -309,10 +309,10 @@
return freq;
}
- dprintk(VIDC_PROF, "%s Inst %pK : Freq = %lu\n", __func__, inst, freq);
-
freq = max(vpp_cycles, vsp_cycles);
+ dprintk(VIDC_PROF, "%s Inst %pK : Freq = %lu\n", __func__, inst, freq);
+
return freq;
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index 9dda0d2..7b75d70 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -5497,6 +5497,14 @@
return -EINVAL;
hdev = inst->core->device;
mutex_lock(&inst->lock);
+ if (inst->state >= MSM_VIDC_RELEASE_RESOURCES_DONE ||
+ inst->state < MSM_VIDC_START_DONE ||
+ inst->core->state == VIDC_CORE_INVALID) {
+ dprintk(VIDC_DBG,
+ "Inst %pK : Not in valid state to call %s\n",
+ inst, __func__);
+ goto sess_continue_fail;
+ }
if (inst->session_type == MSM_VIDC_DECODER && inst->in_reconfig) {
dprintk(VIDC_DBG, "send session_continue\n");
rc = call_hfi_op(hdev, session_continue,
@@ -5515,6 +5523,7 @@
dprintk(VIDC_ERR,
"session_continue called in wrong state for decoder");
}
+
sess_continue_fail:
mutex_unlock(&inst->lock);
return rc;
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
index 2dd25f3..eaba920 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
@@ -456,7 +456,7 @@
#define HFI_INTRA_REFRESH_NONE (HFI_COMMON_BASE + 0x1)
#define HFI_INTRA_REFRESH_CYCLIC (HFI_COMMON_BASE + 0x2)
-#define HFI_INTRA_REFRESH_RANDOM (HFI_COMMON_BASE + 0x3)
+#define HFI_INTRA_REFRESH_RANDOM (HFI_COMMON_BASE + 0x5)
struct hfi_intra_refresh {
u32 mode;
diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig
index 3a6e214..1946204 100644
--- a/drivers/platform/msm/Kconfig
+++ b/drivers/platform/msm/Kconfig
@@ -152,4 +152,12 @@
a log and rates the actions according to whether a typical user would
use the tools.
+config QCOM_GENI_SE
+ tristate "QCOM GENI Serial Engine Driver"
+ help
+ This module is used to interact with GENI based Serial Engines on
+ Qualcomm Technologies, Inc. Universal Peripheral(QUPv3). This
+ module is used to configure and read the configuration from the
+ Serial Engines.
+
endmenu
diff --git a/drivers/platform/msm/Makefile b/drivers/platform/msm/Makefile
index cf24d7a..ff1d0e2 100644
--- a/drivers/platform/msm/Makefile
+++ b/drivers/platform/msm/Makefile
@@ -11,3 +11,4 @@
obj-$(CONFIG_USB_BAM) += usb_bam.o
obj-$(CONFIG_MSM_11AD) += msm_11ad/
obj-$(CONFIG_SEEMP_CORE) += seemp_core/
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c
index a37947b..6c597f0 100644
--- a/drivers/platform/msm/ipa/ipa_api.c
+++ b/drivers/platform/msm/ipa/ipa_api.c
@@ -2600,6 +2600,9 @@
case IPA_HW_v3_5_1:
str = "3.5.1";
break;
+ case IPA_HW_v4_0:
+ str = "4.0";
+ break;
default:
str = "Invalid version";
break;
@@ -2660,6 +2663,7 @@
case IPA_HW_v3_1:
case IPA_HW_v3_5:
case IPA_HW_v3_5_1:
+ case IPA_HW_v4_0:
result = ipa3_plat_drv_probe(pdev_p, ipa_api_ctrl,
ipa_plat_drv_match);
break;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index e7b16b3..31e530e 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -1735,7 +1735,7 @@
IPAERR("failed to construct dma_shared_mem imm cmd\n");
return -ENOMEM;
}
- desc.opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc.opcode = cmd_pyld->opcode;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
desc.type = IPA_IMM_CMD_DESC;
@@ -2000,8 +2000,7 @@
retval = -ENOMEM;
goto free_empty_img;
}
- desc[num_cmds].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmds].opcode = cmd_pyld[num_cmds]->opcode;
desc[num_cmds].pyld = cmd_pyld[num_cmds]->data;
desc[num_cmds].len = cmd_pyld[num_cmds]->len;
desc[num_cmds].type = IPA_IMM_CMD_DESC;
@@ -2100,8 +2099,7 @@
retval = -ENOMEM;
goto free_desc;
}
- desc->opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc->opcode = cmd_pyld->opcode;
desc->pyld = cmd_pyld->data;
desc->len = cmd_pyld->len;
desc->type = IPA_IMM_CMD_DESC;
@@ -2191,8 +2189,7 @@
retval = -EFAULT;
goto bail_desc;
}
- desc->opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc->opcode = cmd_pyld->opcode;
desc->pyld = cmd_pyld->data;
desc->len = cmd_pyld->len;
desc->type = IPA_IMM_CMD_DESC;
@@ -2259,8 +2256,7 @@
BUG();
}
- desc[num_descs].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_REGISTER_WRITE);
+ desc[num_descs].opcode = cmd_pyld->opcode;
desc[num_descs].type = IPA_IMM_CMD_DESC;
desc[num_descs].callback = ipa3_destroy_imm;
desc[num_descs].user1 = cmd_pyld;
@@ -2289,8 +2285,7 @@
return -EFAULT;
}
- desc[num_descs].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_REGISTER_WRITE);
+ desc[num_descs].opcode = cmd_pyld->opcode;
desc[num_descs].type = IPA_IMM_CMD_DESC;
desc[num_descs].callback = ipa3_destroy_imm;
desc[num_descs].user1 = cmd_pyld;
@@ -2494,7 +2489,7 @@
mem.phys_base);
return -EFAULT;
}
- desc.opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_HDR_INIT_LOCAL);
+ desc.opcode = cmd_pyld->opcode;
desc.type = IPA_IMM_CMD_DESC;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
@@ -2539,7 +2534,7 @@
mem.phys_base);
return -EFAULT;
}
- desc.opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc.opcode = cmd_pyld->opcode;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
desc.type = IPA_IMM_CMD_DESC;
@@ -2611,8 +2606,7 @@
goto free_mem;
}
- desc.opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V4_ROUTING_INIT);
+ desc.opcode = cmd_pyld->opcode;
desc.type = IPA_IMM_CMD_DESC;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
@@ -2678,8 +2672,7 @@
goto free_mem;
}
- desc.opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V6_ROUTING_INIT);
+ desc.opcode = cmd_pyld->opcode;
desc.type = IPA_IMM_CMD_DESC;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
@@ -2739,7 +2732,7 @@
goto free_mem;
}
- desc.opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V4_FILTER_INIT);
+ desc.opcode = cmd_pyld->opcode;
desc.type = IPA_IMM_CMD_DESC;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
@@ -2800,7 +2793,7 @@
goto free_mem;
}
- desc.opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V6_FILTER_INIT);
+ desc.opcode = cmd_pyld->opcode;
desc.type = IPA_IMM_CMD_DESC;
desc.pyld = cmd_pyld->data;
desc.len = cmd_pyld->len;
@@ -3939,6 +3932,9 @@
case IPA_HW_v3_5_1:
gsi_ver = GSI_VER_1_3;
break;
+ case IPA_HW_v4_0:
+ gsi_ver = GSI_VER_2_0;
+ break;
default:
IPAERR("No GSI version for ipa type %d\n", ipa_hw_type);
WARN_ON(1);
@@ -4319,6 +4315,7 @@
IPAERR("failed to construct IMM cmd\n");
return -ENOMEM;
}
+ ipa3_ctx->pkt_init_imm_opcode = cmd_pyld->opcode;
mem.size = cmd_pyld->len * ipa3_ctx->ipa_num_pipes;
mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
index ca77be9..1ee8ec8 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
@@ -244,6 +244,38 @@
pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CFG_n, pipe));
}
+/**
+ * _ipa_read_ep_reg_v4_0() - Reads and prints endpoint configuration registers
+ *
+ * Returns the number of characters printed
+ * Removed IPA_ENDP_INIT_ROUTE_n from v3
+ */
+int _ipa_read_ep_reg_v4_0(char *buf, int max_len, int pipe)
+{
+ return scnprintf(
+ dbg_buff, IPA_MAX_MSG_LEN,
+ "IPA_ENDP_INIT_NAT_%u=0x%x\n"
+ "IPA_ENDP_INIT_HDR_%u=0x%x\n"
+ "IPA_ENDP_INIT_HDR_EXT_%u=0x%x\n"
+ "IPA_ENDP_INIT_MODE_%u=0x%x\n"
+ "IPA_ENDP_INIT_AGGR_%u=0x%x\n"
+ "IPA_ENDP_INIT_CTRL_%u=0x%x\n"
+ "IPA_ENDP_INIT_HOL_EN_%u=0x%x\n"
+ "IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n"
+ "IPA_ENDP_INIT_DEAGGR_%u=0x%x\n"
+ "IPA_ENDP_INIT_CFG_%u=0x%x\n",
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_NAT_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HDR_EXT_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_MODE_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_AGGR_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CTRL_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_EN_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_DEAGGR_n, pipe),
+ pipe, ipahal_read_reg_n(IPA_ENDP_INIT_CFG_n, pipe));
+}
+
static ssize_t ipa3_read_ep_reg(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
@@ -1381,6 +1413,11 @@
u32 option = 0;
struct ipahal_reg_debug_cnt_ctrl dbg_cnt_ctrl;
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {
+ IPAERR("IPA_DEBUG_CNT_CTRL is not supported in IPA 4.0\n");
+ return -EPERM;
+ }
+
if (sizeof(dbg_buff) < count + 1)
return -EFAULT;
@@ -1416,6 +1453,11 @@
int nbytes;
u32 regval;
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {
+ IPAERR("IPA_DEBUG_CNT_REG is not supported in IPA 4.0\n");
+ return -EPERM;
+ }
+
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
regval =
ipahal_read_reg_n(IPA_DEBUG_CNT_REG_n, 0);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
index faa47d8..bf13ac5 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
@@ -315,9 +315,7 @@
}
/* populate tag field */
- if (desc[i].opcode ==
- ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_IP_PACKET_TAG_STATUS)) {
+ if (desc[i].is_tag_status) {
if (ipa_populate_tag_field(&desc[i], tx_pkt,
&tag_pyld_ret)) {
IPAERR("Failed to populate tag field\n");
@@ -1279,15 +1277,10 @@
* notification. IPA will generate a status packet with
* tag info as a result of the TAG STATUS command.
*/
- desc[data_idx].opcode =
- ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_IP_PACKET_TAG_STATUS);
- desc[data_idx].type = IPA_IMM_CMD_DESC;
- desc[data_idx].callback = ipa3_tag_destroy_imm;
+ desc[data_idx].is_tag_status = true;
data_idx++;
}
- desc[data_idx].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_PACKET_INIT);
+ desc[data_idx].opcode = ipa3_ctx->pkt_init_imm_opcode;
desc[data_idx].dma_address_valid = true;
desc[data_idx].dma_address = ipa3_ctx->pkt_init_imm[dst_ep_idx];
desc[data_idx].type = IPA_IMM_CMD_DESC;
@@ -1338,11 +1331,7 @@
* notification. IPA will generate a status packet with
* tag info as a result of the TAG STATUS command.
*/
- desc[data_idx].opcode =
- ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_IP_PACKET_TAG_STATUS);
- desc[data_idx].type = IPA_IMM_CMD_DESC;
- desc[data_idx].callback = ipa3_tag_destroy_imm;
+ desc[data_idx].is_tag_status = true;
data_idx++;
}
desc[data_idx].pyld = skb->data;
@@ -2979,11 +2968,7 @@
(u8)sys->ep->cfg.meta.qmap_id;
/* the tag field will be populated in ipa3_send() function */
- desc[0].opcode =
- ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_IP_PACKET_TAG_STATUS);
- desc[0].type = IPA_IMM_CMD_DESC;
- desc[0].callback = ipa3_tag_destroy_imm;
+ desc[0].is_tag_status = true;
desc[1].pyld = entry->pyld_buffer;
desc[1].len = entry->pyld_len;
desc[1].type = IPA_DATA_DESC_SKB;
@@ -3615,8 +3600,11 @@
*/
IPADBG_LOW("tx_pkt sent in tag: 0x%p\n", tx_pkt);
desc->pyld = tag_pyld->data;
+ desc->opcode = tag_pyld->opcode;
desc->len = tag_pyld->len;
desc->user1 = tag_pyld;
+ desc->type = IPA_IMM_CMD_DESC;
+ desc->callback = ipa3_tag_destroy_imm;
*tag_pyld_ret = tag_pyld;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
index ff763c4..d0ed782 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
@@ -573,7 +573,7 @@
rc = -EFAULT;
goto fail_reg_write_construct;
}
- desc[0].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[0].opcode = cmd_pyld[0]->opcode;
desc[0].pyld = cmd_pyld[0]->data;
desc[0].len = cmd_pyld[0]->len;
desc[0].type = IPA_IMM_CMD_DESC;
@@ -609,8 +609,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd++].type = IPA_IMM_CMD_DESC;
@@ -630,8 +629,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd++].type = IPA_IMM_CMD_DESC;
@@ -653,8 +651,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd++].type = IPA_IMM_CMD_DESC;
@@ -673,8 +670,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd++].type = IPA_IMM_CMD_DESC;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
index 69db99a..410b96a 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
@@ -181,8 +181,7 @@
IPAERR("fail construct dma_shared_mem cmd\n");
goto end;
}
- desc[0].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[0].opcode = hdr_cmd_pyld->opcode;
desc[0].pyld = hdr_cmd_pyld->data;
desc[0].len = hdr_cmd_pyld->len;
}
@@ -200,8 +199,7 @@
IPAERR("fail construct hdr_init_system cmd\n");
goto end;
}
- desc[0].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_HDR_INIT_SYSTEM);
+ desc[0].opcode = hdr_cmd_pyld->opcode;
desc[0].pyld = hdr_cmd_pyld->data;
desc[0].len = hdr_cmd_pyld->len;
}
@@ -233,8 +231,7 @@
IPAERR("fail construct dma_shared_mem cmd\n");
goto end;
}
- desc[1].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[1].opcode = ctx_cmd_pyld->opcode;
desc[1].pyld = ctx_cmd_pyld->data;
desc[1].len = ctx_cmd_pyld->len;
}
@@ -262,8 +259,7 @@
IPAERR("fail construct register_write cmd\n");
goto end;
}
- desc[1].opcode = ipahal_imm_cmd_get_opcode(
- IPA_IMM_CMD_REGISTER_WRITE);
+ desc[1].opcode = ctx_cmd_pyld->opcode;
desc[1].pyld = ctx_cmd_pyld->data;
desc[1].len = ctx_cmd_pyld->len;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index 3af4486..73a405f 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -701,6 +701,7 @@
* or kmalloc'ed immediate command parameters/plain old data
* @dma_address: dma mapped address of pyld
* @dma_address_valid: valid field for dma_address
+ * @is_tag_status: flag for IP_PACKET_TAG_STATUS imd cmd
* @len: length of the pyld
* @opcode: for immediate commands
* @callback: IPA client provided completion callback
@@ -715,6 +716,7 @@
skb_frag_t *frag;
dma_addr_t dma_address;
bool dma_address_valid;
+ bool is_tag_status;
u16 len;
u16 opcode;
void (*callback)(void *user1, int user2);
@@ -1069,6 +1071,7 @@
* @ipa_bus_hdl: msm driver handle for the data path bus
* @ctrl: holds the core specific operations based on
* core version (vtable like)
+ * @pkt_init_imm_opcode: opcode for IP_PACKET_INIT imm cmd
* @enable_clock_scaling: clock scaling is enabled ?
* @curr_ipa_clk_rate: IPA current clock rate
* @wcstats: wlan common buffer stats
@@ -1180,6 +1183,7 @@
bool q6_proxy_clk_vote_valid;
u32 ipa_num_pipes;
dma_addr_t pkt_init_imm[IPA3_MAX_NUM_PIPES];
+ u32 pkt_init_imm_opcode;
struct ipa3_wlan_comm_memb wc_memb;
@@ -1318,6 +1322,12 @@
* +-------------------------+
* | CANARY |
* +-------------------------+
+ * | PDN CONFIG |
+ * +-------------------------+
+ * | CANARY |
+ * +-------------------------+
+ * | CANARY |
+ * +-------------------------+
* | MODEM MEM |
* +-------------------------+
* | CANARY |
@@ -1398,6 +1408,8 @@
u32 apps_v6_rt_nhash_size;
u32 uc_event_ring_ofst;
u32 uc_event_ring_size;
+ u32 pdn_config_ofst;
+ u32 pdn_config_size;
};
struct ipa3_controller {
@@ -1827,6 +1839,7 @@
int __ipa3_release_hdr(u32 hdr_hdl);
int __ipa3_release_hdr_proc_ctx(u32 proc_ctx_hdl);
int _ipa_read_ep_reg_v3_0(char *buf, int max_len, int pipe);
+int _ipa_read_ep_reg_v4_0(char *buf, int max_len, int pipe);
void _ipa_enable_clks_v3_0(void);
void _ipa_disable_clks_v3_0(void);
struct device *ipa3_get_dma_dev(void);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c
index d98e6b4..e1177ca 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -420,7 +420,7 @@
goto bail;
}
- desc[0].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[0].opcode = nop_cmd_pyld->opcode;
desc[0].type = IPA_IMM_CMD_DESC;
desc[0].callback = NULL;
desc[0].user1 = NULL;
@@ -505,7 +505,7 @@
goto free_nop;
}
- desc[1].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V4_NAT_INIT);
+ desc[1].opcode = cmd_pyld->opcode;
desc[1].type = IPA_IMM_CMD_DESC;
desc[1].callback = NULL;
desc[1].user1 = NULL;
@@ -668,7 +668,7 @@
goto bail;
}
desc[0].type = IPA_IMM_CMD_DESC;
- desc[0].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[0].opcode = nop_cmd_pyld->opcode;
desc[0].callback = NULL;
desc[0].user1 = NULL;
desc[0].user2 = 0;
@@ -687,7 +687,7 @@
continue;
}
desc[1].type = IPA_IMM_CMD_DESC;
- desc[1].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_NAT_DMA);
+ desc[1].opcode = cmd_pyld->opcode;
desc[1].callback = NULL;
desc[1].user1 = NULL;
desc[1].user2 = 0;
@@ -777,7 +777,7 @@
result = -ENOMEM;
goto bail;
}
- desc[0].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[0].opcode = nop_cmd_pyld->opcode;
desc[0].type = IPA_IMM_CMD_DESC;
desc[0].callback = NULL;
desc[0].user1 = NULL;
@@ -804,7 +804,7 @@
result = -EPERM;
goto destroy_regwrt_imm_cmd;
}
- desc[1].opcode = ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_V4_NAT_INIT);
+ desc[1].opcode = cmd_pyld->opcode;
desc[1].type = IPA_IMM_CMD_DESC;
desc[1].callback = NULL;
desc[1].user1 = NULL;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
index 273877c..cf28986 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -550,8 +550,7 @@
IPAERR("fail construct register_write imm cmd. IP %d\n", ip);
goto fail_size_valid;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd].type = IPA_IMM_CMD_DESC;
@@ -569,8 +568,7 @@
IPAERR("fail construct dma_shared_mem imm cmd. IP %d\n", ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd].type = IPA_IMM_CMD_DESC;
@@ -588,8 +586,7 @@
IPAERR("fail construct dma_shared_mem imm cmd. IP %d\n", ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd].type = IPA_IMM_CMD_DESC;
@@ -609,8 +606,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd].type = IPA_IMM_CMD_DESC;
@@ -630,8 +626,7 @@
ip);
goto fail_imm_cmd_construct;
}
- desc[num_cmd].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_DMA_SHARED_MEM);
+ desc[num_cmd].opcode = cmd_pyld[num_cmd]->opcode;
desc[num_cmd].pyld = cmd_pyld[num_cmd]->data;
desc[num_cmd].len = cmd_pyld[num_cmd]->len;
desc[num_cmd].type = IPA_IMM_CMD_DESC;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 6321ca9..f8b4d7d 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -42,6 +42,7 @@
#define IPA_FORCE_CLOSE_TAG_PROCESS_TIMEOUT (10 * HZ)
#define IPA_BCR_REG_VAL_v3_0 (0x00000001)
#define IPA_BCR_REG_VAL_v3_5 (0x0000003B)
+#define IPA_BCR_REG_VAL_v4_0 (0x00000039)
#define IPA_AGGR_GRAN_MIN (1)
#define IPA_AGGR_GRAN_MAX (32)
#define IPA_EOT_COAL_GRAN_MIN (1)
@@ -62,8 +63,6 @@
/* configure IPA spare register 1 in order to have correct IPA version
* set bits 0,2,3 and 4. see SpareBits documentation.xlsx
*/
-#define IPA_SPARE_REG_1_VAL (0x0000081D)
-
/* HPS, DPS sequencers Types*/
#define IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY 0x00000000
@@ -121,6 +120,16 @@
#define IPA_v3_5_SRC_GROUP_MAX (4)
#define IPA_v3_5_DST_GROUP_MAX (3)
+#define IPA_v4_0_GROUP_LWA_DL (0)
+#define IPA_v4_0_MHI_GROUP_PCIE (0)
+#define IPA_v4_0_ETHERNET (0)
+#define IPA_v4_0_GROUP_UL_DL (1)
+#define IPA_v4_0_MHI_GROUP_DDR (1)
+#define IPA_v4_0_MHI_GROUP_DMA (2)
+#define IPA_v4_0_GROUP_UC_RX_Q (3)
+#define IPA_v4_0_SRC_GROUP_MAX (4)
+#define IPA_v4_0_DST_GROUP_MAX (4)
+
#define IPA_GROUP_MAX IPA_v3_0_GROUP_MAX
enum ipa_rsrc_grp_type_src {
@@ -139,7 +148,14 @@
IPA_v3_5_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF,
IPA_v3_5_RSRC_GRP_TYPE_SRC_HPS_DMARS,
IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES,
- IPA_v3_5_RSRC_GRP_TYPE_SRC_MAX
+ IPA_v3_5_RSRC_GRP_TYPE_SRC_MAX,
+
+ IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS = 0,
+ IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS,
+ IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF,
+ IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS,
+ IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES,
+ IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX
};
#define IPA_RSRC_GRP_TYPE_SRC_MAX IPA_v3_0_RSRC_GRP_TYPE_SRC_MAX
@@ -153,6 +169,10 @@
IPA_v3_5_RSRC_GRP_TYPE_DST_DATA_SECTORS = 0,
IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS,
IPA_v3_5_RSRC_GRP_TYPE_DST_MAX,
+
+ IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS = 0,
+ IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS,
+ IPA_v4_0_RSRC_GRP_TYPE_DST_MAX,
};
#define IPA_RSRC_GRP_TYPE_DST_MAX IPA_v3_0_RSRC_GRP_TYPE_DST_MAX
@@ -160,6 +180,12 @@
IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ,
IPA_RSRC_GRP_TYPE_RX_MAX
};
+
+enum ipa_rsrc_grp_rx_hps_weight_config {
+ IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG,
+ IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_MAX
+};
+
struct rsrc_min_max {
u32 min;
u32 max;
@@ -170,6 +196,8 @@
IPA_3_5,
IPA_3_5_MHI,
IPA_3_5_1,
+ IPA_4_0,
+ IPA_4_0_MHI,
IPA_VER_MAX,
};
@@ -233,6 +261,32 @@
[IPA_v3_5_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
{14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },
},
+ [IPA_4_0] = {
+ /* LWA_DL UL_DL not used UC_RX_Q, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
+ {1, 255}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
+ {10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
+ {12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
+ {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
+ {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_MHI] = {
+ /* PCIE DDR DMA not used, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
+ {4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
+ {10, 10}, {10, 10}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
+ {12, 12}, {12, 12}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
+ {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
+ {14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },
+ },
};
static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
@@ -267,6 +321,20 @@
[IPA_v3_5_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
{2, 255}, {1, 255}, {1, 2}, {0, 0}, {0, 0}, {0, 0} },
},
+ [IPA_4_0] = {
+ /*LWA_DL UL/DL/DPL uC, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
+ {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
+ {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_MHI] = {
+ /*LWA_DL UL/DL/DPL uC, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
+ {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
+ {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
+ },
};
static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
@@ -285,12 +353,50 @@
/* PCIE DDR DMA unused N/A N/A */
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
{ 3, 3 }, { 7, 7 }, { 2, 2 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },
-},
+ },
[IPA_3_5_1] = {
/* LWA_DL UL_DL unused UC_RX_Q N/A N/A */
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },
},
+ [IPA_4_0] = {
+ /* LWA_DL UL_DL not used UC_RX_Q, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
+ {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_MHI] = {
+ /* PCIE DDR DMA unused N/A N/A */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
+ { 3, 3 }, { 7, 7 }, { 2, 2 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },
+ },
+};
+
+static const u32 ipa3_rsrc_rx_grp_hps_weight_config
+ [IPA_VER_MAX][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_MAX][IPA_GROUP_MAX] = {
+ [IPA_3_0] = {
+ /* UL DL DIAG DMA Unused uC Rx */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 0, 0, 0, 0, 0, 0 },
+ },
+ [IPA_3_5] = {
+ /* unused UL_DL unused UC_RX_Q N/A N/A */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },
+ },
+ [IPA_3_5_MHI] = {
+ /* PCIE DDR DMA unused N/A N/A */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 },
+ },
+ [IPA_3_5_1] = {
+ /* LWA_DL UL_DL unused UC_RX_Q N/A N/A */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },
+ },
+ [IPA_4_0] = {
+ /* LWA_DL UL_DL not used UC_RX_Q, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },
+ },
+ [IPA_4_0_MHI] = {
+ /* PCIE DDR DMA unused N/A N/A */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 },
+ },
};
enum ipa_ees {
@@ -1115,6 +1221,399 @@
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 11, 2, 4, 6, IPA_EE_AP } },
+
+
+ /* IPA_4_0 */
+ [IPA_4_0][IPA_CLIENT_HSIC1_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_WLAN1_PROD] = {
+ 7, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 7, 9, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_HSIC2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_HSIC3_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB3_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_HSIC4_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB4_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_HSIC5_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_UC_USB_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_A5_WLAN_AMPDU_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_A2_EMBEDDED_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_A2_TETHERED_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_APPS_LAN_PROD] = {
+ 8, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 10, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_APPS_WAN_PROD] = {
+ 2, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 2, 3, 16, 32, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_APPS_CMD_PROD] = {
+ 5, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 5, 4, 20, 24, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_ODU_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 0, 1, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_ETHERNET_PROD] = {
+ 9, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 9, 0, 8, 16, IPA_EE_UC } },
+ [IPA_4_0][IPA_CLIENT_MHI_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_LAN_PROD] = {
+ 6, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 6, 2, 12, 24, IPA_EE_Q6 } },
+ [IPA_4_0][IPA_CLIENT_Q6_WAN_PROD] = {
+ 3, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 3, 0, 16, 32, IPA_EE_Q6 } },
+ [IPA_4_0][IPA_CLIENT_Q6_CMD_PROD] = {
+ 4, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 4, 1, 20, 24, IPA_EE_Q6 } },
+ [IPA_4_0][IPA_CLIENT_Q6_DECOMP_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_DECOMP2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = IPA_CLIENT_NOT_USED,
+ /* Only for test purpose */
+ [IPA_4_0][IPA_CLIENT_TEST_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST1_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST2_PROD] = {
+ 1, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 1, 0, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST3_PROD] = {
+ 7, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {7, 9, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST4_PROD] = {
+ 8, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 10, 8, 16, IPA_EE_AP } },
+
+
+ [IPA_4_0][IPA_CLIENT_HSIC1_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_WLAN1_CONS] = {
+ 18, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 18, 12, 6, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_HSIC2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_WLAN2_CONS] = {
+ 20, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 20, 14, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_HSIC3_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB3_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_WLAN3_CONS] = {
+ 21, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 21, 15, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_HSIC4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_WLAN4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_HSIC5_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_USB_CONS] = {
+ 19, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 19, 13, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_USB_DPL_CONS] = {
+ 15, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 15, 7, 5, 5, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_A2_EMBEDDED_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_A2_TETHERED_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_A5_LAN_WAN_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_APPS_LAN_CONS] = {
+ 10, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 10, 5, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_APPS_WAN_CONS] = {
+ 11, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 6, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_ODU_EMB_CONS] = {
+ 17, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 17, 1, 17, 17, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_ETHERNET_CONS] = {
+ 22, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 22, 1, 17, 17, IPA_EE_UC } },
+ [IPA_4_0][IPA_CLIENT_ODU_TETH_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_MHI_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_LAN_CONS] = {
+ 14, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 14, 4, 9, 9, IPA_EE_Q6 } },
+ [IPA_4_0][IPA_CLIENT_Q6_WAN_CONS] = {
+ 13, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 13, 3, 9, 9, IPA_EE_Q6 } },
+ [IPA_4_0][IPA_CLIENT_Q6_DUN_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_DECOMP_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_DECOMP2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = {
+ 16, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 16, 5, 9, 9, IPA_EE_Q6 } },
+ /* Only for test purpose */
+ /* MBIM aggregation test pipes should have the same QMB as USB_CONS */
+ [IPA_4_0][IPA_CLIENT_TEST_CONS] = {
+ 12, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 12, 2, 5, 5, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST1_CONS] = {
+ 12, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 12, 2, 5, 5, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST2_CONS] = {
+ 18, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 18, 12, 6, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST3_CONS] = {
+ 20, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 20, 14, 9, 9, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST4_CONS] = {
+ 21, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 21, 15, 9, 9, IPA_EE_AP } },
+
+ /* IPA_4_0_MHI */
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC1_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_WLAN1_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC3_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB3_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC4_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB4_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC5_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB_PROD] = {
+ 0, IPA_v4_0_MHI_GROUP_DDR, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_UC_USB_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_A5_WLAN_AMPDU_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_A2_EMBEDDED_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_A2_TETHERED_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_APPS_LAN_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_APPS_WAN_PROD] = {
+ 2, IPA_v4_0_MHI_GROUP_DDR, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 2, 3, 16, 32, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_APPS_CMD_PROD] = {
+ 5, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 5, 4, 20, 24, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_ODU_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_MHI_PROD] = {
+ 1, IPA_v4_0_MHI_GROUP_PCIE, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_PCIE,
+ { 1, 0, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_LAN_PROD] = {
+ 3, IPA_v4_0_MHI_GROUP_DDR, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 3, 0, 16, 32, IPA_EE_Q6 } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_WAN_PROD] = {
+ 6, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 6, 2, 12, 24, IPA_EE_Q6 } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_CMD_PROD] = {
+ 4, IPA_v4_0_MHI_GROUP_PCIE, false,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 4, 1, 20, 24, IPA_EE_Q6 } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_DECOMP_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_DECOMP2_PROD] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = {
+ 7, IPA_v4_0_MHI_GROUP_DMA, false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 7, 9, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = {
+ 8, IPA_v4_0_MHI_GROUP_DMA, false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 10, 8, 16, IPA_EE_AP } },
+ /* Only for test purpose */
+ [IPA_4_0_MHI][IPA_CLIENT_TEST_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0][IPA_CLIENT_TEST1_PROD] = {
+ 0, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST2_PROD] = {
+ 1, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 1, 0, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST3_PROD] = {
+ 7, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {7, 9, 8, 16, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST4_PROD] = {
+ 8, IPA_v4_0_GROUP_UL_DL, true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 10, 8, 16, IPA_EE_AP } },
+
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC1_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_WLAN1_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_WLAN2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC3_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB3_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_WLAN3_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_WLAN4_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_HSIC5_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_USB_CONS] = {
+ 19, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 19, 13, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_USB_DPL_CONS] = {
+ 15, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 15, 7, 5, 5, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_A2_EMBEDDED_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_A2_TETHERED_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_A5_LAN_WAN_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_APPS_LAN_CONS] = {
+ 10, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 10, 5, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_APPS_WAN_CONS] = {
+ 11, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 6, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_ODU_EMB_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_ODU_TETH_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_MHI_CONS] = {
+ 17, IPA_v4_0_MHI_GROUP_PCIE, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 17, 1, 17, 17, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_LAN_CONS] = {
+ 14, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 14, 4, 9, 9, IPA_EE_Q6 } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_WAN_CONS] = {
+ 13, IPA_v4_0_MHI_GROUP_DDR, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 13, 3, 9, 9, IPA_EE_Q6 } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_DUN_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_DECOMP_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_DECOMP2_CONS] = IPA_CLIENT_NOT_USED,
+ [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = {
+ 20, IPA_v4_0_MHI_GROUP_DMA, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 20, 14, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = {
+ 21, IPA_v4_0_MHI_GROUP_DMA, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 21, 15, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = {
+ 16, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 16, 5, 9, 9, IPA_EE_Q6 } },
+ /* Only for test purpose */
+ [IPA_4_0_MHI][IPA_CLIENT_TEST_CONS] = {
+ 12, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 12, 2, 5, 5, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST1_CONS] = {
+ 12, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 12, 2, 5, 5, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST2_CONS] = {
+ 18, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 18, 12, 6, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST3_CONS] = {
+ 20, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 20, 14, 9, 9, IPA_EE_AP } },
+ [IPA_4_0_MHI][IPA_CLIENT_TEST4_CONS] = {
+ 21, IPA_v4_0_GROUP_UL_DL, false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 21, 15, 9, 9, IPA_EE_AP } },
+
+
};
static struct msm_bus_vectors ipa_init_vectors_v3_0[] = {
@@ -1587,16 +2086,22 @@
*/
void ipa3_cfg_qsb(void)
{
- int qsb_max_writes[2] = { 8, 2 };
- int qsb_max_reads[2] = { 8, 8 };
+ struct ipahal_reg_qsb_max_reads max_reads = { 0 };
+ struct ipahal_reg_qsb_max_writes max_writes = { 0 };
+
+ max_reads.qmb_0_max_reads = 8,
+ max_reads.qmb_1_max_reads = 8,
+
+ max_writes.qmb_0_max_writes = 8;
+ max_writes.qmb_1_max_writes = 2;
if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5) {
- qsb_max_writes[1] = 4;
- qsb_max_reads[1] = 12;
+ max_writes.qmb_1_max_writes = 4;
+ max_reads.qmb_1_max_reads = 12;
}
- ipahal_write_reg_fields(IPA_QSB_MAX_WRITES, qsb_max_writes);
- ipahal_write_reg_fields(IPA_QSB_MAX_READS, qsb_max_reads);
+ ipahal_write_reg_fields(IPA_QSB_MAX_WRITES, &max_writes);
+ ipahal_write_reg_fields(IPA_QSB_MAX_READS, &max_reads);
}
/**
@@ -1624,6 +2129,9 @@
case IPA_HW_v3_5_1:
val = IPA_BCR_REG_VAL_v3_5;
break;
+ case IPA_HW_v4_0:
+ val = IPA_BCR_REG_VAL_v4_0;
+ break;
default:
IPAERR("unknown HW type in dts\n");
return -EFAULT;
@@ -1663,6 +2171,15 @@
case IPA_HW_v3_5_1:
hw_type_index = IPA_3_5_1;
break;
+ case IPA_HW_v4_0:
+ hw_type_index = IPA_4_0;
+ /*
+ *this flag is initialized only after fw load trigger from
+ * user space (ipa3_write)
+ */
+ if (ipa3_ctx->ipa_config_is_mhi)
+ hw_type_index = IPA_4_0_MHI;
+ break;
default:
IPAERR("Incorrect IPA version %d\n", ipa3_ctx->ipa_hw_type);
hw_type_index = IPA_3_0;
@@ -2573,12 +3090,15 @@
ipa3_ctx->ep[clnt_hdl].rt_tbl_idx =
IPA_MEM_PART(v4_apps_rt_index_lo);
- IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl));
+ if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0) {
+ IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl));
- init_rt.route_table_index = ipa3_ctx->ep[clnt_hdl].rt_tbl_idx;
- ipahal_write_reg_n_fields(IPA_ENDP_INIT_ROUTE_n, clnt_hdl, &init_rt);
+ init_rt.route_table_index = ipa3_ctx->ep[clnt_hdl].rt_tbl_idx;
+ ipahal_write_reg_n_fields(IPA_ENDP_INIT_ROUTE_n,
+ clnt_hdl, &init_rt);
- IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl));
+ IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl));
+ }
return 0;
}
@@ -2815,11 +3335,18 @@
{
struct ipahal_reg_qcncm qcncm;
- IPA_ACTIVE_CLIENTS_INC_SIMPLE();
- ipahal_read_reg_fields(IPA_QCNCM, &qcncm);
- qcncm.mode_en = mode;
- ipahal_write_reg_fields(IPA_QCNCM, &qcncm);
- IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {
+ if (mode != IPA_MBIM_AGGR) {
+ IPAERR("Only MBIM mode is supported staring 4.0\n");
+ return -EPERM;
+ }
+ } else {
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+ ipahal_read_reg_fields(IPA_QCNCM, &qcncm);
+ qcncm.mode_en = mode;
+ ipahal_write_reg_fields(IPA_QCNCM, &qcncm);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ }
return 0;
}
@@ -2839,6 +3366,11 @@
{
struct ipahal_reg_qcncm qcncm;
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {
+ IPAERR("QCNCM mode is not supported staring 4.0\n");
+ return -EPERM;
+ }
+
if (sig == NULL) {
IPAERR("bad argument for ipa3_set_qcncm_ndp_sig/n");
return -EINVAL;
@@ -2863,6 +3395,11 @@
{
struct ipahal_reg_single_ndp_mode mode;
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {
+ IPAERR("QCNCM mode is not supported staring 4.0\n");
+ return -EPERM;
+ }
+
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
ipahal_read_reg_fields(IPA_SINGLE_NDP_MODE, &mode);
mode.single_ndp_en = enable;
@@ -2910,13 +3447,13 @@
*/
int ipa3_init_mem_partition(struct device_node *node)
{
- const size_t ram_mmap_v3_0_size = 70;
- const size_t ram_mmap_v3_5_size = 72;
const size_t ram_mmap_current_version_size =
sizeof(ipa3_ctx->ctrl->mem_partition) / sizeof(u32);
- const size_t version = ipa_get_hw_type();
int result;
+ memset(&ipa3_ctx->ctrl->mem_partition, 0,
+ sizeof(ipa3_ctx->ctrl->mem_partition));
+
IPADBG("Reading from DTS as u32 array\n");
/*
@@ -2925,39 +3462,21 @@
* mismatch. The size of the array monotonically increasing because the
* obsolete entries are set to zero rather than deleted, so the
* possible sizes are in range
- * [ram_mmap_v3_0_size, ram_mmap_current_version_size]
+ * [1, ram_mmap_current_version_size]
*/
result = of_property_read_variable_u32_array(node, "qcom,ipa-ram-mmap",
(u32 *)&ipa3_ctx->ctrl->mem_partition,
- ram_mmap_v3_0_size, ram_mmap_current_version_size);
+ 1, ram_mmap_current_version_size);
- if (result <= 0) {
- IPAERR("Read operation failed\n");
+ if (IPA_MEM_PART(uc_event_ring_ofst) & 1023) {
+ IPAERR("UC EVENT RING OFST 0x%x is unaligned\n",
+ IPA_MEM_PART(uc_event_ring_ofst));
return -ENODEV;
}
- if (version < IPA_HW_v3_0)
- ipa_assert();
- if (version < IPA_HW_v3_5) {
- if (result != ram_mmap_v3_0_size) {
- IPAERR("Mismatch at IPA RAM MMAP DTS entry\n");
- return -ENODEV;
- }
- } else {
- if (result != ram_mmap_v3_5_size) {
- IPAERR("Mismatch at IPA RAM MMAP DTS entry\n");
- return -ENODEV;
- }
- if (IPA_MEM_PART(uc_event_ring_ofst) & 1023) {
- IPAERR("UC EVENT RING OFST 0x%x is unaligned\n",
- IPA_MEM_PART(uc_event_ring_ofst));
- return -ENODEV;
- }
-
- IPADBG("UC EVENT RING OFST 0x%x SIZE 0x%x\n",
- IPA_MEM_PART(uc_event_ring_ofst),
- IPA_MEM_PART(uc_event_ring_size));
- }
+ IPADBG("UC EVENT RING OFST 0x%x SIZE 0x%x\n",
+ IPA_MEM_PART(uc_event_ring_ofst),
+ IPA_MEM_PART(uc_event_ring_size));
IPADBG("NAT OFST 0x%x SIZE 0x%x\n", IPA_MEM_PART(nat_ofst),
IPA_MEM_PART(nat_size));
@@ -3126,6 +3645,16 @@
IPA_MEM_PART(apps_hdr_proc_ctx_size),
IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr));
+ if (IPA_MEM_PART(pdn_config_ofst) & 7) {
+ IPAERR("PDN CONFIG OFST 0x%x is unaligned\n",
+ IPA_MEM_PART(pdn_config_ofst));
+ return -ENODEV;
+ }
+
+ IPADBG("PDN CONFIG OFST 0x%x SIZE 0x%x\n",
+ IPA_MEM_PART(pdn_config_ofst),
+ IPA_MEM_PART(pdn_config_size));
+
if (IPA_MEM_PART(modem_ofst) & 7) {
IPAERR("MODEM OFST 0x%x is unaligned\n",
IPA_MEM_PART(modem_ofst));
@@ -3207,9 +3736,11 @@
ctrl->ipa_reg_base_ofst = ipahal_get_reg_base();
ctrl->ipa_init_sram = _ipa_init_sram_v3;
ctrl->ipa_sram_read_settings = _ipa_sram_settings_read_v3_0;
-
ctrl->ipa_init_hdr = _ipa_init_hdr_v3_0;
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)
+ ctrl->ipa3_read_ep_reg = _ipa_read_ep_reg_v4_0;
+
return 0;
}
@@ -3343,8 +3874,7 @@
res = -ENOMEM;
goto fail_free_tag_desc;
}
- tag_desc[desc_idx].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ tag_desc[desc_idx].opcode = cmd_pyld->opcode;
tag_desc[desc_idx].pyld = cmd_pyld->data;
tag_desc[desc_idx].len = cmd_pyld->len;
tag_desc[desc_idx].type = IPA_IMM_CMD_DESC;
@@ -3362,8 +3892,7 @@
res = -ENOMEM;
goto fail_free_desc;
}
- tag_desc[desc_idx].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_PACKET_INIT);
+ tag_desc[desc_idx].opcode = cmd_pyld->opcode;
tag_desc[desc_idx].pyld = cmd_pyld->data;
tag_desc[desc_idx].len = cmd_pyld->len;
tag_desc[desc_idx].type = IPA_IMM_CMD_DESC;
@@ -3380,8 +3909,7 @@
res = -ENOMEM;
goto fail_free_desc;
}
- tag_desc[desc_idx].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_IP_PACKET_TAG_STATUS);
+ tag_desc[desc_idx].opcode = cmd_pyld->opcode;
tag_desc[desc_idx].pyld = cmd_pyld->data;
tag_desc[desc_idx].len = cmd_pyld->len;
tag_desc[desc_idx].type = IPA_IMM_CMD_DESC;
@@ -3520,8 +4048,7 @@
goto fail_alloc_reg_write_agg_close;
}
- desc[desc_idx].opcode =
- ipahal_imm_cmd_get_opcode(IPA_IMM_CMD_REGISTER_WRITE);
+ desc[desc_idx].opcode = cmd_pyld->opcode;
desc[desc_idx].pyld = cmd_pyld->data;
desc[desc_idx].len = cmd_pyld->len;
desc[desc_idx].type = IPA_IMM_CMD_DESC;
@@ -4059,6 +4586,49 @@
}
}
break;
+ case IPA_4_0:
+ case IPA_4_0_MHI:
+ if (src) {
+ switch (group_index) {
+ case IPA_v4_0_GROUP_LWA_DL:
+ case IPA_v4_0_GROUP_UL_DL:
+ ipahal_write_reg_n_fields(
+ IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,
+ n, val);
+ break;
+ case IPA_v4_0_MHI_GROUP_DMA:
+ case IPA_v4_0_GROUP_UC_RX_Q:
+ ipahal_write_reg_n_fields(
+ IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,
+ n, val);
+ break;
+ default:
+ IPAERR(
+ " Invalid source resource group,index #%d\n",
+ group_index);
+ break;
+ }
+ } else {
+ switch (group_index) {
+ case IPA_v4_0_GROUP_LWA_DL:
+ case IPA_v4_0_GROUP_UL_DL:
+ ipahal_write_reg_n_fields(
+ IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
+ n, val);
+ break;
+ case IPA_v4_0_MHI_GROUP_DMA:
+ ipahal_write_reg_n_fields(
+ IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,
+ n, val);
+ break;
+ default:
+ IPAERR(
+ " Invalid destination resource group,index #%d\n",
+ group_index);
+ break;
+ }
+ }
+ break;
default:
IPAERR("invalid hw type\n");
WARN_ON(1);
@@ -4103,6 +4673,33 @@
}
}
+static void ipa3_configure_rx_hps_weight(void)
+{
+ struct ipahal_reg_rx_hps_weights val;
+ u8 hw_type_idx;
+
+ hw_type_idx = ipa3_get_hw_type_index();
+
+ val.hps_queue_weight_0 =
+ ipa3_rsrc_rx_grp_hps_weight_config
+ [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG]
+ [0];
+ val.hps_queue_weight_1 =
+ ipa3_rsrc_rx_grp_hps_weight_config
+ [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG]
+ [1];
+ val.hps_queue_weight_2 =
+ ipa3_rsrc_rx_grp_hps_weight_config
+ [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG]
+ [2];
+ val.hps_queue_weight_3 =
+ ipa3_rsrc_rx_grp_hps_weight_config
+ [hw_type_idx][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG]
+ [3];
+
+ ipahal_write_reg_fields(IPA_HPS_FTCH_ARB_QUEUE_WEIGHT, &val);
+}
+
void ipa3_set_resorce_groups_min_max_limits(void)
{
int i;
@@ -4133,6 +4730,13 @@
src_grp_idx_max = IPA_v3_5_SRC_GROUP_MAX;
dst_grp_idx_max = IPA_v3_5_DST_GROUP_MAX;
break;
+ case IPA_4_0:
+ case IPA_4_0_MHI:
+ src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;
+ dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;
+ src_grp_idx_max = IPA_v4_0_SRC_GROUP_MAX;
+ dst_grp_idx_max = IPA_v4_0_DST_GROUP_MAX;
+ break;
default:
IPAERR("invalid hw type index\n");
WARN_ON(1);
@@ -4186,6 +4790,9 @@
ipa3_configure_rx_hps_clients(1, false);
}
+ if (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5)
+ ipa3_configure_rx_hps_weight();
+
IPADBG("EXIT\n");
}
@@ -4309,8 +4916,7 @@
{
struct ipa3_desc desc = {0};
- desc.opcode = ipahal_imm_cmd_get_opcode_param(
- IPA_IMM_CMD_DMA_TASK_32B_ADDR, 1);
+ desc.opcode = ipa3_ctx->dma_task_info.cmd_pyld->opcode;
desc.pyld = ipa3_ctx->dma_task_info.cmd_pyld->data;
desc.len = ipa3_ctx->dma_task_info.cmd_pyld->len;
desc.type = IPA_IMM_CMD_DESC;
@@ -4565,6 +5171,7 @@
switch (ipa3_ctx->ipa_hw_type) {
case IPA_HW_v3_0:
case IPA_HW_v3_5:
+ case IPA_HW_v4_0:
return false;
case IPA_HW_v3_1:
case IPA_HW_v3_5_1:
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
index fa9c6c8..d35b8a7 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
@@ -49,6 +49,8 @@
#define IPAHAL_MEM_ALLOC(__size, __is_atomic_ctx) \
(kzalloc((__size), ((__is_atomic_ctx)?GFP_ATOMIC:GFP_KERNEL)))
+static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd);
+
static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dma_task_32b_addr(
enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
@@ -63,6 +65,8 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ /* Currently supports only one packet */
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd) + (1 << 8);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_dma_task_32b_addr *)pyld->data;
@@ -101,6 +105,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_packet_tag_status *)pyld->data;
@@ -127,6 +132,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_dma_shared_mem *)pyld->data;
@@ -164,6 +170,61 @@
return pyld;
}
+static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dma_shared_mem_v_4_0(
+ enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
+{
+ struct ipahal_imm_cmd_pyld *pyld;
+ struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 *data;
+ struct ipahal_imm_cmd_dma_shared_mem *mem_params =
+ (struct ipahal_imm_cmd_dma_shared_mem *)params;
+
+ if (unlikely(mem_params->size & ~0xFFFF)) {
+ IPAHAL_ERR("Size is bigger than 16bit width 0x%x\n",
+ mem_params->size);
+ WARN_ON(1);
+ return NULL;
+ }
+ if (unlikely(mem_params->local_addr & ~0xFFFF)) {
+ IPAHAL_ERR("Local addr is bigger than 16bit width 0x%x\n",
+ mem_params->local_addr);
+ WARN_ON(1);
+ return NULL;
+ }
+
+ pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx);
+ if (unlikely(!pyld)) {
+ WARN_ON(1);
+ return pyld;
+ }
+
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
+ pyld->len = sizeof(*data);
+ data = (struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 *)pyld->data;
+
+ data->direction = mem_params->is_read ? 1 : 0;
+ data->clear_after_read = mem_params->clear_after_read;
+ data->size = mem_params->size;
+ data->local_addr = mem_params->local_addr;
+ data->system_addr = mem_params->system_addr;
+ pyld->opcode |= (mem_params->skip_pipeline_clear ? 1 : 0) << 8;
+ switch (mem_params->pipeline_clear_options) {
+ case IPAHAL_HPS_CLEAR:
+ break;
+ case IPAHAL_SRC_GRP_CLEAR:
+ pyld->opcode |= (1 << 9);
+ break;
+ case IPAHAL_FULL_PIPELINE_CLEAR:
+ pyld->opcode |= (2 << 9);
+ break;
+ default:
+ IPAHAL_ERR("unsupported pipline clear option %d\n",
+ mem_params->pipeline_clear_options);
+ WARN_ON(1);
+ };
+
+ return pyld;
+}
+
static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_register_write(
enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
{
@@ -177,6 +238,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_register_write *)pyld->data;
@@ -209,6 +271,54 @@
return pyld;
}
+static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_register_write_v_4_0(
+ enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
+{
+ struct ipahal_imm_cmd_pyld *pyld;
+ struct ipa_imm_cmd_hw_register_write_v_4_0 *data;
+ struct ipahal_imm_cmd_register_write *regwrt_params =
+ (struct ipahal_imm_cmd_register_write *)params;
+
+ if (unlikely(regwrt_params->offset & ~0xFFFF)) {
+ IPAHAL_ERR("Offset is bigger than 16bit width 0x%x\n",
+ regwrt_params->offset);
+ WARN_ON(1);
+ return NULL;
+ }
+
+ pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) + sizeof(*data), is_atomic_ctx);
+ if (unlikely(!pyld)) {
+ WARN_ON(1);
+ return pyld;
+ }
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
+ pyld->len = sizeof(*data);
+ data = (struct ipa_imm_cmd_hw_register_write_v_4_0 *)pyld->data;
+
+ data->offset = regwrt_params->offset;
+ data->offset_high = regwrt_params->offset >> 16;
+ data->value = regwrt_params->value;
+ data->value_mask = regwrt_params->value_mask;
+
+ pyld->opcode |= (regwrt_params->skip_pipeline_clear ? 1 : 0) << 8;
+ switch (regwrt_params->pipeline_clear_options) {
+ case IPAHAL_HPS_CLEAR:
+ break;
+ case IPAHAL_SRC_GRP_CLEAR:
+ pyld->opcode |= (1 << 9);
+ break;
+ case IPAHAL_FULL_PIPELINE_CLEAR:
+ pyld->opcode |= (2 << 9);
+ break;
+ default:
+ IPAHAL_ERR("unsupported pipline clear option %d\n",
+ regwrt_params->pipeline_clear_options);
+ WARN_ON(1);
+ };
+
+ return pyld;
+}
+
static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_packet_init(
enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
{
@@ -222,6 +332,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_packet_init *)pyld->data;
@@ -248,6 +359,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_nat_dma *)pyld->data;
@@ -272,6 +384,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_hdr_init_system *)pyld->data;
@@ -293,6 +406,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_hdr_init_local *)pyld->data;
@@ -321,6 +435,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_v6_routing_init *)pyld->data;
@@ -347,6 +462,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_v4_routing_init *)pyld->data;
@@ -373,6 +489,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_v4_nat_init *)pyld->data;
@@ -411,6 +528,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_v6_filter_init *)pyld->data;
@@ -437,6 +555,7 @@
IPAHAL_ERR("kzalloc err\n");
return pyld;
}
+ pyld->opcode = ipahal_imm_cmd_get_opcode(cmd);
pyld->len = sizeof(*data);
data = (struct ipa_imm_cmd_hw_ip_v4_filter_init *)pyld->data;
@@ -455,16 +574,11 @@
* specific IPA version
* @construct - CB to construct imm command payload from abstracted structure
* @opcode - Immediate command OpCode
- * @dyn_op - Does this command supports Dynamic opcode?
- * Some commands opcode are dynamic where the part of the opcode is
- * supplied as param. This flag indicates if the specific command supports it
- * or not.
*/
struct ipahal_imm_cmd_obj {
struct ipahal_imm_cmd_pyld *(*construct)(enum ipahal_imm_cmd_name cmd,
const void *params, bool is_atomic_ctx);
u16 opcode;
- bool dyn_op;
};
/*
@@ -484,43 +598,51 @@
/* IPAv3 */
[IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_FILTER_INIT] = {
ipa_imm_cmd_construct_ip_v4_filter_init,
- 3, false},
+ 3},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_V6_FILTER_INIT] = {
ipa_imm_cmd_construct_ip_v6_filter_init,
- 4, false},
+ 4},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_NAT_INIT] = {
ipa_imm_cmd_construct_ip_v4_nat_init,
- 5, false},
+ 5},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_V4_ROUTING_INIT] = {
ipa_imm_cmd_construct_ip_v4_routing_init,
- 7, false},
+ 7},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_V6_ROUTING_INIT] = {
ipa_imm_cmd_construct_ip_v6_routing_init,
- 8, false},
+ 8},
[IPA_HW_v3_0][IPA_IMM_CMD_HDR_INIT_LOCAL] = {
ipa_imm_cmd_construct_hdr_init_local,
- 9, false},
+ 9},
[IPA_HW_v3_0][IPA_IMM_CMD_HDR_INIT_SYSTEM] = {
ipa_imm_cmd_construct_hdr_init_system,
- 10, false},
+ 10},
[IPA_HW_v3_0][IPA_IMM_CMD_REGISTER_WRITE] = {
ipa_imm_cmd_construct_register_write,
- 12, false},
+ 12},
[IPA_HW_v3_0][IPA_IMM_CMD_NAT_DMA] = {
ipa_imm_cmd_construct_nat_dma,
- 14, false},
+ 14},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_PACKET_INIT] = {
ipa_imm_cmd_construct_ip_packet_init,
- 16, false},
+ 16},
[IPA_HW_v3_0][IPA_IMM_CMD_DMA_TASK_32B_ADDR] = {
ipa_imm_cmd_construct_dma_task_32b_addr,
- 17, true},
+ 17},
[IPA_HW_v3_0][IPA_IMM_CMD_DMA_SHARED_MEM] = {
ipa_imm_cmd_construct_dma_shared_mem,
- 19, false},
+ 19},
[IPA_HW_v3_0][IPA_IMM_CMD_IP_PACKET_TAG_STATUS] = {
ipa_imm_cmd_construct_ip_packet_tag_status,
- 20, false},
+ 20},
+
+ /* IPAv4 */
+ [IPA_HW_v4_0][IPA_IMM_CMD_REGISTER_WRITE] = {
+ ipa_imm_cmd_construct_register_write_v_4_0,
+ 12},
+ [IPA_HW_v4_0][IPA_IMM_CMD_DMA_SHARED_MEM] = {
+ ipa_imm_cmd_construct_dma_shared_mem_v_4_0,
+ 19},
};
/*
@@ -589,7 +711,7 @@
/*
* ipahal_imm_cmd_get_opcode() - Get the fixed opcode of the immediate command
*/
-u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd)
+static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd)
{
u32 opcode;
@@ -613,63 +735,6 @@
}
/*
- * ipahal_imm_cmd_get_opcode_param() - Get the opcode of an immediate command
- * that supports dynamic opcode
- * Some commands opcode are not totaly fixed, but part of it is
- * a supplied parameter. E.g. Low-Byte is fixed and Hi-Byte
- * is a given parameter.
- * This API will return the composed opcode of the command given
- * the parameter
- * Note: Use this API only for immediate comamnds that support Dynamic Opcode
- */
-u16 ipahal_imm_cmd_get_opcode_param(enum ipahal_imm_cmd_name cmd, int param)
-{
- u32 opcode;
-
- if (cmd >= IPA_IMM_CMD_MAX) {
- IPAHAL_ERR("Invalid immediate command IMM_CMD=%u\n", cmd);
- ipa_assert();
- return -EFAULT;
- }
-
- IPAHAL_DBG_LOW("Get opcode of IMM_CMD=%s\n",
- ipahal_imm_cmd_name_str(cmd));
-
- if (!ipahal_imm_cmd_objs[ipahal_ctx->hw_type][cmd].dyn_op) {
- IPAHAL_ERR("IMM_CMD=%s does not support dynamic opcode\n",
- ipahal_imm_cmd_name_str(cmd));
- ipa_assert();
- return -EFAULT;
- }
-
- /* Currently, dynamic opcode commands uses params to be set
- * on the Opcode hi-byte (lo-byte is fixed).
- * If this to be changed in the future, make the opcode calculation
- * a CB per command
- */
- if (param & ~0xFFFF) {
- IPAHAL_ERR("IMM_CMD=%s opcode param is invalid\n",
- ipahal_imm_cmd_name_str(cmd));
- ipa_assert();
- return -EFAULT;
- }
- opcode = ipahal_imm_cmd_objs[ipahal_ctx->hw_type][cmd].opcode;
- if (opcode == -1) {
- IPAHAL_ERR("Try to get opcode of obsolete IMM_CMD=%s\n",
- ipahal_imm_cmd_name_str(cmd));
- ipa_assert();
- return -EFAULT;
- }
- if (opcode & ~0xFFFF) {
- IPAHAL_ERR("IMM_CMD=%s opcode will be overridden\n",
- ipahal_imm_cmd_name_str(cmd));
- ipa_assert();
- return -EFAULT;
- }
- return (opcode + (param<<8));
-}
-
-/*
* ipahal_construct_imm_cmd() - Construct immdiate command
* This function builds imm cmd bulk that can be be sent to IPA
* The command will be allocated dynamically.
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h
index 8f85d4e..e71a48b 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h
@@ -259,6 +259,8 @@
* Perform mem copy into or out of the SW area of IPA local mem
* @size: Size in bytes of data to copy. Expected size is up to 2K bytes
* @local_addr: Address in IPA local memory
+ * @clear_after_read: Clear local memory at the end of a read operation allows
+ * atomic read and clear if HPS is clear. Ignore for writes.
* @is_read: Read operation from local memory? If not, then write.
* @skip_pipeline_clear: if to skip pipeline clear waiting (don't wait)
* @pipeline_clear_option: options for pipeline clear waiting
@@ -267,6 +269,7 @@
struct ipahal_imm_cmd_dma_shared_mem {
u32 size;
u32 local_addr;
+ bool clear_after_read;
bool is_read;
bool skip_pipeline_clear;
enum ipahal_pipeline_clear_option pipeline_clear_options;
@@ -322,13 +325,13 @@
/*
* struct ipahal_imm_cmd_pyld - Immediate cmd payload information
* @len: length of the buffer
- * @reserved: padding bytes to make data buffer aligned
+ * @opcode: opcode of the immediate command
* @data: buffer contains the immediate command payload. Buffer goes
* back to back with this structure
*/
struct ipahal_imm_cmd_pyld {
u16 len;
- u16 reserved;
+ u16 opcode;
u8 data[0];
};
@@ -342,23 +345,6 @@
const char *ipahal_imm_cmd_name_str(enum ipahal_imm_cmd_name cmd_name);
/*
- * ipahal_imm_cmd_get_opcode() - Get the fixed opcode of the immediate command
- */
-u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd);
-
-/*
- * ipahal_imm_cmd_get_opcode_param() - Get the opcode of an immediate command
- * that supports dynamic opcode
- * Some commands opcode are not totaly fixed, but part of it is
- * a supplied parameter. E.g. Low-Byte is fixed and Hi-Byte
- * is a given parameter.
- * This API will return the composed opcode of the command given
- * the parameter
- * Note: Use this API only for immediate comamnds that support Dynamic Opcode
- */
-u16 ipahal_imm_cmd_get_opcode_param(enum ipahal_imm_cmd_name cmd, int param);
-
-/*
* ipahal_construct_imm_cmd() - Construct immdiate command
* This function builds imm cmd bulk that can be be sent to IPA
* The command will be allocated dynamically.
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h
index d6a496e..804c554 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h
@@ -278,7 +278,7 @@
* in H/W format.
* Write value to register. Allows reg changes to be synced with data packet
* and other immediate command. Can be used to access the sram
- * @sw_rsvd: Ignored by H/W. My be used by S/W
+ * @sw_rsvd: Ignored by H/W. May be used by S/W
* @skip_pipeline_clear: 0 to wait until IPA pipeline is clear. 1 don't wait
* @offset: offset from IPA base address - Lower 16bit of the IPA reg addr
* @value: value to write to register
@@ -301,6 +301,29 @@
};
/*
+ * struct ipa_imm_cmd_hw_register_write - REGISTER_WRITE command payload
+ * in H/W format.
+ * Write value to register. Allows reg changes to be synced with data packet
+ * and other immediate command. Can be used to access the sram
+ * @sw_rsvd: Ignored by H/W. May be used by S/W
+ * @offset_high: high bits of the Offset field - bits 17-20
+ * @rsvd: reserved - should be set to zero
+ * @offset: offset from IPA base address - Lower 16bit of the IPA reg addr
+ * @value: value to write to register
+ * @value_mask: mask specifying which value bits to write to the register
+ * @rsvd2: reserved - should be set to zero
+ */
+struct ipa_imm_cmd_hw_register_write_v_4_0 {
+ u64 sw_rsvd:11;
+ u64 offset_high:4;
+ u64 rsvd:1;
+ u64 offset:16;
+ u64 value:32;
+ u64 value_mask:32;
+ u64 rsvd2:32;
+};
+
+/*
* struct ipa_imm_cmd_hw_dma_shared_mem - DMA_SHARED_MEM command payload
* in H/W format.
* Perform mem copy into or out of the SW area of IPA local mem
@@ -331,6 +354,31 @@
};
/*
+ * struct ipa_imm_cmd_hw_dma_shared_mem - DMA_SHARED_MEM command payload
+ * in H/W format.
+ * Perform mem copy into or out of the SW area of IPA local mem
+ * @sw_rsvd: Ignored by H/W. My be used by S/W
+ * @size: Size in bytes of data to copy. Expected size is up to 2K bytes
+ * @clear_after_read: Clear local memory at the end of a read operation allows
+ * atomic read and clear if HPS is clear. Ignore for writes.
+ * @local_addr: Address in IPA local memory
+ * @direction: Read or write?
+ * 0: IPA write, Write to local address from system address
+ * 1: IPA read, Read from local address to system address
+ * @rsvd: reserved - should be set to zero
+ * @system_addr: Address in system memory
+ */
+struct ipa_imm_cmd_hw_dma_shared_mem_v_4_0 {
+ u64 sw_rsvd:15;
+ u64 clear_after_read:1;
+ u64 size:16;
+ u64 local_addr:16;
+ u64 direction:1;
+ u64 rsvd:15;
+ u64 system_addr:64;
+};
+
+/*
* struct ipa_imm_cmd_hw_ip_packet_tag_status -
* IP_PACKET_TAG_STATUS command payload in H/W format.
* This cmd is used for to allow SW to track HW processing by setting a TAG
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
index d369e82..1a119b9 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
@@ -78,6 +78,7 @@
__stringify(IPA_RX_HPS_CLIENTS_MIN_DEPTH_1),
__stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0),
__stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_1),
+ __stringify(IPA_HPS_FTCH_ARB_QUEUE_WEIGHT),
__stringify(IPA_QSB_MAX_WRITES),
__stringify(IPA_QSB_MAX_READS),
__stringify(IPA_TX_CFG),
@@ -355,6 +356,29 @@
IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK);
}
+static void ipareg_construct_endp_status_n_v4_0(
+ enum ipahal_reg_name reg, const void *fields, u32 *val)
+{
+ struct ipahal_reg_ep_cfg_status *ep_status =
+ (struct ipahal_reg_ep_cfg_status *)fields;
+
+ IPA_SETFIELD_IN_REG(*val, ep_status->status_en,
+ IPA_ENDP_STATUS_n_STATUS_EN_SHFT,
+ IPA_ENDP_STATUS_n_STATUS_EN_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val, ep_status->status_ep,
+ IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT,
+ IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val, ep_status->status_location,
+ IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT,
+ IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val, ep_status->status_pkt_suppress,
+ IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT,
+ IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK);
+}
+
static void ipareg_construct_qcncm(
enum ipahal_reg_name reg, const void *fields, u32 *val)
{
@@ -896,12 +920,14 @@
static void ipareg_construct_qsb_max_writes(enum ipahal_reg_name reg,
const void *fields, u32 *val)
{
- int *qsb_max_writes = (int *)fields;
+ struct ipahal_reg_qsb_max_writes *max_writes;
- IPA_SETFIELD_IN_REG(*val, qsb_max_writes[0],
+ max_writes = (struct ipahal_reg_qsb_max_writes *)fields;
+
+ IPA_SETFIELD_IN_REG(*val, max_writes->qmb_0_max_writes,
IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT,
IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK);
- IPA_SETFIELD_IN_REG(*val, qsb_max_writes[1],
+ IPA_SETFIELD_IN_REG(*val, max_writes->qmb_1_max_writes,
IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT,
IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK);
}
@@ -909,16 +935,39 @@
static void ipareg_construct_qsb_max_reads(enum ipahal_reg_name reg,
const void *fields, u32 *val)
{
- int *qsb_max_reads = (int *)fields;
+ struct ipahal_reg_qsb_max_reads *max_reads;
- IPA_SETFIELD_IN_REG(*val, qsb_max_reads[0],
+ max_reads = (struct ipahal_reg_qsb_max_reads *)fields;
+
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_reads,
IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT,
IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK);
- IPA_SETFIELD_IN_REG(*val, qsb_max_reads[1],
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_reads,
IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT,
IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);
}
+static void ipareg_construct_qsb_max_reads_v4_0(enum ipahal_reg_name reg,
+ const void *fields, u32 *val)
+{
+ struct ipahal_reg_qsb_max_reads *max_reads;
+
+ max_reads = (struct ipahal_reg_qsb_max_reads *)fields;
+
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_reads,
+ IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT,
+ IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK);
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_reads,
+ IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT,
+ IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_0_max_read_beats,
+ IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0,
+ IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0);
+ IPA_SETFIELD_IN_REG(*val, max_reads->qmb_1_max_read_beats,
+ IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0,
+ IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0);
+}
+
static void ipareg_parse_tx_cfg(enum ipahal_reg_name reg,
void *fields, u32 val)
{
@@ -934,9 +983,44 @@
IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5,
IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5);
- tx_cfg->prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val,
+ tx_cfg->tx0_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val,
IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5,
IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5);
+
+ tx_cfg->tx1_prefetch_almost_empty_size =
+ tx_cfg->tx0_prefetch_almost_empty_size;
+}
+
+static void ipareg_parse_tx_cfg_v4_0(enum ipahal_reg_name reg,
+ void *fields, u32 val)
+{
+ struct ipahal_reg_tx_cfg *tx_cfg;
+
+ tx_cfg = (struct ipahal_reg_tx_cfg *)fields;
+
+ tx_cfg->tx0_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0);
+
+ tx_cfg->tx1_prefetch_almost_empty_size = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0);
+
+ tx_cfg->dmaw_scnd_outsd_pred_en = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0);
+
+ tx_cfg->dmaw_scnd_outsd_pred_threshold = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0);
+
+ tx_cfg->dmaw_max_beats_256_dis = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0);
+
+ tx_cfg->pa_mask_en = IPA_GETFIELD_FROM_REG(val,
+ IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0,
+ IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0);
}
static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg,
@@ -946,6 +1030,10 @@
tx_cfg = (struct ipahal_reg_tx_cfg *)fields;
+ if (tx_cfg->tx0_prefetch_almost_empty_size !=
+ tx_cfg->tx1_prefetch_almost_empty_size)
+ ipa_assert();
+
IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_disable,
IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5,
IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5);
@@ -954,11 +1042,43 @@
IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5,
IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5);
- IPA_SETFIELD_IN_REG(*val, tx_cfg->prefetch_almost_empty_size,
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_almost_empty_size,
IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5,
IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5);
}
+static void ipareg_construct_tx_cfg_v4_0(enum ipahal_reg_name reg,
+ const void *fields, u32 *val)
+{
+ struct ipahal_reg_tx_cfg *tx_cfg;
+
+ tx_cfg = (struct ipahal_reg_tx_cfg *)fields;
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_almost_empty_size,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0);
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->tx1_prefetch_almost_empty_size,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0,
+ IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0);
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_scnd_outsd_pred_threshold,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0);
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_max_beats_256_dis,
+ IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0);
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->dmaw_scnd_outsd_pred_en,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0,
+ IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0);
+
+ IPA_SETFIELD_IN_REG(*val, tx_cfg->pa_mask_en,
+ IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0,
+ IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0);
+}
+
static void ipareg_construct_idle_indication_cfg(enum ipahal_reg_name reg,
const void *fields, u32 *val)
{
@@ -977,6 +1097,59 @@
IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_BMSK_V3_5);
}
+static void ipareg_construct_hps_queue_weights(enum ipahal_reg_name reg,
+ const void *fields, u32 *val)
+{
+ struct ipahal_reg_rx_hps_weights *hps_weights;
+
+ hps_weights = (struct ipahal_reg_rx_hps_weights *)fields;
+
+ IPA_SETFIELD_IN_REG(*val,
+ hps_weights->hps_queue_weight_0,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ hps_weights->hps_queue_weight_1,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ hps_weights->hps_queue_weight_2,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ hps_weights->hps_queue_weight_3,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK);
+}
+
+static void ipareg_parse_hps_queue_weights(
+ enum ipahal_reg_name reg, void *fields, u32 val)
+{
+ struct ipahal_reg_rx_hps_weights *hps_weights =
+ (struct ipahal_reg_rx_hps_weights *)fields;
+
+ memset(hps_weights, 0, sizeof(struct ipahal_reg_rx_hps_weights));
+
+ hps_weights->hps_queue_weight_0 = IPA_GETFIELD_FROM_REG(val,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK);
+
+ hps_weights->hps_queue_weight_1 = IPA_GETFIELD_FROM_REG(val,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK);
+
+ hps_weights->hps_queue_weight_2 = IPA_GETFIELD_FROM_REG(val,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK);
+
+ hps_weights->hps_queue_weight_3 = IPA_GETFIELD_FROM_REG(val,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK);
+}
+
/*
* struct ipahal_reg_obj - Register H/W information for specific IPA version
* @construct - CB to construct register value from abstracted structure
@@ -1266,6 +1439,41 @@
[IPA_HW_v3_5][IPA_IDLE_INDICATION_CFG] = {
ipareg_construct_idle_indication_cfg, ipareg_parse_dummy,
0x00000220, 0},
+ [IPA_HW_v3_5][IPA_HPS_FTCH_ARB_QUEUE_WEIGHT] = {
+ ipareg_construct_hps_queue_weights,
+ ipareg_parse_hps_queue_weights, 0x000005a4, 0},
+
+ /* IPAv4.0 */
+ [IPA_HW_v4_0][IPA_TX_CFG] = {
+ ipareg_construct_tx_cfg_v4_0, ipareg_parse_tx_cfg_v4_0,
+ 0x000001FC, 0},
+ [IPA_HW_v4_0][IPA_DEBUG_CNT_REG_n] = {
+ ipareg_construct_dummy, ipareg_parse_dummy,
+ -1, 0},
+ [IPA_HW_v4_0][IPA_DEBUG_CNT_CTRL_n] = {
+ ipareg_construct_debug_cnt_ctrl_n, ipareg_parse_dummy,
+ -1, 0},
+ [IPA_HW_v4_0][IPA_QCNCM] = {
+ ipareg_construct_qcncm, ipareg_parse_qcncm,
+ -1, 0},
+ [IPA_HW_v4_0][IPA_SINGLE_NDP_MODE] = {
+ ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode,
+ -1, 0},
+ [IPA_HW_v4_0][IPA_QSB_MAX_READS] = {
+ ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_dummy,
+ 0x00000078, 0},
+ [IPA_HW_v4_0][IPA_FILT_ROUT_HASH_FLUSH] = {
+ ipareg_construct_dummy, ipareg_parse_dummy,
+ 0x0000014c, 0},
+ [IPA_HW_v4_0][IPA_STATE_AGGR_ACTIVE] = {
+ ipareg_construct_dummy, ipareg_parse_dummy,
+ 0x000000b4, 0},
+ [IPA_HW_v4_0][IPA_ENDP_INIT_ROUTE_n] = {
+ ipareg_construct_endp_init_route_n, ipareg_parse_dummy,
+ -1, 0},
+ [IPA_HW_v4_0][IPA_ENDP_STATUS_n] = {
+ ipareg_construct_endp_status_n_v4_0, ipareg_parse_dummy,
+ 0x00000840, 0x70},
};
/*
@@ -1597,11 +1805,16 @@
if (ipahal_ctx->hw_type <= IPA_HW_v3_1) {
shft = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT;
bmsk = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK;
- } else {
+ } else if (ipahal_ctx->hw_type <= IPA_HW_v3_5_1) {
shft =
IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5;
bmsk =
IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5;
+ } else {
+ shft =
+ IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_0;
+ bmsk =
+ IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_0;
}
IPA_SETFIELD_IN_REG(valmask->val, 1 << ep_idx, shft, bmsk);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
index 4490103..c9293b8 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
@@ -81,6 +81,7 @@
IPA_RX_HPS_CLIENTS_MIN_DEPTH_1,
IPA_RX_HPS_CLIENTS_MAX_DEPTH_0,
IPA_RX_HPS_CLIENTS_MAX_DEPTH_1,
+ IPA_HPS_FTCH_ARB_QUEUE_WEIGHT,
IPA_QSB_MAX_WRITES,
IPA_QSB_MAX_READS,
IPA_TX_CFG,
@@ -168,11 +169,13 @@
* If set to 0 (default), PKT-STATUS will be appended before the packet
* for this endpoint. If set to 1, PKT-STATUS will be appended after the
* packet for this endpoint. Valid only for Output Pipes (IPA Producer)
+ * @status_pkt_suppress:
*/
struct ipahal_reg_ep_cfg_status {
bool status_en;
u8 status_ep;
bool status_location;
+ u8 status_pkt_suppress;
};
/*
@@ -272,6 +275,20 @@
};
/*
+* struct ipahal_reg_rx_hps_weights - weight values for RX HPS clients
+* @hps_queue_weight_0 - 4 bit Weight for RX_HPS_CMDQ #0 (3:0)
+* @hps_queue_weight_1 - 4 bit Weight for RX_HPS_CMDQ #1 (7:4)
+* @hps_queue_weight_2 - 4 bit Weight for RX_HPS_CMDQ #2 (11:8)
+* @hps_queue_weight_3 - 4 bit Weight for RX_HPS_CMDQ #3 (15:12)
+*/
+struct ipahal_reg_rx_hps_weights {
+ u32 hps_queue_weight_0;
+ u32 hps_queue_weight_1;
+ u32 hps_queue_weight_2;
+ u32 hps_queue_weight_3;
+};
+
+/*
* struct ipahal_reg_valmask - holding values and masking for registers
* HAL application may require only value and mask of it for some
* register fields.
@@ -322,15 +339,50 @@
};
/*
+ * struct ipahal_reg_qsb_max_writes - IPA QSB Max Writes register
+ * @qmb_0_max_writes: Max number of outstanding writes for GEN_QMB_0
+ * @qmb_1_max_writes: Max number of outstanding writes for GEN_QMB_1
+ */
+struct ipahal_reg_qsb_max_writes {
+ u32 qmb_0_max_writes;
+ u32 qmb_1_max_writes;
+};
+
+/*
+ * struct ipahal_reg_qsb_max_reads - IPA QSB Max Reads register
+ * @qmb_0_max_reads: Max number of outstanding reads for GEN_QMB_0
+ * @qmb_1_max_reads: Max number of outstanding reads for GEN_QMB_1
+ * @qmb_0_max_read_beats: Max number of outstanding read beats for GEN_QMB_0
+ * @qmb_1_max_read_beats: Max number of outstanding read beats for GEN_QMB_1
+ */
+struct ipahal_reg_qsb_max_reads {
+ u32 qmb_0_max_reads;
+ u32 qmb_1_max_reads;
+ u32 qmb_0_max_read_beats;
+ u32 qmb_1_max_read_beats;
+};
+
+/*
* struct ipahal_reg_tx_cfg - IPA TX_CFG register
* @tx0_prefetch_disable: Disable prefetch on TX0
* @tx1_prefetch_disable: Disable prefetch on TX1
- * @prefetch_almost_empty_size: Prefetch almost empty size
+ * @tx0_prefetch_almost_empty_size: Prefetch almost empty size on TX0
+ * @tx1_prefetch_almost_empty_size: Prefetch almost empty size on TX1
+ * @dmaw_scnd_outsd_pred_threshold:
+ * @dmaw_max_beats_256_dis:
+ * @dmaw_scnd_outsd_pred_en:
+ * @pa_mask_en:
*/
struct ipahal_reg_tx_cfg {
bool tx0_prefetch_disable;
bool tx1_prefetch_disable;
- u16 prefetch_almost_empty_size;
+ u32 tx0_prefetch_almost_empty_size;
+ u32 tx1_prefetch_almost_empty_size;
+ u32 dmaw_scnd_outsd_pred_threshold;
+ u32 dmaw_max_beats_256_dis;
+ u32 dmaw_scnd_outsd_pred_en;
+ u32 pa_mask_en;
+
};
/*
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
index 6d69b15..17bad03 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
@@ -93,6 +93,8 @@
#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0
#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5 0xfffff
#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5 0
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V4_0 0x7fffff
+#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V4_0 0
/* IPA_ENDP_INIT_ROUTE_n register */
#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f
@@ -129,6 +131,7 @@
/* IPA_ENDP_INIT_HOL_BLOCK_EN_n register */
#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1
#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAX 19
+#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAX_V_4_0 22
#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1
#define IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0
@@ -230,6 +233,8 @@
#define IPA_QCNCM_MODE_EN_SHFT 0
/* IPA_ENDP_STATUS_n register */
+#define IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_BMSK 0x200
+#define IPA_ENDP_STATUS_n_STATUS_PKT_SUPPRESS_SHFT 0x9
#define IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK 0x100
#define IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT 0x8
#define IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e
@@ -289,7 +294,6 @@
#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5 0x3F
#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5 0
-
/* IPA_IPA_IPA_RX_HPS_CLIENTS_MIN/MAX_DEPTH_0/1 registers */
#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(n) (0x7F << (8 * (n)))
#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(n) \
@@ -308,6 +312,12 @@
#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK (0xf0)
#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT (4)
+/* IPA_QSB_MAX_READS_BEATS register */
+#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0 (0xff0000)
+#define IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0 (0x10)
+#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0 (0xff000000)
+#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0 (0x18)
+
/* IPA_TX_CFG register */
#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5 (0x1)
#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5 (0)
@@ -316,10 +326,34 @@
#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C)
#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2)
+/* IPA_TX_CFG register v4.0 */
+#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0 (0x1e000)
+#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_SHFT_V4_0 (0xd)
+#define IPA_TX_CFG_PA_MASK_EN_BMSK_V4_0 (0x1000)
+#define IPA_TX_CFG_PA_MASK_EN_SHFT_V4_0 (0xc)
+#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_BMSK_V4_0 (0x800)
+#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_EN_SHFT_V4_0 (0xb)
+#define IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_BMSK_V4_0 (0x400)
+#define IPA_TX_CFG_DMAW_MAX_BEATS_256_DIS_SHFT_V4_0 (0xa)
+#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_BMSK_V4_0 (0x3c0)
+#define IPA_TX_CFG_DMAW_SCND_OUTSD_PRED_THRESHOLD_SHFT_V4_0 (0x6)
+#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_BMSK_V4_0 (0x3c)
+#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX0_SHFT_V4_0 (0x2)
+
/* IPA_IDLE_INDICATION_CFG regiser */
#define IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_BMSK_V3_5 (0xffff)
#define IPA_IDLE_INDICATION_CFG_ENTER_IDLE_DEBOUNCE_THRESH_SHFT_V3_5 (0)
#define IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_BMSK_V3_5 (0x10000)
#define IPA_IDLE_INDICATION_CFG_CONST_NON_IDLE_ENABLE_SHFT_V3_5 (16)
+/* IPA_HPS_FTCH_QUEUE_WEIGHT register */
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_BMSK (0xf)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_0_SHFT (0x0)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_BMSK (0xf0)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_1_SHFT (0x4)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_BMSK (0xf00)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_2_SHFT (0x8)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK (0xf000)
+#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT (0xc)
+
#endif /* _IPAHAL_REG_I_H_ */
diff --git a/drivers/platform/msm/qcom-geni-se.c b/drivers/platform/msm/qcom-geni-se.c
new file mode 100644
index 0000000..1fffa7c
--- /dev/null
+++ b/drivers/platform/msm/qcom-geni-se.c
@@ -0,0 +1,1269 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/dma-iommu.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/ipc_logging.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/msm-bus.h>
+#include <linux/msm-bus-board.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/qcom-geni-se.h>
+#include <linux/spinlock.h>
+
+#define GENI_SE_IOMMU_VA_START (0x40000000)
+#define GENI_SE_IOMMU_VA_SIZE (0xC0000000)
+
+#define NUM_LOG_PAGES 2
+
+static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, 100000000};
+
+/**
+ * @struct geni_se_device - Data structure to represent the QUPv3 Core
+ * @dev: Device pointer of the QUPv3 core.
+ * @cb_dev: Device pointer of the context bank in the IOMMU.
+ * @iommu_lock: Lock to protect IOMMU Mapping & attachment.
+ * @iommu_map: IOMMU map of the memory space supported by this core.
+ * @iommu_s1_bypass: Bypass IOMMU stage 1 translation.
+ * @base: Base address of this instance of QUPv3 core.
+ * @bus_bw: Client handle to the bus bandwidth request.
+ * @bus_mas_id: Master Endpoint ID for bus BW request.
+ * @bus_slv_id: Slave Endpoint ID for bus BW request.
+ * @ab_ib_lock: Lock to protect the bus ab & ib values, list.
+ * @ab_list_head: Sorted resource list based on average bus BW.
+ * @ib_list_head: Sorted resource list based on instantaneous bus BW.
+ * @cur_ab: Current Bus Average BW request value.
+ * @cur_ib: Current Bus Instantaneous BW request value.
+ * @bus_bw_set: Clock plan for the bus driver.
+ * @cur_bus_bw_idx: Current index within the bus clock plan.
+ * @log_ctx: Logging context to hold the debug information
+ */
+struct geni_se_device {
+ struct device *dev;
+ struct device *cb_dev;
+ struct mutex iommu_lock;
+ struct dma_iommu_mapping *iommu_map;
+ bool iommu_s1_bypass;
+ void __iomem *base;
+ struct msm_bus_client_handle *bus_bw;
+ u32 bus_mas_id;
+ u32 bus_slv_id;
+ spinlock_t ab_ib_lock;
+ struct list_head ab_list_head;
+ struct list_head ib_list_head;
+ unsigned long cur_ab;
+ unsigned long cur_ib;
+ int bus_bw_set_size;
+ unsigned long *bus_bw_set;
+ int cur_bus_bw_idx;
+ void *log_ctx;
+};
+
+/* Offset of QUPV3 Hardware Version Register */
+#define QUPV3_HW_VER (0x4)
+
+#define HW_VER_MAJOR_MASK GENMASK(31, 28)
+#define HW_VER_MAJOR_SHFT 28
+#define HW_VER_MINOR_MASK GENMASK(27, 16)
+#define HW_VER_MINOR_SHFT 16
+#define HW_VER_STEP_MASK GENMASK(15, 0)
+
+static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev);
+
+/**
+ * geni_read_reg_nolog() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg_nolog(void __iomem *base, int offset)
+{
+ return readl_relaxed_no_log(base + offset);
+}
+EXPORT_SYMBOL(geni_read_reg_nolog);
+
+/**
+ * geni_write_reg_nolog() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ */
+void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset)
+{
+ return writel_relaxed_no_log(value, (base + offset));
+}
+EXPORT_SYMBOL(geni_write_reg_nolog);
+
+/**
+ * geni_read_reg() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg(void __iomem *base, int offset)
+{
+ return readl_relaxed(base + offset);
+}
+EXPORT_SYMBOL(geni_read_reg);
+
+/**
+ * geni_write_reg() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ */
+void geni_write_reg(unsigned int value, void __iomem *base, int offset)
+{
+ return writel_relaxed(value, (base + offset));
+}
+EXPORT_SYMBOL(geni_write_reg);
+
+/**
+ * get_se_proto() - Read the protocol configured for a serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * Return: Protocol value as configured in the serial engine.
+ */
+int get_se_proto(void __iomem *base)
+{
+ int proto;
+
+ proto = ((geni_read_reg(base, GENI_FW_REVISION_RO)
+ & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT);
+ return proto;
+}
+EXPORT_SYMBOL(get_se_proto);
+
+static int se_geni_irq_en(void __iomem *base)
+{
+ unsigned int common_geni_m_irq_en;
+ unsigned int common_geni_s_irq_en;
+
+ common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
+ common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);
+ /* Common to all modes */
+ common_geni_m_irq_en |= M_COMMON_GENI_M_IRQ_EN;
+ common_geni_s_irq_en |= S_COMMON_GENI_S_IRQ_EN;
+
+ geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);
+ geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN);
+ return 0;
+}
+
+
+static void se_set_rx_rfr_wm(void __iomem *base, unsigned int rx_wm,
+ unsigned int rx_rfr)
+{
+ geni_write_reg(rx_wm, base, SE_GENI_RX_WATERMARK_REG);
+ geni_write_reg(rx_rfr, base, SE_GENI_RX_RFR_WATERMARK_REG);
+}
+
+static int se_io_set_mode(void __iomem *base)
+{
+ unsigned int io_mode;
+ unsigned int geni_dma_mode;
+
+ io_mode = geni_read_reg(base, SE_IRQ_EN);
+ geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
+
+ io_mode |= (GENI_M_IRQ_EN | GENI_S_IRQ_EN);
+ io_mode |= (DMA_TX_IRQ_EN | DMA_RX_IRQ_EN);
+ geni_dma_mode &= ~GENI_DMA_MODE_EN;
+
+ geni_write_reg(io_mode, base, SE_IRQ_EN);
+ geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
+ geni_write_reg(0, base, SE_GSI_EVENT_EN);
+ return 0;
+}
+
+static void se_io_init(void __iomem *base)
+{
+ unsigned int io_op_ctrl;
+ unsigned int geni_cgc_ctrl;
+ unsigned int dma_general_cfg;
+
+ geni_cgc_ctrl = geni_read_reg(base, GENI_CGC_CTRL);
+ dma_general_cfg = geni_read_reg(base, SE_DMA_GENERAL_CFG);
+ geni_cgc_ctrl |= DEFAULT_CGC_EN;
+ dma_general_cfg |= (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON |
+ DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON);
+ io_op_ctrl = DEFAULT_IO_OUTPUT_CTRL_MSK;
+ geni_write_reg(geni_cgc_ctrl, base, GENI_CGC_CTRL);
+ geni_write_reg(dma_general_cfg, base, SE_DMA_GENERAL_CFG);
+
+ geni_write_reg(io_op_ctrl, base, GENI_OUTPUT_CTRL);
+ geni_write_reg(FORCE_DEFAULT, base, GENI_FORCE_DEFAULT_REG);
+}
+
+/**
+ * geni_se_init() - Initialize the GENI Serial Engine
+ * @base: Base address of the serial engine's register block.
+ * @rx_wm: Receive watermark to be configured.
+ * @rx_rfr_wm: Ready-for-receive watermark to be configured.
+ *
+ * This function is used to initialize the GENI serial engine, configure
+ * receive watermark and ready-for-receive watermarks.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_init(void __iomem *base, unsigned int rx_wm, unsigned int rx_rfr)
+{
+ int ret;
+
+ se_io_init(base);
+ ret = se_io_set_mode(base);
+ if (ret)
+ return ret;
+
+ se_set_rx_rfr_wm(base, rx_wm, rx_rfr);
+ ret = se_geni_irq_en(base);
+ return ret;
+}
+EXPORT_SYMBOL(geni_se_init);
+
+static int geni_se_select_fifo_mode(void __iomem *base)
+{
+ int proto = get_se_proto(base);
+ unsigned int common_geni_m_irq_en;
+ unsigned int common_geni_s_irq_en;
+ unsigned int geni_dma_mode;
+
+ geni_write_reg(0, base, SE_GSI_EVENT_EN);
+ geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);
+ geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR);
+ geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR);
+ geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);
+ geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);
+
+ common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
+ common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);
+ geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
+ if (proto != UART) {
+ common_geni_m_irq_en |=
+ (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
+ M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
+ common_geni_s_irq_en |= S_CMD_DONE_EN;
+ }
+ geni_dma_mode &= ~GENI_DMA_MODE_EN;
+
+ geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);
+ geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN);
+ geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
+ return 0;
+}
+
+static int geni_se_select_dma_mode(void __iomem *base)
+{
+ unsigned int geni_dma_mode = 0;
+
+ geni_write_reg(0, base, SE_GSI_EVENT_EN);
+ geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);
+ geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR);
+ geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR);
+ geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);
+ geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN);
+
+ geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
+ geni_dma_mode |= GENI_DMA_MODE_EN;
+ geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
+ return 0;
+}
+
+static int geni_se_select_gsi_mode(void __iomem *base)
+{
+ unsigned int io_mode = 0;
+ unsigned int geni_dma_mode = 0;
+ unsigned int gsi_event_en = 0;
+
+ geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
+ gsi_event_en = geni_read_reg(base, SE_GSI_EVENT_EN);
+ io_mode = geni_read_reg(base, SE_IRQ_EN);
+
+ geni_dma_mode |= GENI_DMA_MODE_EN;
+ io_mode &= ~(DMA_TX_IRQ_EN | DMA_RX_IRQ_EN);
+ gsi_event_en |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN |
+ GENI_M_EVENT_EN | GENI_S_EVENT_EN);
+
+ geni_write_reg(io_mode, base, SE_IRQ_EN);
+ geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
+ geni_write_reg(gsi_event_en, base, SE_GSI_EVENT_EN);
+ return 0;
+
+}
+
+/**
+ * geni_se_select_mode() - Select the serial engine transfer mode
+ * @base: Base address of the serial engine's register block.
+ * @mode: Transfer mode to be selected.
+ *
+ * Return: 0 on success, standard Linux error codes on failure.
+ */
+int geni_se_select_mode(void __iomem *base, int mode)
+{
+ int ret = 0;
+
+ switch (mode) {
+ case FIFO_MODE:
+ geni_se_select_fifo_mode(base);
+ break;
+ case SE_DMA:
+ geni_se_select_dma_mode(base);
+ break;
+ case GSI_DMA:
+ geni_se_select_gsi_mode(base);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(geni_se_select_mode);
+
+/**
+ * geni_setup_m_cmd() - Setup the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ * @cmd: Command/Operation to setup in the primary sequencer.
+ * @params: Parameter for the sequencer command.
+ *
+ * This function is used to configure the primary sequencer with the
+ * command and its assoicated parameters.
+ */
+void geni_setup_m_cmd(void __iomem *base, u32 cmd, u32 params)
+{
+ u32 m_cmd = (cmd << M_OPCODE_SHFT);
+
+ m_cmd |= (params & M_PARAMS_MSK);
+ geni_write_reg(m_cmd, base, SE_GENI_M_CMD0);
+}
+EXPORT_SYMBOL(geni_setup_m_cmd);
+
+/**
+ * geni_setup_s_cmd() - Setup the secondary sequencer
+ * @base: Base address of the serial engine's register block.
+ * @cmd: Command/Operation to setup in the secondary sequencer.
+ * @params: Parameter for the sequencer command.
+ *
+ * This function is used to configure the secondary sequencer with the
+ * command and its assoicated parameters.
+ */
+void geni_setup_s_cmd(void __iomem *base, u32 cmd, u32 params)
+{
+ u32 s_cmd = geni_read_reg(base, SE_GENI_S_CMD0);
+
+ s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
+ s_cmd |= (cmd << S_OPCODE_SHFT);
+ s_cmd |= (params & S_PARAMS_MSK);
+ geni_write_reg(s_cmd, base, SE_GENI_S_CMD0);
+}
+EXPORT_SYMBOL(geni_setup_s_cmd);
+
+/**
+ * geni_cancel_m_cmd() - Cancel the command configured in the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to cancel the currently configured command in the
+ * primary sequencer.
+ */
+void geni_cancel_m_cmd(void __iomem *base)
+{
+ geni_write_reg(M_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG);
+}
+EXPORT_SYMBOL(geni_cancel_m_cmd);
+
+/**
+ * geni_cancel_s_cmd() - Cancel the command configured in the secondary
+ * sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to cancel the currently configured command in the
+ * secondary sequencer.
+ */
+void geni_cancel_s_cmd(void __iomem *base)
+{
+ geni_write_reg(S_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG);
+}
+EXPORT_SYMBOL(geni_cancel_s_cmd);
+
+/**
+ * geni_abort_m_cmd() - Abort the command configured in the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to force abort the currently configured command in the
+ * primary sequencer.
+ */
+void geni_abort_m_cmd(void __iomem *base)
+{
+ geni_write_reg(M_GENI_CMD_ABORT, base, SE_GENI_M_CMD_CTRL_REG);
+}
+EXPORT_SYMBOL(geni_abort_m_cmd);
+
+/**
+ * geni_abort_s_cmd() - Abort the command configured in the secondary
+ * sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to force abort the currently configured command in the
+ * secondary sequencer.
+ */
+void geni_abort_s_cmd(void __iomem *base)
+{
+ geni_write_reg(S_GENI_CMD_ABORT, base, SE_GENI_S_CMD_CTRL_REG);
+}
+EXPORT_SYMBOL(geni_abort_s_cmd);
+
+/**
+ * get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the depth i.e. number of elements in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo depth in units of FIFO words.
+ */
+int get_tx_fifo_depth(void __iomem *base)
+{
+ int tx_fifo_depth;
+
+ tx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_0)
+ & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT);
+ return tx_fifo_depth;
+}
+EXPORT_SYMBOL(get_tx_fifo_depth);
+
+/**
+ * get_tx_fifo_width() - Get the TX fifo width of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the width i.e. word size per element in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo width in bits
+ */
+int get_tx_fifo_width(void __iomem *base)
+{
+ int tx_fifo_width;
+
+ tx_fifo_width = ((geni_read_reg(base, SE_HW_PARAM_0)
+ & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT);
+ return tx_fifo_width;
+}
+EXPORT_SYMBOL(get_tx_fifo_width);
+
+/**
+ * get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the depth i.e. number of elements in the
+ * RX fifo of the serial engine.
+ *
+ * Return: RX fifo depth in units of FIFO words
+ */
+int get_rx_fifo_depth(void __iomem *base)
+{
+ int rx_fifo_depth;
+
+ rx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_1)
+ & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT);
+ return rx_fifo_depth;
+}
+EXPORT_SYMBOL(get_rx_fifo_depth);
+
+/**
+ * se_get_packing_config() - Get the packing configuration based on input
+ * @bpw: Bits of data per transfer word.
+ * @pack_words: Number of words per fifo element.
+ * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
+ * @cfg0: Output buffer to hold the first half of configuration.
+ * @cfg1: Output buffer to hold the second half of configuration.
+ *
+ * This function is used to calculate the packing configuration based on
+ * the input packing requirement and the configuration logic.
+ */
+void se_get_packing_config(int bpw, int pack_words, bool msb_to_lsb,
+ unsigned long *cfg0, unsigned long *cfg1)
+{
+ u32 cfg[4] = {0};
+ int len;
+ int temp_bpw = bpw;
+ int idx_start = (msb_to_lsb ? (bpw - 1) : 0);
+ int idx = idx_start;
+ int idx_delta = (msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE);
+ int ceil_bpw = ((bpw & (BITS_PER_BYTE - 1)) ?
+ ((bpw & ~(BITS_PER_BYTE - 1)) + BITS_PER_BYTE) : bpw);
+ int iter = (ceil_bpw * pack_words) >> 3;
+ int i;
+
+ if (unlikely(iter <= 0 || iter > 4)) {
+ *cfg0 = 0;
+ *cfg1 = 0;
+ return;
+ }
+
+ for (i = 0; i < iter; i++) {
+ len = (temp_bpw < BITS_PER_BYTE) ?
+ (temp_bpw - 1) : BITS_PER_BYTE - 1;
+ cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1));
+ idx = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
+ ((i + 1) * BITS_PER_BYTE) + idx_start :
+ idx + idx_delta;
+ temp_bpw = ((temp_bpw - BITS_PER_BYTE) <= 0) ?
+ bpw : (temp_bpw - BITS_PER_BYTE);
+ }
+ cfg[iter - 1] |= 1;
+ *cfg0 = cfg[0] | (cfg[1] << 10);
+ *cfg1 = cfg[2] | (cfg[3] << 10);
+}
+EXPORT_SYMBOL(se_get_packing_config);
+
+/**
+ * se_config_packing() - Packing configuration of the serial engine
+ * @base: Base address of the serial engine's register block.
+ * @bpw: Bits of data per transfer word.
+ * @pack_words: Number of words per fifo element.
+ * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
+ *
+ * This function is used to configure the packing rules for the current
+ * transfer.
+ */
+void se_config_packing(void __iomem *base, int bpw,
+ int pack_words, bool msb_to_lsb)
+{
+ unsigned long cfg0, cfg1;
+
+ se_get_packing_config(bpw, pack_words, msb_to_lsb, &cfg0, &cfg1);
+ geni_write_reg(cfg0, base, SE_GENI_TX_PACKING_CFG0);
+ geni_write_reg(cfg1, base, SE_GENI_TX_PACKING_CFG1);
+ geni_write_reg(cfg0, base, SE_GENI_RX_PACKING_CFG0);
+ geni_write_reg(cfg1, base, SE_GENI_RX_PACKING_CFG1);
+ if (pack_words || bpw == 32)
+ geni_write_reg((bpw >> 4), base, SE_GENI_BYTE_GRAN);
+}
+EXPORT_SYMBOL(se_config_packing);
+
+static void se_geni_clks_off(struct se_geni_rsc *rsc)
+{
+ clk_disable_unprepare(rsc->se_clk);
+ clk_disable_unprepare(rsc->s_ahb_clk);
+ clk_disable_unprepare(rsc->m_ahb_clk);
+}
+
+static bool geni_se_check_bus_bw(struct geni_se_device *geni_se_dev)
+{
+ int i;
+ int new_bus_bw_idx = geni_se_dev->bus_bw_set_size - 1;
+ unsigned long new_bus_bw;
+ bool bus_bw_update = false;
+
+ new_bus_bw = max(geni_se_dev->cur_ib, geni_se_dev->cur_ab) /
+ DEFAULT_BUS_WIDTH;
+ for (i = 0; i < geni_se_dev->bus_bw_set_size; i++) {
+ if (geni_se_dev->bus_bw_set[i] >= new_bus_bw) {
+ new_bus_bw_idx = i;
+ break;
+ }
+ }
+
+ if (geni_se_dev->cur_bus_bw_idx != new_bus_bw_idx) {
+ geni_se_dev->cur_bus_bw_idx = new_bus_bw_idx;
+ bus_bw_update = true;
+ }
+ return bus_bw_update;
+}
+
+static int geni_se_rmv_ab_ib(struct geni_se_device *geni_se_dev,
+ struct se_geni_rsc *rsc)
+{
+ unsigned long flags;
+ struct se_geni_rsc *tmp;
+ bool bus_bw_update = false;
+ int ret = 0;
+
+ if (unlikely(list_empty(&rsc->ab_list) || list_empty(&rsc->ib_list)))
+ return -EINVAL;
+
+ spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags);
+ list_del_init(&rsc->ab_list);
+ geni_se_dev->cur_ab -= rsc->ab;
+
+ list_del_init(&rsc->ib_list);
+ tmp = list_first_entry_or_null(&geni_se_dev->ib_list_head,
+ struct se_geni_rsc, ib_list);
+ if (tmp && tmp->ib != geni_se_dev->cur_ib)
+ geni_se_dev->cur_ib = tmp->ib;
+ else if (!tmp && geni_se_dev->cur_ib)
+ geni_se_dev->cur_ib = 0;
+
+ bus_bw_update = geni_se_check_bus_bw(geni_se_dev);
+ spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags);
+
+ if (bus_bw_update)
+ ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw,
+ geni_se_dev->cur_ab,
+ geni_se_dev->cur_ib);
+ GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL,
+ "%s: %lu:%lu (%lu:%lu) %d\n", __func__,
+ geni_se_dev->cur_ab, geni_se_dev->cur_ib,
+ rsc->ab, rsc->ib, bus_bw_update);
+ return ret;
+}
+
+/**
+ * se_geni_resources_off() - Turn off resources associated with the serial
+ * engine
+ * @rsc: Handle to resources associated with the serial engine.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int se_geni_resources_off(struct se_geni_rsc *rsc)
+{
+ int ret = 0;
+ struct geni_se_device *geni_se_dev;
+
+ if (unlikely(!rsc || !rsc->wrapper_dev))
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(rsc->wrapper_dev);
+ if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw))
+ return -ENODEV;
+
+ ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_sleep);
+ if (ret) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error %d pinctrl_select_state\n", __func__, ret);
+ return ret;
+ }
+ se_geni_clks_off(rsc);
+ ret = geni_se_rmv_ab_ib(geni_se_dev, rsc);
+ if (ret)
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error %d during bus_bw_update\n", __func__, ret);
+ return ret;
+}
+EXPORT_SYMBOL(se_geni_resources_off);
+
+static int se_geni_clks_on(struct se_geni_rsc *rsc)
+{
+ int ret;
+
+ ret = clk_prepare_enable(rsc->m_ahb_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(rsc->s_ahb_clk);
+ if (ret) {
+ clk_disable_unprepare(rsc->m_ahb_clk);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(rsc->se_clk);
+ if (ret) {
+ clk_disable_unprepare(rsc->s_ahb_clk);
+ clk_disable_unprepare(rsc->m_ahb_clk);
+ }
+ return ret;
+}
+
+static int geni_se_add_ab_ib(struct geni_se_device *geni_se_dev,
+ struct se_geni_rsc *rsc)
+{
+ unsigned long flags;
+ struct se_geni_rsc *tmp;
+ struct list_head *ins_list_head;
+ bool bus_bw_update = false;
+ int ret = 0;
+
+ spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags);
+ list_add(&rsc->ab_list, &geni_se_dev->ab_list_head);
+ geni_se_dev->cur_ab += rsc->ab;
+
+ ins_list_head = &geni_se_dev->ib_list_head;
+ list_for_each_entry(tmp, &geni_se_dev->ib_list_head, ib_list) {
+ if (tmp->ib < rsc->ib)
+ break;
+ ins_list_head = &tmp->ib_list;
+ }
+ list_add(&rsc->ib_list, ins_list_head);
+ /* Currently inserted node has greater average BW value */
+ if (ins_list_head == &geni_se_dev->ib_list_head)
+ geni_se_dev->cur_ib = tmp->ib;
+
+ bus_bw_update = geni_se_check_bus_bw(geni_se_dev);
+ spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags);
+
+ if (bus_bw_update)
+ ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw,
+ geni_se_dev->cur_ab,
+ geni_se_dev->cur_ib);
+ GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL,
+ "%s: %lu:%lu (%lu:%lu) %d\n", __func__,
+ geni_se_dev->cur_ab, geni_se_dev->cur_ib,
+ rsc->ab, rsc->ib, bus_bw_update);
+ return ret;
+}
+
+/**
+ * se_geni_resources_on() - Turn on resources associated with the serial
+ * engine
+ * @rsc: Handle to resources associated with the serial engine.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int se_geni_resources_on(struct se_geni_rsc *rsc)
+{
+ int ret = 0;
+ struct geni_se_device *geni_se_dev;
+
+ if (unlikely(!rsc || !rsc->wrapper_dev))
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(rsc->wrapper_dev);
+ if (unlikely(!geni_se_dev))
+ return -EPROBE_DEFER;
+
+ ret = geni_se_add_ab_ib(geni_se_dev, rsc);
+ if (ret) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error %d during bus_bw_update\n", __func__, ret);
+ return ret;
+ }
+
+ ret = se_geni_clks_on(rsc);
+ if (ret) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error %d during clks_on\n", __func__, ret);
+ geni_se_rmv_ab_ib(geni_se_dev, rsc);
+ return ret;
+ }
+
+ ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_active);
+ if (ret) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error %d pinctrl_select_state\n", __func__, ret);
+ se_geni_clks_off(rsc);
+ geni_se_rmv_ab_ib(geni_se_dev, rsc);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(se_geni_resources_on);
+
+/**
+ * geni_se_resources_init() - Init the SE resource structure
+ * @rsc: SE resource structure to be initialized.
+ * @ab: Initial Average bus bandwidth request value.
+ * @ib: Initial Instantaneous bus bandwidth request value.
+ *
+ * Return: 0 on success, standard Linux error codes on failure.
+ */
+int geni_se_resources_init(struct se_geni_rsc *rsc,
+ unsigned long ab, unsigned long ib)
+{
+ struct geni_se_device *geni_se_dev;
+
+ if (unlikely(!rsc || !rsc->wrapper_dev))
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(rsc->wrapper_dev);
+ if (unlikely(!geni_se_dev))
+ return -EPROBE_DEFER;
+
+ if (unlikely(IS_ERR_OR_NULL(geni_se_dev->bus_bw))) {
+ geni_se_dev->bus_bw = msm_bus_scale_register(
+ geni_se_dev->bus_mas_id,
+ geni_se_dev->bus_slv_id,
+ (char *)dev_name(geni_se_dev->dev),
+ false);
+ if (IS_ERR_OR_NULL(geni_se_dev->bus_bw)) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Error creating bus client\n", __func__);
+ return (int)PTR_ERR(geni_se_dev->bus_bw);
+ }
+ }
+
+ rsc->ab = ab;
+ rsc->ib = ib;
+ INIT_LIST_HEAD(&rsc->ab_list);
+ INIT_LIST_HEAD(&rsc->ib_list);
+ geni_se_iommu_map_and_attach(geni_se_dev);
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_resources_init);
+
+/**
+ * geni_se_tx_dma_prep() - Prepare the Serial Engine for TX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
+ * @base: Base address of the SE register block.
+ * @tx_buf: Pointer to the TX buffer.
+ * @tx_len: Length of the TX buffer.
+ * @tx_dma: Pointer to store the mapped DMA address.
+ *
+ * This function is used to prepare the buffers for DMA TX.
+ *
+ * Return: 0 on success, standard Linux error codes on error/failure.
+ */
+int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base,
+ void *tx_buf, int tx_len, dma_addr_t *tx_dma)
+{
+ int ret;
+
+ if (unlikely(!wrapper_dev || !base || !tx_buf || !tx_len || !tx_dma))
+ return -EINVAL;
+
+ ret = geni_se_iommu_map_buf(wrapper_dev, tx_dma, tx_buf, tx_len,
+ DMA_TO_DEVICE);
+ if (ret)
+ return ret;
+
+ geni_write_reg(7, base, SE_DMA_TX_IRQ_EN_SET);
+ geni_write_reg((u32)(*tx_dma), base, SE_DMA_TX_PTR_L);
+ geni_write_reg((u32)((*tx_dma) >> 32), base, SE_DMA_TX_PTR_H);
+ geni_write_reg(1, base, SE_DMA_TX_ATTR);
+ geni_write_reg(tx_len, base, SE_DMA_TX_LEN);
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_tx_dma_prep);
+
+/**
+ * geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped.
+ * @base: Base address of the SE register block.
+ * @rx_buf: Pointer to the RX buffer.
+ * @rx_len: Length of the RX buffer.
+ * @rx_dma: Pointer to store the mapped DMA address.
+ *
+ * This function is used to prepare the buffers for DMA RX.
+ *
+ * Return: 0 on success, standard Linux error codes on error/failure.
+ */
+int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base,
+ void *rx_buf, int rx_len, dma_addr_t *rx_dma)
+{
+ int ret;
+
+ if (unlikely(!wrapper_dev || !base || !rx_buf || !rx_len || !rx_dma))
+ return -EINVAL;
+
+ ret = geni_se_iommu_map_buf(wrapper_dev, rx_dma, rx_buf, rx_len,
+ DMA_FROM_DEVICE);
+ if (ret)
+ return ret;
+
+ geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET);
+ geni_write_reg((u32)(*rx_dma), base, SE_DMA_RX_PTR_L);
+ geni_write_reg((u32)((*rx_dma) >> 32), base, SE_DMA_RX_PTR_H);
+ /* RX does not have EOT bit */
+ geni_write_reg(0, base, SE_DMA_RX_ATTR);
+ geni_write_reg(rx_len, base, SE_DMA_RX_LEN);
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_rx_dma_prep);
+
+/**
+ * geni_se_tx_dma_unprep() - Unprepare the Serial Engine after TX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped.
+ * @tx_dma: DMA address of the TX buffer.
+ * @tx_len: Length of the TX buffer.
+ *
+ * This function is used to unprepare the DMA buffers after DMA TX.
+ */
+void geni_se_tx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t tx_dma, int tx_len)
+{
+ if (tx_dma)
+ geni_se_iommu_unmap_buf(wrapper_dev, &tx_dma, tx_len,
+ DMA_TO_DEVICE);
+}
+EXPORT_SYMBOL(geni_se_tx_dma_unprep);
+
+/**
+ * geni_se_rx_dma_unprep() - Unprepare the Serial Engine after RX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped.
+ * @rx_dma: DMA address of the RX buffer.
+ * @rx_len: Length of the RX buffer.
+ *
+ * This function is used to unprepare the DMA buffers after DMA RX.
+ */
+void geni_se_rx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t rx_dma, int rx_len)
+{
+ if (rx_dma)
+ geni_se_iommu_unmap_buf(wrapper_dev, &rx_dma, rx_len,
+ DMA_FROM_DEVICE);
+}
+EXPORT_SYMBOL(geni_se_rx_dma_unprep);
+
+/**
+ * geni_se_qupv3_hw_version() - Read the QUPv3 Hardware version
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @major: Buffer for Major Version field.
+ * @minor: Buffer for Minor Version field.
+ * @step: Buffer for Step Version field.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_qupv3_hw_version(struct device *wrapper_dev, unsigned int *major,
+ unsigned int *minor, unsigned int *step)
+{
+ unsigned int version;
+ struct geni_se_device *geni_se_dev;
+
+ if (!wrapper_dev || !major || !minor || !step)
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(wrapper_dev);
+ if (unlikely(!geni_se_dev))
+ return -ENODEV;
+
+ version = geni_read_reg(geni_se_dev->base, QUPV3_HW_VER);
+ *major = (version & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT;
+ *minor = (version & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT;
+ *step = version & HW_VER_STEP_MASK;
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_qupv3_hw_version);
+
+static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev)
+{
+ dma_addr_t va_start = GENI_SE_IOMMU_VA_START;
+ size_t va_size = GENI_SE_IOMMU_VA_SIZE;
+ int bypass = 1;
+ struct device *cb_dev = geni_se_dev->cb_dev;
+
+ mutex_lock(&geni_se_dev->iommu_lock);
+ if (likely(geni_se_dev->iommu_map)) {
+ mutex_unlock(&geni_se_dev->iommu_lock);
+ return 0;
+ }
+
+ geni_se_dev->iommu_map = arm_iommu_create_mapping(&platform_bus_type,
+ va_start, va_size);
+ if (IS_ERR(geni_se_dev->iommu_map)) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s:%s iommu_create_mapping failure\n",
+ __func__, dev_name(cb_dev));
+ mutex_unlock(&geni_se_dev->iommu_lock);
+ return PTR_ERR(geni_se_dev->iommu_map);
+ }
+
+ if (geni_se_dev->iommu_s1_bypass) {
+ if (iommu_domain_set_attr(geni_se_dev->iommu_map->domain,
+ DOMAIN_ATTR_S1_BYPASS, &bypass)) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s:%s Couldn't bypass s1 translation\n",
+ __func__, dev_name(cb_dev));
+ arm_iommu_release_mapping(geni_se_dev->iommu_map);
+ geni_se_dev->iommu_map = NULL;
+ mutex_unlock(&geni_se_dev->iommu_lock);
+ return -EIO;
+ }
+ }
+
+ if (arm_iommu_attach_device(cb_dev, geni_se_dev->iommu_map)) {
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s:%s couldn't arm_iommu_attach_device\n",
+ __func__, dev_name(cb_dev));
+ arm_iommu_release_mapping(geni_se_dev->iommu_map);
+ geni_se_dev->iommu_map = NULL;
+ mutex_unlock(&geni_se_dev->iommu_lock);
+ return -EIO;
+ }
+ mutex_unlock(&geni_se_dev->iommu_lock);
+ GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, "%s:%s successful\n",
+ __func__, dev_name(cb_dev));
+ return 0;
+}
+
+/**
+ * geni_se_iommu_map_buf() - Map a single buffer into QUPv3 context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @buf: Address of the buffer that needs to be mapped.
+ * @size: Size of the buffer.
+ * @dir: Direction of the DMA transfer.
+ *
+ * This function is used to map an already allocated buffer into the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ void *buf, size_t size, enum dma_data_direction dir)
+{
+ struct device *cb_dev;
+ struct geni_se_device *geni_se_dev;
+
+ if (!wrapper_dev || !iova || !buf || !size)
+ return -EINVAL;
+
+ *iova = DMA_ERROR_CODE;
+ geni_se_dev = dev_get_drvdata(wrapper_dev);
+ if (!geni_se_dev || !geni_se_dev->cb_dev)
+ return -ENODEV;
+
+ cb_dev = geni_se_dev->cb_dev;
+
+ *iova = dma_map_single(cb_dev, buf, size, dir);
+ if (dma_mapping_error(cb_dev, *iova))
+ return -EIO;
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_iommu_map_buf);
+
+/**
+ * geni_se_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3
+ * context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @size: Size of the buffer.
+ *
+ * This function is used to allocate a buffer and map it into the
+ * QUPv3 context bank device space.
+ *
+ * Return: address of the buffer on success, NULL or ERR_PTR on
+ * failure/error.
+ */
+void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ size_t size)
+{
+ struct device *cb_dev;
+ struct geni_se_device *geni_se_dev;
+ void *buf = NULL;
+
+ if (!wrapper_dev || !iova || !size)
+ return ERR_PTR(-EINVAL);
+
+ *iova = DMA_ERROR_CODE;
+ geni_se_dev = dev_get_drvdata(wrapper_dev);
+ if (!geni_se_dev || !geni_se_dev->cb_dev)
+ return ERR_PTR(-ENODEV);
+
+ cb_dev = geni_se_dev->cb_dev;
+
+ buf = dma_alloc_coherent(cb_dev, size, iova, GFP_KERNEL);
+ if (!buf)
+ GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL,
+ "%s: Failed dma_alloc_coherent\n", __func__);
+ return buf;
+}
+EXPORT_SYMBOL(geni_se_iommu_alloc_buf);
+
+/**
+ * geni_se_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @size: Size of the buffer.
+ * @dir: Direction of the DMA transfer.
+ *
+ * This function is used to unmap an already mapped buffer from the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ size_t size, enum dma_data_direction dir)
+{
+ struct device *cb_dev;
+ struct geni_se_device *geni_se_dev;
+
+ if (!wrapper_dev || !iova || !size)
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(wrapper_dev);
+ if (!geni_se_dev || !geni_se_dev->cb_dev)
+ return -ENODEV;
+
+ cb_dev = geni_se_dev->cb_dev;
+
+ dma_unmap_single(cb_dev, *iova, size, dir);
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_iommu_unmap_buf);
+
+/**
+ * geni_se_iommu_free_buf() - Unmap & free a single buffer from QUPv3
+ * context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @buf: Address of the buffer.
+ * @size: Size of the buffer.
+ *
+ * This function is used to unmap and free a buffer from the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ void *buf, size_t size)
+{
+ struct device *cb_dev;
+ struct geni_se_device *geni_se_dev;
+
+ if (!wrapper_dev || !iova || !buf || !size)
+ return -EINVAL;
+
+ geni_se_dev = dev_get_drvdata(wrapper_dev);
+ if (!geni_se_dev || !geni_se_dev->cb_dev)
+ return -ENODEV;
+
+ cb_dev = geni_se_dev->cb_dev;
+
+ dma_free_coherent(cb_dev, size, buf, *iova);
+ return 0;
+}
+EXPORT_SYMBOL(geni_se_iommu_free_buf);
+
+static const struct of_device_id geni_se_dt_match[] = {
+ { .compatible = "qcom,qupv3-geni-se", },
+ { .compatible = "qcom,qupv3-geni-se-cb", },
+ {}
+};
+
+static int geni_se_iommu_probe(struct device *dev)
+{
+ struct geni_se_device *geni_se_dev;
+
+ if (unlikely(!dev->parent)) {
+ dev_err(dev, "%s no parent for this device\n", __func__);
+ return -EINVAL;
+ }
+
+ geni_se_dev = dev_get_drvdata(dev->parent);
+ if (unlikely(!geni_se_dev)) {
+ dev_err(dev, "%s geni_se_dev not found\n", __func__);
+ return -EINVAL;
+ }
+ geni_se_dev->cb_dev = dev;
+
+ GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL,
+ "%s: Probe successful\n", __func__);
+ return 0;
+}
+
+static int geni_se_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct geni_se_device *geni_se_dev;
+
+ if (of_device_is_compatible(dev->of_node, "qcom,qupv3-geni-se-cb"))
+ return geni_se_iommu_probe(dev);
+
+ geni_se_dev = devm_kzalloc(dev, sizeof(*geni_se_dev), GFP_KERNEL);
+ if (!geni_se_dev)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "%s: Mandatory resource info not found\n",
+ __func__);
+ devm_kfree(dev, geni_se_dev);
+ return -EINVAL;
+ }
+
+ geni_se_dev->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR_OR_NULL(geni_se_dev->base)) {
+ dev_err(dev, "%s: Error mapping the resource\n", __func__);
+ devm_kfree(dev, geni_se_dev);
+ return -EFAULT;
+ }
+
+ geni_se_dev->dev = dev;
+ ret = of_property_read_u32(dev->of_node, "qcom,bus-mas-id",
+ &geni_se_dev->bus_mas_id);
+ if (ret) {
+ dev_err(dev, "%s: Error missing bus master id\n", __func__);
+ devm_iounmap(dev, geni_se_dev->base);
+ devm_kfree(dev, geni_se_dev);
+ }
+ ret = of_property_read_u32(dev->of_node, "qcom,bus-slv-id",
+ &geni_se_dev->bus_slv_id);
+ if (ret) {
+ dev_err(dev, "%s: Error missing bus slave id\n", __func__);
+ devm_iounmap(dev, geni_se_dev->base);
+ devm_kfree(dev, geni_se_dev);
+ }
+
+ geni_se_dev->iommu_s1_bypass = of_property_read_bool(dev->of_node,
+ "qcom,iommu-s1-bypass");
+ geni_se_dev->bus_bw_set = default_bus_bw_set;
+ geni_se_dev->bus_bw_set_size = ARRAY_SIZE(default_bus_bw_set);
+ mutex_init(&geni_se_dev->iommu_lock);
+ INIT_LIST_HEAD(&geni_se_dev->ab_list_head);
+ INIT_LIST_HEAD(&geni_se_dev->ib_list_head);
+ spin_lock_init(&geni_se_dev->ab_ib_lock);
+ geni_se_dev->log_ctx = ipc_log_context_create(NUM_LOG_PAGES,
+ dev_name(geni_se_dev->dev), 0);
+ if (!geni_se_dev->log_ctx)
+ dev_err(dev, "%s Failed to allocate log context\n", __func__);
+ dev_set_drvdata(dev, geni_se_dev);
+
+ ret = of_platform_populate(dev->of_node, geni_se_dt_match, NULL, dev);
+ if (ret) {
+ dev_err(dev, "%s: Error populating children\n", __func__);
+ devm_iounmap(dev, geni_se_dev->base);
+ devm_kfree(dev, geni_se_dev);
+ }
+
+ GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL,
+ "%s: Probe successful\n", __func__);
+ return ret;
+}
+
+static int geni_se_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct geni_se_device *geni_se_dev = dev_get_drvdata(dev);
+
+ if (likely(!IS_ERR_OR_NULL(geni_se_dev->iommu_map))) {
+ arm_iommu_detach_device(geni_se_dev->cb_dev);
+ arm_iommu_release_mapping(geni_se_dev->iommu_map);
+ }
+ ipc_log_context_destroy(geni_se_dev->log_ctx);
+ devm_iounmap(dev, geni_se_dev->base);
+ devm_kfree(dev, geni_se_dev);
+ return 0;
+}
+
+static struct platform_driver geni_se_driver = {
+ .driver = {
+ .name = "qupv3_geni_se",
+ .of_match_table = geni_se_dt_match,
+ },
+ .probe = geni_se_probe,
+ .remove = geni_se_remove,
+};
+
+static int __init geni_se_driver_init(void)
+{
+ return platform_driver_register(&geni_se_driver);
+}
+arch_initcall(geni_se_driver_init);
+
+static void __exit geni_se_driver_exit(void)
+{
+ platform_driver_unregister(&geni_se_driver);
+}
+module_exit(geni_se_driver_exit);
+
+MODULE_DESCRIPTION("GENI Serial Engine Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 3311380..0bdcc99 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -545,6 +545,25 @@
for the platforms that use APRv2.
Say M if you want to enable this module.
+config MSM_PERFORMANCE
+ tristate "msm performacne driver to support userspace hotplug requests"
+ default n
+ help
+ This driver is used to provide CPU hotplug support to userspace.
+ It ensures that no more than a user specified number of CPUs stay
+ online at any given point in time. This module can also restrict
+ max freq or min freq of cpu cluster
+
+config MSM_PERFORMANCE_HOTPLUG_ON
+ bool "Hotplug functionality through msm_performance turned on"
+ depends on MSM_PERFORMANCE
+ default y
+ help
+ If some other core-control driver is present turn off the core-control
+ capability of msm_performance driver. Setting this flag to false will
+ compile out the nodes needed for core-control functionality through
+ msm_performance.
+
config MSM_CDSP_LOADER
tristate "CDSP loader support"
depends on MSM_GLINK
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ba00ef10..9d175cd 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -57,6 +57,8 @@
obj-$(CONFIG_MSM_PIL) += peripheral-loader.o
obj-$(CONFIG_MSM_AVTIMER) += avtimer.o
+obj-$(CONFIG_MSM_PERFORMANCE) += msm_performance.o
+
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
obj-y += subsystem_notif.o
obj-y += subsystem_restart.o
diff --git a/drivers/soc/qcom/msm_performance.c b/drivers/soc/qcom/msm_performance.c
new file mode 100644
index 0000000..25e6a9d
--- /dev/null
+++ b/drivers/soc/qcom/msm_performance.c
@@ -0,0 +1,2771 @@
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
+#include <linux/moduleparam.h>
+#include <linux/cpumask.h>
+#include <linux/cpufreq.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/tick.h>
+#include <trace/events/power.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/kthread.h>
+
+static struct mutex managed_cpus_lock;
+
+/* Maximum number to clusters that this module will manage */
+static unsigned int num_clusters;
+struct cluster {
+ cpumask_var_t cpus;
+ /* Number of CPUs to maintain online */
+ int max_cpu_request;
+ /* To track CPUs that the module decides to offline */
+ cpumask_var_t offlined_cpus;
+ /* stats for load detection */
+ /* IO */
+ u64 last_io_check_ts;
+ unsigned int iowait_enter_cycle_cnt;
+ unsigned int iowait_exit_cycle_cnt;
+ spinlock_t iowait_lock;
+ unsigned int cur_io_busy;
+ bool io_change;
+ /* CPU */
+ unsigned int mode;
+ bool mode_change;
+ u64 last_mode_check_ts;
+ unsigned int single_enter_cycle_cnt;
+ unsigned int single_exit_cycle_cnt;
+ unsigned int multi_enter_cycle_cnt;
+ unsigned int multi_exit_cycle_cnt;
+ spinlock_t mode_lock;
+ /* Perf Cluster Peak Loads */
+ unsigned int perf_cl_peak;
+ u64 last_perf_cl_check_ts;
+ bool perf_cl_detect_state_change;
+ unsigned int perf_cl_peak_enter_cycle_cnt;
+ unsigned int perf_cl_peak_exit_cycle_cnt;
+ spinlock_t perf_cl_peak_lock;
+ /* Tunables */
+ unsigned int single_enter_load;
+ unsigned int pcpu_multi_enter_load;
+ unsigned int perf_cl_peak_enter_load;
+ unsigned int single_exit_load;
+ unsigned int pcpu_multi_exit_load;
+ unsigned int perf_cl_peak_exit_load;
+ unsigned int single_enter_cycles;
+ unsigned int single_exit_cycles;
+ unsigned int multi_enter_cycles;
+ unsigned int multi_exit_cycles;
+ unsigned int perf_cl_peak_enter_cycles;
+ unsigned int perf_cl_peak_exit_cycles;
+ unsigned int current_freq;
+ spinlock_t timer_lock;
+ unsigned int timer_rate;
+ struct timer_list mode_exit_timer;
+ struct timer_list perf_cl_peak_mode_exit_timer;
+};
+
+static struct cluster **managed_clusters;
+static bool clusters_inited;
+
+/* Work to evaluate the onlining/offlining CPUs */
+static struct delayed_work evaluate_hotplug_work;
+
+/* To handle cpufreq min/max request */
+struct cpu_status {
+ unsigned int min;
+ unsigned int max;
+};
+static DEFINE_PER_CPU(struct cpu_status, cpu_stats);
+
+static unsigned int num_online_managed(struct cpumask *mask);
+static int init_cluster_control(void);
+static int rm_high_pwr_cost_cpus(struct cluster *cl);
+static int init_events_group(void);
+static DEFINE_PER_CPU(unsigned int, cpu_power_cost);
+struct events {
+ spinlock_t cpu_hotplug_lock;
+ bool cpu_hotplug;
+ bool init_success;
+};
+static struct events events_group;
+static struct task_struct *events_notify_thread;
+
+#define LAST_UPDATE_TOL USEC_PER_MSEC
+
+struct input_events {
+ unsigned int evt_x_cnt;
+ unsigned int evt_y_cnt;
+ unsigned int evt_pres_cnt;
+ unsigned int evt_dist_cnt;
+};
+struct trig_thr {
+ unsigned int pwr_cl_trigger_threshold;
+ unsigned int perf_cl_trigger_threshold;
+ unsigned int ip_evt_threshold;
+};
+struct load_stats {
+ u64 last_wallclock;
+ /* IO wait related */
+ u64 last_iowait;
+ unsigned int last_iopercent;
+ /* CPU load related */
+ unsigned int cpu_load;
+ /* CPU Freq */
+ unsigned int freq;
+};
+static bool input_events_handler_registered;
+static struct input_events *ip_evts;
+static struct trig_thr thr;
+static unsigned int use_input_evts_with_hi_slvt_detect;
+static int register_input_handler(void);
+static void unregister_input_handler(void);
+static DEFINE_PER_CPU(struct load_stats, cpu_load_stats);
+
+/* Bitmask to keep track of the workloads being detected */
+static unsigned int workload_detect;
+#define IO_DETECT 1
+#define MODE_DETECT 2
+#define PERF_CL_PEAK_DETECT 4
+
+/* IOwait related tunables */
+static unsigned int io_enter_cycles = 4;
+static unsigned int io_exit_cycles = 4;
+static u64 iowait_ceiling_pct = 25;
+static u64 iowait_floor_pct = 8;
+#define LAST_IO_CHECK_TOL (3 * USEC_PER_MSEC)
+
+static unsigned int aggr_iobusy;
+static unsigned int aggr_mode;
+
+static struct task_struct *notify_thread;
+
+static struct input_handler *handler;
+
+/* CPU workload detection related */
+#define NO_MODE (0)
+#define SINGLE (1)
+#define MULTI (2)
+#define MIXED (3)
+#define PERF_CL_PEAK (4)
+#define DEF_SINGLE_ENT 90
+#define DEF_PCPU_MULTI_ENT 85
+#define DEF_PERF_CL_PEAK_ENT 80
+#define DEF_SINGLE_EX 60
+#define DEF_PCPU_MULTI_EX 50
+#define DEF_PERF_CL_PEAK_EX 70
+#define DEF_SINGLE_ENTER_CYCLE 4
+#define DEF_SINGLE_EXIT_CYCLE 4
+#define DEF_MULTI_ENTER_CYCLE 4
+#define DEF_MULTI_EXIT_CYCLE 4
+#define DEF_PERF_CL_PEAK_ENTER_CYCLE 100
+#define DEF_PERF_CL_PEAK_EXIT_CYCLE 20
+#define LAST_LD_CHECK_TOL (2 * USEC_PER_MSEC)
+#define CLUSTER_0_THRESHOLD_FREQ 147000
+#define CLUSTER_1_THRESHOLD_FREQ 190000
+#define INPUT_EVENT_CNT_THRESHOLD 15
+#define MAX_LENGTH_CPU_STRING 256
+
+/**************************sysfs start********************************/
+
+static int set_num_clusters(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ if (num_clusters)
+ return -EINVAL;
+
+ num_clusters = val;
+
+ if (init_cluster_control()) {
+ num_clusters = 0;
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int get_num_clusters(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", num_clusters);
+}
+
+static const struct kernel_param_ops param_ops_num_clusters = {
+ .set = set_num_clusters,
+ .get = get_num_clusters,
+};
+device_param_cb(num_clusters, ¶m_ops_num_clusters, NULL, 0644);
+
+static int set_max_cpus(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int i, ntokens = 0;
+ const char *cp = buf;
+ int val;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%d\n", &val) != 1)
+ return -EINVAL;
+ if (val > (int)cpumask_weight(managed_clusters[i]->cpus))
+ return -EINVAL;
+
+ managed_clusters[i]->max_cpu_request = val;
+
+ cp = strnchr(cp, strlen(cp), ':');
+ cp++;
+ trace_set_max_cpus(cpumask_bits(managed_clusters[i]->cpus)[0],
+ val);
+ }
+
+ schedule_delayed_work(&evaluate_hotplug_work, 0);
+
+ return 0;
+}
+
+static int get_max_cpus(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%d:", managed_clusters[i]->max_cpu_request);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_max_cpus = {
+ .set = set_max_cpus,
+ .get = get_max_cpus,
+};
+
+#ifdef CONFIG_MSM_PERFORMANCE_HOTPLUG_ON
+device_param_cb(max_cpus, ¶m_ops_max_cpus, NULL, 0644);
+#endif
+
+static int set_managed_cpus(const char *buf, const struct kernel_param *kp)
+{
+ int i, ret;
+ struct cpumask tmp_mask;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ ret = cpulist_parse(buf, &tmp_mask);
+
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_clusters; i++) {
+ if (cpumask_empty(managed_clusters[i]->cpus)) {
+ mutex_lock(&managed_cpus_lock);
+ cpumask_copy(managed_clusters[i]->cpus, &tmp_mask);
+ cpumask_clear(managed_clusters[i]->offlined_cpus);
+ mutex_unlock(&managed_cpus_lock);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int get_managed_cpus(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0, total_cnt = 0;
+ char tmp[MAX_LENGTH_CPU_STRING] = "";
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++) {
+ cnt = cpumap_print_to_pagebuf(true, buf,
+ managed_clusters[i]->cpus);
+ if ((i + 1) < num_clusters &&
+ (total_cnt + cnt + 1) <= MAX_LENGTH_CPU_STRING) {
+ snprintf(tmp + total_cnt, cnt, "%s", buf);
+ tmp[cnt-1] = ':';
+ tmp[cnt] = '\0';
+ total_cnt += cnt;
+ } else if ((i + 1) == num_clusters &&
+ (total_cnt + cnt) <= MAX_LENGTH_CPU_STRING) {
+ snprintf(tmp + total_cnt, cnt, "%s", buf);
+ total_cnt += cnt;
+ } else {
+ pr_err("invalid string for managed_cpu:%s%s\n", tmp,
+ buf);
+ break;
+ }
+ }
+ snprintf(buf, PAGE_SIZE, "%s", tmp);
+ return total_cnt;
+}
+
+static const struct kernel_param_ops param_ops_managed_cpus = {
+ .set = set_managed_cpus,
+ .get = get_managed_cpus,
+};
+device_param_cb(managed_cpus, ¶m_ops_managed_cpus, NULL, 0644);
+
+/* Read-only node: To display all the online managed CPUs */
+static int get_managed_online_cpus(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0, total_cnt = 0;
+ char tmp[MAX_LENGTH_CPU_STRING] = "";
+ struct cpumask tmp_mask;
+ struct cluster *i_cl;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++) {
+ i_cl = managed_clusters[i];
+
+ cpumask_clear(&tmp_mask);
+ cpumask_complement(&tmp_mask, i_cl->offlined_cpus);
+ cpumask_and(&tmp_mask, i_cl->cpus, &tmp_mask);
+
+ cnt = cpumap_print_to_pagebuf(true, buf, &tmp_mask);
+ if ((i + 1) < num_clusters &&
+ (total_cnt + cnt + 1) <= MAX_LENGTH_CPU_STRING) {
+ snprintf(tmp + total_cnt, cnt, "%s", buf);
+ tmp[cnt-1] = ':';
+ tmp[cnt] = '\0';
+ total_cnt += cnt;
+ } else if ((i + 1) == num_clusters &&
+ (total_cnt + cnt) <= MAX_LENGTH_CPU_STRING) {
+ snprintf(tmp + total_cnt, cnt, "%s", buf);
+ total_cnt += cnt;
+ } else {
+ pr_err("invalid string for managed_cpu:%s%s\n", tmp,
+ buf);
+ break;
+ }
+ }
+ snprintf(buf, PAGE_SIZE, "%s", tmp);
+ return total_cnt;
+}
+
+static const struct kernel_param_ops param_ops_managed_online_cpus = {
+ .get = get_managed_online_cpus,
+};
+
+#ifdef CONFIG_MSM_PERFORMANCE_HOTPLUG_ON
+device_param_cb(managed_online_cpus, ¶m_ops_managed_online_cpus,
+ NULL, 0444);
+#endif
+/*
+ * Userspace sends cpu#:min_freq_value to vote for min_freq_value as the new
+ * scaling_min. To withdraw its vote it needs to enter cpu#:0
+ */
+static int set_cpu_min_freq(const char *buf, const struct kernel_param *kp)
+{
+ int i, j, ntokens = 0;
+ unsigned int val, cpu;
+ const char *cp = buf;
+ struct cpu_status *i_cpu_stats;
+ struct cpufreq_policy policy;
+ cpumask_var_t limit_mask;
+ int ret;
+
+ while ((cp = strpbrk(cp + 1, " :")))
+ ntokens++;
+
+ /* CPU:value pair */
+ if (!(ntokens % 2))
+ return -EINVAL;
+
+ cp = buf;
+ cpumask_clear(limit_mask);
+ for (i = 0; i < ntokens; i += 2) {
+ if (sscanf(cp, "%u:%u", &cpu, &val) != 2)
+ return -EINVAL;
+ if (cpu > (num_present_cpus() - 1))
+ return -EINVAL;
+
+ i_cpu_stats = &per_cpu(cpu_stats, cpu);
+
+ i_cpu_stats->min = val;
+ cpumask_set_cpu(cpu, limit_mask);
+
+ cp = strnchr(cp, strlen(cp), ' ');
+ cp++;
+ }
+
+ /*
+ * Since on synchronous systems policy is shared amongst multiple
+ * CPUs only one CPU needs to be updated for the limit to be
+ * reflected for the entire cluster. We can avoid updating the policy
+ * of other CPUs in the cluster once it is done for at least one CPU
+ * in the cluster
+ */
+ get_online_cpus();
+ for_each_cpu(i, limit_mask) {
+ i_cpu_stats = &per_cpu(cpu_stats, i);
+
+ if (cpufreq_get_policy(&policy, i))
+ continue;
+
+ if (cpu_online(i) && (policy.min != i_cpu_stats->min)) {
+ ret = cpufreq_update_policy(i);
+ if (ret)
+ continue;
+ }
+ for_each_cpu(j, policy.related_cpus)
+ cpumask_clear_cpu(j, limit_mask);
+ }
+ put_online_cpus();
+
+ return 0;
+}
+
+static int get_cpu_min_freq(char *buf, const struct kernel_param *kp)
+{
+ int cnt = 0, cpu;
+
+ for_each_present_cpu(cpu) {
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%d:%u ", cpu, per_cpu(cpu_stats, cpu).min);
+ }
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "\n");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_cpu_min_freq = {
+ .set = set_cpu_min_freq,
+ .get = get_cpu_min_freq,
+};
+module_param_cb(cpu_min_freq, ¶m_ops_cpu_min_freq, NULL, 0644);
+
+/*
+ * Userspace sends cpu#:max_freq_value to vote for max_freq_value as the new
+ * scaling_max. To withdraw its vote it needs to enter cpu#:UINT_MAX
+ */
+static int set_cpu_max_freq(const char *buf, const struct kernel_param *kp)
+{
+ int i, j, ntokens = 0;
+ unsigned int val, cpu;
+ const char *cp = buf;
+ struct cpu_status *i_cpu_stats;
+ struct cpufreq_policy policy;
+ cpumask_var_t limit_mask;
+ int ret;
+
+ while ((cp = strpbrk(cp + 1, " :")))
+ ntokens++;
+
+ /* CPU:value pair */
+ if (!(ntokens % 2))
+ return -EINVAL;
+
+ cp = buf;
+ cpumask_clear(limit_mask);
+ for (i = 0; i < ntokens; i += 2) {
+ if (sscanf(cp, "%u:%u", &cpu, &val) != 2)
+ return -EINVAL;
+ if (cpu > (num_present_cpus() - 1))
+ return -EINVAL;
+
+ i_cpu_stats = &per_cpu(cpu_stats, cpu);
+
+ i_cpu_stats->max = val;
+ cpumask_set_cpu(cpu, limit_mask);
+
+ cp = strnchr(cp, strlen(cp), ' ');
+ cp++;
+ }
+
+ get_online_cpus();
+ for_each_cpu(i, limit_mask) {
+ i_cpu_stats = &per_cpu(cpu_stats, i);
+ if (cpufreq_get_policy(&policy, i))
+ continue;
+
+ if (cpu_online(i) && (policy.max != i_cpu_stats->max)) {
+ ret = cpufreq_update_policy(i);
+ if (ret)
+ continue;
+ }
+ for_each_cpu(j, policy.related_cpus)
+ cpumask_clear_cpu(j, limit_mask);
+ }
+ put_online_cpus();
+
+ return 0;
+}
+
+static int get_cpu_max_freq(char *buf, const struct kernel_param *kp)
+{
+ int cnt = 0, cpu;
+
+ for_each_present_cpu(cpu) {
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%d:%u ", cpu, per_cpu(cpu_stats, cpu).max);
+ }
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "\n");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_cpu_max_freq = {
+ .set = set_cpu_max_freq,
+ .get = get_cpu_max_freq,
+};
+module_param_cb(cpu_max_freq, ¶m_ops_cpu_max_freq, NULL, 0644);
+
+static int set_ip_evt_trigger_threshold(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ thr.ip_evt_threshold = val;
+ return 0;
+}
+
+static int get_ip_evt_trigger_threshold(char *buf,
+ const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", thr.ip_evt_threshold);
+}
+
+static const struct kernel_param_ops param_ops_ip_evt_trig_thr = {
+ .set = set_ip_evt_trigger_threshold,
+ .get = get_ip_evt_trigger_threshold,
+};
+device_param_cb(ip_evt_trig_thr, ¶m_ops_ip_evt_trig_thr, NULL, 0644);
+
+
+static int set_perf_cl_trigger_threshold(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ thr.perf_cl_trigger_threshold = val;
+ return 0;
+}
+
+static int get_perf_cl_trigger_threshold(char *buf,
+ const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", thr.perf_cl_trigger_threshold);
+}
+
+static const struct kernel_param_ops param_ops_perf_trig_thr = {
+ .set = set_perf_cl_trigger_threshold,
+ .get = get_perf_cl_trigger_threshold,
+};
+device_param_cb(perf_cl_trig_thr, ¶m_ops_perf_trig_thr, NULL, 0644);
+
+
+static int set_pwr_cl_trigger_threshold(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ thr.pwr_cl_trigger_threshold = val;
+ return 0;
+}
+
+static int get_pwr_cl_trigger_threshold(char *buf,
+ const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", thr.pwr_cl_trigger_threshold);
+}
+
+static const struct kernel_param_ops param_ops_pwr_trig_thr = {
+ .set = set_pwr_cl_trigger_threshold,
+ .get = get_pwr_cl_trigger_threshold,
+};
+device_param_cb(pwr_cl_trig_thr, ¶m_ops_pwr_trig_thr, NULL, 0644);
+
+static int freq_greater_than_threshold(struct cluster *cl, int idx)
+{
+ int rc = 0;
+ /* Check for Cluster 0 */
+ if (!idx && cl->current_freq >= thr.pwr_cl_trigger_threshold)
+ rc = 1;
+ /* Check for Cluster 1 */
+ if (idx && cl->current_freq >= thr.perf_cl_trigger_threshold)
+ rc = 1;
+ return rc;
+}
+
+static bool input_events_greater_than_threshold(void)
+{
+
+ bool rc = false;
+
+ if ((ip_evts->evt_x_cnt >= thr.ip_evt_threshold) ||
+ (ip_evts->evt_y_cnt >= thr.ip_evt_threshold) ||
+ !use_input_evts_with_hi_slvt_detect)
+ rc = true;
+
+ return rc;
+}
+
+static int set_single_enter_load(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val < managed_clusters[i]->single_exit_load)
+ return -EINVAL;
+
+ managed_clusters[i]->single_enter_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_single_enter_load(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->single_enter_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_single_enter_load = {
+ .set = set_single_enter_load,
+ .get = get_single_enter_load,
+};
+device_param_cb(single_enter_load, ¶m_ops_single_enter_load, NULL, 0644);
+
+static int set_single_exit_load(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val > managed_clusters[i]->single_enter_load)
+ return -EINVAL;
+
+ managed_clusters[i]->single_exit_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_single_exit_load(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->single_exit_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_single_exit_load = {
+ .set = set_single_exit_load,
+ .get = get_single_exit_load,
+};
+device_param_cb(single_exit_load, ¶m_ops_single_exit_load, NULL, 0644);
+
+static int set_pcpu_multi_enter_load(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val < managed_clusters[i]->pcpu_multi_exit_load)
+ return -EINVAL;
+
+ managed_clusters[i]->pcpu_multi_enter_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_pcpu_multi_enter_load(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->pcpu_multi_enter_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_pcpu_multi_enter_load = {
+ .set = set_pcpu_multi_enter_load,
+ .get = get_pcpu_multi_enter_load,
+};
+device_param_cb(pcpu_multi_enter_load, ¶m_ops_pcpu_multi_enter_load,
+ NULL, 0644);
+
+static int set_pcpu_multi_exit_load(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val > managed_clusters[i]->pcpu_multi_enter_load)
+ return -EINVAL;
+
+ managed_clusters[i]->pcpu_multi_exit_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_pcpu_multi_exit_load(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->pcpu_multi_exit_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_pcpu_multi_exit_load = {
+ .set = set_pcpu_multi_exit_load,
+ .get = get_pcpu_multi_exit_load,
+};
+device_param_cb(pcpu_multi_exit_load, ¶m_ops_pcpu_multi_exit_load,
+ NULL, 0644);
+static int set_perf_cl_peak_enter_load(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val < managed_clusters[i]->perf_cl_peak_exit_load)
+ return -EINVAL;
+
+ managed_clusters[i]->perf_cl_peak_enter_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_perf_cl_peak_enter_load(char *buf,
+ const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->perf_cl_peak_enter_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_perf_cl_peak_enter_load = {
+ .set = set_perf_cl_peak_enter_load,
+ .get = get_perf_cl_peak_enter_load,
+};
+device_param_cb(perf_cl_peak_enter_load, ¶m_ops_perf_cl_peak_enter_load,
+ NULL, 0644);
+
+static int set_perf_cl_peak_exit_load(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val > managed_clusters[i]->perf_cl_peak_enter_load)
+ return -EINVAL;
+
+ managed_clusters[i]->perf_cl_peak_exit_load = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_perf_cl_peak_exit_load(char *buf,
+ const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->perf_cl_peak_exit_load);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_perf_cl_peak_exit_load = {
+ .set = set_perf_cl_peak_exit_load,
+ .get = get_perf_cl_peak_exit_load,
+};
+device_param_cb(perf_cl_peak_exit_load, ¶m_ops_perf_cl_peak_exit_load,
+ NULL, 0644);
+
+static int set_perf_cl_peak_enter_cycles(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->perf_cl_peak_enter_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_perf_cl_peak_enter_cycles(char *buf,
+ const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "%u:",
+ managed_clusters[i]->perf_cl_peak_enter_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_perf_cl_peak_enter_cycles = {
+ .set = set_perf_cl_peak_enter_cycles,
+ .get = get_perf_cl_peak_enter_cycles,
+};
+device_param_cb(perf_cl_peak_enter_cycles, ¶m_ops_perf_cl_peak_enter_cycles,
+ NULL, 0644);
+
+
+static int set_perf_cl_peak_exit_cycles(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->perf_cl_peak_exit_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_perf_cl_peak_exit_cycles(char *buf,
+ const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->perf_cl_peak_exit_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_perf_cl_peak_exit_cycles = {
+ .set = set_perf_cl_peak_exit_cycles,
+ .get = get_perf_cl_peak_exit_cycles,
+};
+device_param_cb(perf_cl_peak_exit_cycles, ¶m_ops_perf_cl_peak_exit_cycles,
+ NULL, 0644);
+
+
+static int set_single_enter_cycles(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->single_enter_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_single_enter_cycles(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "%u:",
+ managed_clusters[i]->single_enter_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_single_enter_cycles = {
+ .set = set_single_enter_cycles,
+ .get = get_single_enter_cycles,
+};
+device_param_cb(single_enter_cycles, ¶m_ops_single_enter_cycles,
+ NULL, 0644);
+
+
+static int set_single_exit_cycles(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->single_exit_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_single_exit_cycles(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->single_exit_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_single_exit_cycles = {
+ .set = set_single_exit_cycles,
+ .get = get_single_exit_cycles,
+};
+device_param_cb(single_exit_cycles, ¶m_ops_single_exit_cycles, NULL, 0644);
+
+static int set_multi_enter_cycles(const char *buf,
+ const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->multi_enter_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_multi_enter_cycles(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->multi_enter_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_multi_enter_cycles = {
+ .set = set_multi_enter_cycles,
+ .get = get_multi_enter_cycles,
+};
+device_param_cb(multi_enter_cycles, ¶m_ops_multi_enter_cycles, NULL, 0644);
+
+static int set_multi_exit_cycles(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val, i, ntokens = 0;
+ const char *cp = buf;
+ unsigned int bytes_left;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ while ((cp = strpbrk(cp + 1, ":")))
+ ntokens++;
+
+ if (ntokens != (num_clusters - 1))
+ return -EINVAL;
+
+ cp = buf;
+ for (i = 0; i < num_clusters; i++) {
+
+ if (sscanf(cp, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ managed_clusters[i]->multi_exit_cycles = val;
+
+ bytes_left = PAGE_SIZE - (cp - buf);
+ cp = strnchr(cp, bytes_left, ':');
+ cp++;
+ }
+
+ return 0;
+}
+
+static int get_multi_exit_cycles(char *buf, const struct kernel_param *kp)
+{
+ int i, cnt = 0;
+
+ if (!clusters_inited)
+ return cnt;
+
+ for (i = 0; i < num_clusters; i++)
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
+ "%u:", managed_clusters[i]->multi_exit_cycles);
+ cnt--;
+ cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, " ");
+ return cnt;
+}
+
+static const struct kernel_param_ops param_ops_multi_exit_cycles = {
+ .set = set_multi_exit_cycles,
+ .get = get_multi_exit_cycles,
+};
+device_param_cb(multi_exit_cycles, ¶m_ops_multi_exit_cycles, NULL, 0644);
+
+static int set_io_enter_cycles(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ io_enter_cycles = val;
+
+ return 0;
+}
+
+static int get_io_enter_cycles(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", io_enter_cycles);
+}
+
+static const struct kernel_param_ops param_ops_io_enter_cycles = {
+ .set = set_io_enter_cycles,
+ .get = get_io_enter_cycles,
+};
+device_param_cb(io_enter_cycles, ¶m_ops_io_enter_cycles, NULL, 0644);
+
+static int set_io_exit_cycles(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ io_exit_cycles = val;
+
+ return 0;
+}
+
+static int get_io_exit_cycles(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", io_exit_cycles);
+}
+
+static const struct kernel_param_ops param_ops_io_exit_cycles = {
+ .set = set_io_exit_cycles,
+ .get = get_io_exit_cycles,
+};
+device_param_cb(io_exit_cycles, ¶m_ops_io_exit_cycles, NULL, 0644);
+
+static int set_iowait_floor_pct(const char *buf, const struct kernel_param *kp)
+{
+ u64 val;
+
+ if (sscanf(buf, "%llu\n", &val) != 1)
+ return -EINVAL;
+ if (val > iowait_ceiling_pct)
+ return -EINVAL;
+
+ iowait_floor_pct = val;
+
+ return 0;
+}
+
+static int get_iowait_floor_pct(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%llu", iowait_floor_pct);
+}
+
+static const struct kernel_param_ops param_ops_iowait_floor_pct = {
+ .set = set_iowait_floor_pct,
+ .get = get_iowait_floor_pct,
+};
+device_param_cb(iowait_floor_pct, ¶m_ops_iowait_floor_pct, NULL, 0644);
+
+static int set_iowait_ceiling_pct(const char *buf,
+ const struct kernel_param *kp)
+{
+ u64 val;
+
+ if (sscanf(buf, "%llu\n", &val) != 1)
+ return -EINVAL;
+ if (val < iowait_floor_pct)
+ return -EINVAL;
+
+ iowait_ceiling_pct = val;
+
+ return 0;
+}
+
+static int get_iowait_ceiling_pct(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%llu", iowait_ceiling_pct);
+}
+
+static const struct kernel_param_ops param_ops_iowait_ceiling_pct = {
+ .set = set_iowait_ceiling_pct,
+ .get = get_iowait_ceiling_pct,
+};
+device_param_cb(iowait_ceiling_pct, ¶m_ops_iowait_ceiling_pct, NULL, 0644);
+
+static int set_workload_detect(const char *buf, const struct kernel_param *kp)
+{
+ unsigned int val, i;
+ struct cluster *i_cl;
+ unsigned long flags;
+
+ if (!clusters_inited)
+ return -EINVAL;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val == workload_detect)
+ return 0;
+
+ workload_detect = val;
+ if (!(workload_detect & IO_DETECT)) {
+ for (i = 0; i < num_clusters; i++) {
+ i_cl = managed_clusters[i];
+ spin_lock_irqsave(&i_cl->iowait_lock, flags);
+ i_cl->iowait_enter_cycle_cnt = 0;
+ i_cl->iowait_exit_cycle_cnt = 0;
+ i_cl->cur_io_busy = 0;
+ i_cl->io_change = true;
+ spin_unlock_irqrestore(&i_cl->iowait_lock, flags);
+ }
+ }
+ if (!(workload_detect & MODE_DETECT)) {
+ for (i = 0; i < num_clusters; i++) {
+ i_cl = managed_clusters[i];
+ spin_lock_irqsave(&i_cl->mode_lock, flags);
+ i_cl->single_enter_cycle_cnt = 0;
+ i_cl->single_exit_cycle_cnt = 0;
+ i_cl->multi_enter_cycle_cnt = 0;
+ i_cl->multi_exit_cycle_cnt = 0;
+ i_cl->mode = 0;
+ i_cl->mode_change = true;
+ spin_unlock_irqrestore(&i_cl->mode_lock, flags);
+ }
+ }
+
+ if (!(workload_detect & PERF_CL_PEAK_DETECT)) {
+ for (i = 0; i < num_clusters; i++) {
+ i_cl = managed_clusters[i];
+ spin_lock_irqsave(&i_cl->perf_cl_peak_lock, flags);
+ i_cl->perf_cl_peak_enter_cycle_cnt = 0;
+ i_cl->perf_cl_peak_exit_cycle_cnt = 0;
+ i_cl->perf_cl_peak = 0;
+ spin_unlock_irqrestore(&i_cl->perf_cl_peak_lock, flags);
+ }
+ }
+
+ wake_up_process(notify_thread);
+ return 0;
+}
+
+static int get_workload_detect(char *buf, const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u", workload_detect);
+}
+
+static const struct kernel_param_ops param_ops_workload_detect = {
+ .set = set_workload_detect,
+ .get = get_workload_detect,
+};
+device_param_cb(workload_detect, ¶m_ops_workload_detect, NULL, 0644);
+
+
+static int set_input_evts_with_hi_slvt_detect(const char *buf,
+ const struct kernel_param *kp)
+{
+
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+
+ if (val == use_input_evts_with_hi_slvt_detect)
+ return 0;
+
+ use_input_evts_with_hi_slvt_detect = val;
+
+ if ((workload_detect & PERF_CL_PEAK_DETECT) &&
+ !input_events_handler_registered &&
+ use_input_evts_with_hi_slvt_detect) {
+ if (register_input_handler() == -ENOMEM) {
+ use_input_evts_with_hi_slvt_detect = 0;
+ return -ENOMEM;
+ }
+ } else if ((workload_detect & PERF_CL_PEAK_DETECT) &&
+ input_events_handler_registered &&
+ !use_input_evts_with_hi_slvt_detect) {
+ unregister_input_handler();
+ }
+ return 0;
+}
+
+static int get_input_evts_with_hi_slvt_detect(char *buf,
+ const struct kernel_param *kp)
+{
+ return snprintf(buf, PAGE_SIZE, "%u",
+ use_input_evts_with_hi_slvt_detect);
+}
+
+static const struct kernel_param_ops param_ops_ip_evts_with_hi_slvt_detect = {
+ .set = set_input_evts_with_hi_slvt_detect,
+ .get = get_input_evts_with_hi_slvt_detect,
+};
+device_param_cb(input_evts_with_hi_slvt_detect,
+ ¶m_ops_ip_evts_with_hi_slvt_detect, NULL, 0644);
+
+static struct kobject *mode_kobj;
+
+static ssize_t show_aggr_mode(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u\n", aggr_mode);
+}
+static struct kobj_attribute aggr_mode_attr =
+__ATTR(aggr_mode, 0444, show_aggr_mode, NULL);
+
+static ssize_t show_aggr_iobusy(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u\n", aggr_iobusy);
+}
+static struct kobj_attribute aggr_iobusy_attr =
+__ATTR(aggr_iobusy, 0444, show_aggr_iobusy, NULL);
+
+static struct attribute *attrs[] = {
+ &aggr_mode_attr.attr,
+ &aggr_iobusy_attr.attr,
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = attrs,
+};
+
+static bool check_notify_status(void)
+{
+ int i;
+ struct cluster *cl;
+ bool any_change = false;
+ unsigned long flags;
+
+
+ for (i = 0; i < num_clusters; i++) {
+ cl = managed_clusters[i];
+ spin_lock_irqsave(&cl->iowait_lock, flags);
+ if (!any_change)
+ any_change = cl->io_change;
+ cl->io_change = false;
+ spin_unlock_irqrestore(&cl->iowait_lock, flags);
+
+ spin_lock_irqsave(&cl->mode_lock, flags);
+ if (!any_change)
+ any_change = cl->mode_change;
+ cl->mode_change = false;
+ spin_unlock_irqrestore(&cl->mode_lock, flags);
+
+ spin_lock_irqsave(&cl->perf_cl_peak_lock, flags);
+ if (!any_change)
+ any_change = cl->perf_cl_detect_state_change;
+ cl->perf_cl_detect_state_change = false;
+ spin_unlock_irqrestore(&cl->perf_cl_peak_lock, flags);
+ }
+
+ return any_change;
+}
+
+static int notify_userspace(void *data)
+{
+ unsigned int i, io, cpu_mode, perf_cl_peak_mode;
+
+ while (1) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (!check_notify_status()) {
+ schedule();
+
+ if (kthread_should_stop())
+ break;
+ }
+ set_current_state(TASK_RUNNING);
+
+ io = 0;
+ cpu_mode = 0;
+ perf_cl_peak_mode = 0;
+ for (i = 0; i < num_clusters; i++) {
+ io |= managed_clusters[i]->cur_io_busy;
+ cpu_mode |= managed_clusters[i]->mode;
+ perf_cl_peak_mode |= managed_clusters[i]->perf_cl_peak;
+ }
+ if (io != aggr_iobusy) {
+ aggr_iobusy = io;
+ sysfs_notify(mode_kobj, NULL, "aggr_iobusy");
+ pr_debug("msm_perf: Notifying IO: %u\n", aggr_iobusy);
+ }
+ if ((aggr_mode & (SINGLE | MULTI)) != cpu_mode) {
+ aggr_mode &= ~(SINGLE | MULTI);
+ aggr_mode |= cpu_mode;
+ sysfs_notify(mode_kobj, NULL, "aggr_mode");
+ pr_debug("msm_perf: Notifying CPU mode:%u\n",
+ aggr_mode);
+ }
+ if ((aggr_mode & PERF_CL_PEAK) != perf_cl_peak_mode) {
+ aggr_mode &= ~(PERF_CL_PEAK);
+ aggr_mode |= perf_cl_peak_mode;
+ sysfs_notify(mode_kobj, NULL, "aggr_mode");
+ pr_debug("msm_perf: Notifying Gaming mode:%u\n",
+ aggr_mode);
+ }
+ }
+
+ return 0;
+}
+
+static void check_cluster_iowait(struct cluster *cl, u64 now)
+{
+ struct load_stats *pcpu_st;
+ unsigned int i;
+ unsigned long flags;
+ unsigned int temp_iobusy;
+ u64 max_iowait = 0;
+
+ spin_lock_irqsave(&cl->iowait_lock, flags);
+
+ if (((now - cl->last_io_check_ts)
+ < (cl->timer_rate - LAST_IO_CHECK_TOL)) ||
+ !(workload_detect & IO_DETECT)) {
+ spin_unlock_irqrestore(&cl->iowait_lock, flags);
+ return;
+ }
+
+ temp_iobusy = cl->cur_io_busy;
+ for_each_cpu(i, cl->cpus) {
+ pcpu_st = &per_cpu(cpu_load_stats, i);
+ if ((now - pcpu_st->last_wallclock)
+ > (cl->timer_rate + LAST_UPDATE_TOL))
+ continue;
+ if (max_iowait < pcpu_st->last_iopercent)
+ max_iowait = pcpu_st->last_iopercent;
+ }
+
+ if (!cl->cur_io_busy) {
+ if (max_iowait > iowait_ceiling_pct) {
+ cl->iowait_enter_cycle_cnt++;
+ if (cl->iowait_enter_cycle_cnt >= io_enter_cycles) {
+ cl->cur_io_busy = 1;
+ cl->iowait_enter_cycle_cnt = 0;
+ }
+ } else {
+ cl->iowait_enter_cycle_cnt = 0;
+ }
+ } else {
+ if (max_iowait < iowait_floor_pct) {
+ cl->iowait_exit_cycle_cnt++;
+ if (cl->iowait_exit_cycle_cnt >= io_exit_cycles) {
+ cl->cur_io_busy = 0;
+ cl->iowait_exit_cycle_cnt = 0;
+ }
+ } else {
+ cl->iowait_exit_cycle_cnt = 0;
+ }
+ }
+
+ cl->last_io_check_ts = now;
+ trace_track_iowait(cpumask_first(cl->cpus), cl->iowait_enter_cycle_cnt,
+ cl->iowait_exit_cycle_cnt, cl->cur_io_busy, max_iowait);
+
+ if (temp_iobusy != cl->cur_io_busy) {
+ cl->io_change = true;
+ pr_debug("msm_perf: IO changed to %u\n", cl->cur_io_busy);
+ }
+
+ spin_unlock_irqrestore(&cl->iowait_lock, flags);
+ if (cl->io_change)
+ wake_up_process(notify_thread);
+}
+
+static void disable_timer(struct cluster *cl)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cl->timer_lock, flags);
+
+ if (del_timer(&cl->mode_exit_timer)) {
+ trace_single_cycle_exit_timer_stop(cpumask_first(cl->cpus),
+ cl->single_enter_cycles, cl->single_enter_cycle_cnt,
+ cl->single_exit_cycles, cl->single_exit_cycle_cnt,
+ cl->multi_enter_cycles, cl->multi_enter_cycle_cnt,
+ cl->multi_exit_cycles, cl->multi_exit_cycle_cnt,
+ cl->timer_rate, cl->mode);
+ }
+
+ spin_unlock_irqrestore(&cl->timer_lock, flags);
+}
+
+static void start_timer(struct cluster *cl)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cl->timer_lock, flags);
+ if ((cl->mode & SINGLE) && !timer_pending(&cl->mode_exit_timer)) {
+ /* Set timer for the Cluster since there is none pending */
+ cl->mode_exit_timer.expires = get_jiffies_64() +
+ usecs_to_jiffies(cl->single_exit_cycles * cl->timer_rate);
+ cl->mode_exit_timer.data = cpumask_first(cl->cpus);
+ add_timer(&cl->mode_exit_timer);
+ trace_single_cycle_exit_timer_start(cpumask_first(cl->cpus),
+ cl->single_enter_cycles, cl->single_enter_cycle_cnt,
+ cl->single_exit_cycles, cl->single_exit_cycle_cnt,
+ cl->multi_enter_cycles, cl->multi_enter_cycle_cnt,
+ cl->multi_exit_cycles, cl->multi_exit_cycle_cnt,
+ cl->timer_rate, cl->mode);
+ }
+ spin_unlock_irqrestore(&cl->timer_lock, flags);
+}
+
+static void disable_perf_cl_peak_timer(struct cluster *cl)
+{
+
+ if (del_timer(&cl->perf_cl_peak_mode_exit_timer)) {
+ trace_perf_cl_peak_exit_timer_stop(cpumask_first(cl->cpus),
+ cl->perf_cl_peak_enter_cycles,
+ cl->perf_cl_peak_enter_cycle_cnt,
+ cl->perf_cl_peak_exit_cycles,
+ cl->perf_cl_peak_exit_cycle_cnt,
+ cl->timer_rate, cl->mode);
+ }
+
+}
+
+static void start_perf_cl_peak_timer(struct cluster *cl)
+{
+ if ((cl->mode & PERF_CL_PEAK) &&
+ !timer_pending(&cl->perf_cl_peak_mode_exit_timer)) {
+ /* Set timer for the Cluster since there is none pending */
+ cl->perf_cl_peak_mode_exit_timer.expires = get_jiffies_64() +
+ usecs_to_jiffies(cl->perf_cl_peak_exit_cycles * cl->timer_rate);
+ cl->perf_cl_peak_mode_exit_timer.data = cpumask_first(cl->cpus);
+ add_timer(&cl->perf_cl_peak_mode_exit_timer);
+ trace_perf_cl_peak_exit_timer_start(cpumask_first(cl->cpus),
+ cl->perf_cl_peak_enter_cycles,
+ cl->perf_cl_peak_enter_cycle_cnt,
+ cl->perf_cl_peak_exit_cycles,
+ cl->perf_cl_peak_exit_cycle_cnt,
+ cl->timer_rate, cl->mode);
+ }
+}
+
+static const struct input_device_id msm_perf_input_ids[] = {
+
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = {BIT_MASK(EV_ABS)},
+ .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
+ BIT_MASK(ABS_MT_POSITION_X) |
+ BIT_MASK(ABS_MT_POSITION_Y)},
+ },
+
+ {},
+};
+
+static void msm_perf_input_event_handler(struct input_handle *handle,
+ unsigned int type,
+ unsigned int code,
+ int value)
+{
+ if (type != EV_ABS)
+ return;
+
+ switch (code) {
+
+ case ABS_MT_POSITION_X:
+ ip_evts->evt_x_cnt++;
+ break;
+ case ABS_MT_POSITION_Y:
+ ip_evts->evt_y_cnt++;
+ break;
+
+ case ABS_MT_DISTANCE:
+ break;
+
+ case ABS_MT_PRESSURE:
+ break;
+
+ default:
+ break;
+
+ }
+}
+static int msm_perf_input_connect(struct input_handler *handler,
+ struct input_dev *dev,
+ const struct input_device_id *id)
+{
+ int rc;
+ struct input_handle *handle;
+
+ handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+ if (!handle)
+ return -ENOMEM;
+
+ handle->dev = dev;
+ handle->handler = handler;
+ handle->name = handler->name;
+
+ rc = input_register_handle(handle);
+ if (rc) {
+ pr_err("Failed to register handle\n");
+ goto error;
+ }
+
+ rc = input_open_device(handle);
+ if (rc) {
+ pr_err("Failed to open device\n");
+ goto error_unregister;
+ }
+ return 0;
+
+error_unregister:
+ input_unregister_handle(handle);
+error:
+ kfree(handle);
+ return rc;
+}
+
+static void msm_perf_input_disconnect(struct input_handle *handle)
+{
+ input_close_device(handle);
+ input_unregister_handle(handle);
+ kfree(handle);
+}
+
+static void unregister_input_handler(void)
+{
+ if (handler != NULL) {
+ input_unregister_handler(handler);
+ input_events_handler_registered = false;
+ }
+}
+
+static int register_input_handler(void)
+{
+ int rc;
+
+ if (handler == NULL) {
+ handler = kzalloc(sizeof(*handler), GFP_KERNEL);
+ if (!handler)
+ return -ENOMEM;
+ handler->event = msm_perf_input_event_handler;
+ handler->connect = msm_perf_input_connect;
+ handler->disconnect = msm_perf_input_disconnect;
+ handler->name = "msm_perf";
+ handler->id_table = msm_perf_input_ids;
+ handler->private = NULL;
+ }
+ rc = input_register_handler(handler);
+ if (rc) {
+ pr_err("Unable to register the input handler for msm_perf\n");
+ kfree(handler);
+ } else {
+ input_events_handler_registered = true;
+ }
+ return rc;
+}
+
+static void check_perf_cl_peak_load(struct cluster *cl, u64 now)
+{
+ struct load_stats *pcpu_st;
+ unsigned int i, ret_mode, max_load = 0;
+ unsigned int total_load = 0, cpu_cnt = 0;
+ unsigned long flags;
+ bool cpu_of_cluster_zero = true;
+
+ spin_lock_irqsave(&cl->perf_cl_peak_lock, flags);
+
+ cpu_of_cluster_zero = cpumask_first(cl->cpus) ? false:true;
+ /*
+ * If delta of last load to now < than timer_rate - ld check tolerance
+ * which is 18ms OR if perf_cl_peak detection not set
+ * OR the first CPU of Cluster is CPU 0 (LVT)
+ * then return do nothing. We are interested only in SLVT
+ */
+ if (((now - cl->last_perf_cl_check_ts)
+ < (cl->timer_rate - LAST_LD_CHECK_TOL)) ||
+ !(workload_detect & PERF_CL_PEAK_DETECT) ||
+ cpu_of_cluster_zero) {
+ spin_unlock_irqrestore(&cl->perf_cl_peak_lock, flags);
+ return;
+ }
+ for_each_cpu(i, cl->cpus) {
+ pcpu_st = &per_cpu(cpu_load_stats, i);
+ if ((now - pcpu_st->last_wallclock)
+ > (cl->timer_rate + LAST_UPDATE_TOL))
+ continue;
+ if (pcpu_st->cpu_load > max_load)
+ max_load = pcpu_st->cpu_load;
+ /*
+ * Save the frequency for the cpu of the cluster
+ * This frequency is the most recent/current
+ * as obtained due to a transition
+ * notifier callback.
+ */
+ cl->current_freq = pcpu_st->freq;
+ }
+ ret_mode = cl->perf_cl_peak;
+
+ if (!(cl->perf_cl_peak & PERF_CL_PEAK)) {
+ if (max_load >= cl->perf_cl_peak_enter_load &&
+ freq_greater_than_threshold(cl,
+ cpumask_first(cl->cpus))) {
+ /*
+ * Reset the event count for the first cycle
+ * of perf_cl_peak we detect
+ */
+ if (!cl->perf_cl_peak_enter_cycle_cnt)
+ ip_evts->evt_x_cnt = ip_evts->evt_y_cnt = 0;
+ cl->perf_cl_peak_enter_cycle_cnt++;
+ if (cl->perf_cl_peak_enter_cycle_cnt >=
+ cl->perf_cl_peak_enter_cycles) {
+ if (input_events_greater_than_threshold())
+ ret_mode |= PERF_CL_PEAK;
+ cl->perf_cl_peak_enter_cycle_cnt = 0;
+ }
+ } else {
+ cl->perf_cl_peak_enter_cycle_cnt = 0;
+ /* Reset the event count */
+ ip_evts->evt_x_cnt = ip_evts->evt_y_cnt = 0;
+ }
+ } else {
+ if (max_load >= cl->perf_cl_peak_exit_load &&
+ freq_greater_than_threshold(cl,
+ cpumask_first(cl->cpus))) {
+ cl->perf_cl_peak_exit_cycle_cnt = 0;
+ disable_perf_cl_peak_timer(cl);
+ } else {
+ start_perf_cl_peak_timer(cl);
+ cl->perf_cl_peak_exit_cycle_cnt++;
+ if (cl->perf_cl_peak_exit_cycle_cnt
+ >= cl->perf_cl_peak_exit_cycles) {
+ ret_mode &= ~PERF_CL_PEAK;
+ cl->perf_cl_peak_exit_cycle_cnt = 0;
+ disable_perf_cl_peak_timer(cl);
+ }
+ }
+ }
+
+ cl->last_perf_cl_check_ts = now;
+ if (ret_mode != cl->perf_cl_peak) {
+ pr_debug("msm_perf: Mode changed to %u\n", ret_mode);
+ cl->perf_cl_peak = ret_mode;
+ cl->perf_cl_detect_state_change = true;
+ }
+
+ trace_cpu_mode_detect(cpumask_first(cl->cpus), max_load,
+ cl->single_enter_cycle_cnt, cl->single_exit_cycle_cnt,
+ total_load, cl->multi_enter_cycle_cnt,
+ cl->multi_exit_cycle_cnt, cl->perf_cl_peak_enter_cycle_cnt,
+ cl->perf_cl_peak_exit_cycle_cnt, cl->mode, cpu_cnt);
+
+ spin_unlock_irqrestore(&cl->perf_cl_peak_lock, flags);
+
+ if (cl->perf_cl_detect_state_change)
+ wake_up_process(notify_thread);
+
+}
+
+static void check_cpu_load(struct cluster *cl, u64 now)
+{
+ struct load_stats *pcpu_st;
+ unsigned int i, max_load = 0, total_load = 0, ret_mode, cpu_cnt = 0;
+ unsigned int total_load_ceil, total_load_floor;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cl->mode_lock, flags);
+
+ if (((now - cl->last_mode_check_ts)
+ < (cl->timer_rate - LAST_LD_CHECK_TOL)) ||
+ !(workload_detect & MODE_DETECT)) {
+ spin_unlock_irqrestore(&cl->mode_lock, flags);
+ return;
+ }
+
+ for_each_cpu(i, cl->cpus) {
+ pcpu_st = &per_cpu(cpu_load_stats, i);
+ if ((now - pcpu_st->last_wallclock)
+ > (cl->timer_rate + LAST_UPDATE_TOL))
+ continue;
+ if (pcpu_st->cpu_load > max_load)
+ max_load = pcpu_st->cpu_load;
+ total_load += pcpu_st->cpu_load;
+ cpu_cnt++;
+ }
+
+ if (cpu_cnt > 1) {
+ total_load_ceil = cl->pcpu_multi_enter_load * cpu_cnt;
+ total_load_floor = cl->pcpu_multi_exit_load * cpu_cnt;
+ } else {
+ total_load_ceil = UINT_MAX;
+ total_load_floor = UINT_MAX;
+ }
+
+ ret_mode = cl->mode;
+ if (!(cl->mode & SINGLE)) {
+ if (max_load >= cl->single_enter_load) {
+ cl->single_enter_cycle_cnt++;
+ if (cl->single_enter_cycle_cnt
+ >= cl->single_enter_cycles) {
+ ret_mode |= SINGLE;
+ cl->single_enter_cycle_cnt = 0;
+ }
+ } else {
+ cl->single_enter_cycle_cnt = 0;
+ }
+ } else {
+ if (max_load < cl->single_exit_load) {
+ start_timer(cl);
+ cl->single_exit_cycle_cnt++;
+ if (cl->single_exit_cycle_cnt
+ >= cl->single_exit_cycles) {
+ ret_mode &= ~SINGLE;
+ cl->single_exit_cycle_cnt = 0;
+ disable_timer(cl);
+ }
+ } else {
+ cl->single_exit_cycle_cnt = 0;
+ disable_timer(cl);
+ }
+ }
+
+ if (!(cl->mode & MULTI)) {
+ if (total_load >= total_load_ceil) {
+ cl->multi_enter_cycle_cnt++;
+ if (cl->multi_enter_cycle_cnt
+ >= cl->multi_enter_cycles) {
+ ret_mode |= MULTI;
+ cl->multi_enter_cycle_cnt = 0;
+ }
+ } else {
+ cl->multi_enter_cycle_cnt = 0;
+ }
+ } else {
+ if (total_load < total_load_floor) {
+ cl->multi_exit_cycle_cnt++;
+ if (cl->multi_exit_cycle_cnt
+ >= cl->multi_exit_cycles) {
+ ret_mode &= ~MULTI;
+ cl->multi_exit_cycle_cnt = 0;
+ }
+ } else {
+ cl->multi_exit_cycle_cnt = 0;
+ }
+ }
+
+ cl->last_mode_check_ts = now;
+
+ if (ret_mode != cl->mode) {
+ cl->mode = ret_mode;
+ cl->mode_change = true;
+ pr_debug("msm_perf: Mode changed to %u\n", ret_mode);
+ }
+
+ trace_cpu_mode_detect(cpumask_first(cl->cpus), max_load,
+ cl->single_enter_cycle_cnt, cl->single_exit_cycle_cnt,
+ total_load, cl->multi_enter_cycle_cnt,
+ cl->multi_exit_cycle_cnt, cl->perf_cl_peak_enter_cycle_cnt,
+ cl->perf_cl_peak_exit_cycle_cnt, cl->mode, cpu_cnt);
+
+ spin_unlock_irqrestore(&cl->mode_lock, flags);
+
+ if (cl->mode_change)
+ wake_up_process(notify_thread);
+}
+
+static void check_workload_stats(unsigned int cpu, unsigned int rate, u64 now)
+{
+ struct cluster *cl = NULL;
+ unsigned int i;
+
+ for (i = 0; i < num_clusters; i++) {
+ if (cpumask_test_cpu(cpu, managed_clusters[i]->cpus)) {
+ cl = managed_clusters[i];
+ break;
+ }
+ }
+ if (cl == NULL)
+ return;
+
+ cl->timer_rate = rate;
+ check_cluster_iowait(cl, now);
+ check_cpu_load(cl, now);
+ check_perf_cl_peak_load(cl, now);
+}
+
+static int perf_govinfo_notify(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ struct cpufreq_govinfo *gov_info = data;
+ unsigned int cpu = gov_info->cpu;
+ struct load_stats *cpu_st = &per_cpu(cpu_load_stats, cpu);
+ u64 now, cur_iowait, time_diff, iowait_diff;
+
+ if (!clusters_inited || !workload_detect)
+ return NOTIFY_OK;
+
+ cur_iowait = get_cpu_iowait_time_us(cpu, &now);
+ if (cur_iowait >= cpu_st->last_iowait)
+ iowait_diff = cur_iowait - cpu_st->last_iowait;
+ else
+ iowait_diff = 0;
+
+ if (now > cpu_st->last_wallclock)
+ time_diff = now - cpu_st->last_wallclock;
+ else
+ return NOTIFY_OK;
+
+ if (iowait_diff <= time_diff) {
+ iowait_diff *= 100;
+ cpu_st->last_iopercent = div64_u64(iowait_diff, time_diff);
+ } else {
+ cpu_st->last_iopercent = 100;
+ }
+
+ cpu_st->last_wallclock = now;
+ cpu_st->last_iowait = cur_iowait;
+ cpu_st->cpu_load = gov_info->load;
+
+ /*
+ * Avoid deadlock in case governor notifier ran in the context
+ * of notify_work thread
+ */
+ if (current == notify_thread)
+ return NOTIFY_OK;
+
+ check_workload_stats(cpu, gov_info->sampling_rate_us, now);
+
+ return NOTIFY_OK;
+}
+
+static int perf_cputrans_notify(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ struct cpufreq_freqs *freq = data;
+ unsigned int cpu = freq->cpu;
+ unsigned long flags;
+ unsigned int i;
+ struct cluster *cl = NULL;
+ struct load_stats *cpu_st = &per_cpu(cpu_load_stats, cpu);
+
+ if (!clusters_inited || !workload_detect)
+ return NOTIFY_OK;
+ for (i = 0; i < num_clusters; i++) {
+ if (cpumask_test_cpu(cpu, managed_clusters[i]->cpus)) {
+ cl = managed_clusters[i];
+ break;
+ }
+ }
+ if (cl == NULL)
+ return NOTIFY_OK;
+ if (val == CPUFREQ_POSTCHANGE) {
+ spin_lock_irqsave(&cl->perf_cl_peak_lock, flags);
+ cpu_st->freq = freq->new;
+ spin_unlock_irqrestore(&cl->perf_cl_peak_lock, flags);
+ }
+
+ /*
+ * Avoid deadlock in case governor notifier ran in the context
+ * of notify_work thread
+ */
+ if (current == notify_thread)
+ return NOTIFY_OK;
+ return NOTIFY_OK;
+}
+
+static struct notifier_block perf_govinfo_nb = {
+ .notifier_call = perf_govinfo_notify,
+};
+
+static struct notifier_block perf_cputransitions_nb = {
+ .notifier_call = perf_cputrans_notify,
+};
+
+static void single_mod_exit_timer(unsigned long data)
+{
+ int i;
+ struct cluster *i_cl = NULL;
+ unsigned long flags;
+
+ if (!clusters_inited)
+ return;
+
+ for (i = 0; i < num_clusters; i++) {
+ if (cpumask_test_cpu(data,
+ managed_clusters[i]->cpus)) {
+ i_cl = managed_clusters[i];
+ break;
+ }
+ }
+
+ if (i_cl == NULL)
+ return;
+
+ spin_lock_irqsave(&i_cl->mode_lock, flags);
+ if (i_cl->mode & SINGLE) {
+ /* Disable SINGLE mode and exit since the timer expired */
+ i_cl->mode = i_cl->mode & ~SINGLE;
+ i_cl->single_enter_cycle_cnt = 0;
+ i_cl->single_exit_cycle_cnt = 0;
+ trace_single_mode_timeout(cpumask_first(i_cl->cpus),
+ i_cl->single_enter_cycles, i_cl->single_enter_cycle_cnt,
+ i_cl->single_exit_cycles, i_cl->single_exit_cycle_cnt,
+ i_cl->multi_enter_cycles, i_cl->multi_enter_cycle_cnt,
+ i_cl->multi_exit_cycles, i_cl->multi_exit_cycle_cnt,
+ i_cl->timer_rate, i_cl->mode);
+ }
+ spin_unlock_irqrestore(&i_cl->mode_lock, flags);
+ wake_up_process(notify_thread);
+}
+
+static void perf_cl_peak_mod_exit_timer(unsigned long data)
+{
+ int i;
+ struct cluster *i_cl = NULL;
+ unsigned long flags;
+
+ if (!clusters_inited)
+ return;
+
+ for (i = 0; i < num_clusters; i++) {
+ if (cpumask_test_cpu(data,
+ managed_clusters[i]->cpus)) {
+ i_cl = managed_clusters[i];
+ break;
+ }
+ }
+
+ if (i_cl == NULL)
+ return;
+
+ spin_lock_irqsave(&i_cl->perf_cl_peak_lock, flags);
+ if (i_cl->perf_cl_peak & PERF_CL_PEAK) {
+ /* Disable PERF_CL_PEAK mode and exit since the timer expired */
+ i_cl->perf_cl_peak = i_cl->perf_cl_peak & ~PERF_CL_PEAK;
+ i_cl->perf_cl_peak_enter_cycle_cnt = 0;
+ i_cl->perf_cl_peak_exit_cycle_cnt = 0;
+ }
+ spin_unlock_irqrestore(&i_cl->perf_cl_peak_lock, flags);
+ wake_up_process(notify_thread);
+}
+
+/* CPU Hotplug */
+static struct kobject *events_kobj;
+
+static ssize_t show_cpu_hotplug(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "\n");
+}
+static struct kobj_attribute cpu_hotplug_attr =
+__ATTR(cpu_hotplug, 0444, show_cpu_hotplug, NULL);
+
+static struct attribute *events_attrs[] = {
+ &cpu_hotplug_attr.attr,
+ NULL,
+};
+
+static struct attribute_group events_attr_group = {
+ .attrs = events_attrs,
+};
+/*******************************sysfs ends************************************/
+
+static unsigned int num_online_managed(struct cpumask *mask)
+{
+ struct cpumask tmp_mask;
+
+ cpumask_clear(&tmp_mask);
+ cpumask_and(&tmp_mask, mask, cpu_online_mask);
+
+ return cpumask_weight(&tmp_mask);
+}
+
+static int perf_adjust_notify(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ struct cpufreq_policy *policy = data;
+ unsigned int cpu = policy->cpu;
+ struct cpu_status *cpu_st = &per_cpu(cpu_stats, cpu);
+ unsigned int min = cpu_st->min, max = cpu_st->max;
+
+
+ if (val != CPUFREQ_ADJUST)
+ return NOTIFY_OK;
+
+ pr_debug("msm_perf: CPU%u policy before: %u:%u kHz\n", cpu,
+ policy->min, policy->max);
+ pr_debug("msm_perf: CPU%u seting min:max %u:%u kHz\n", cpu, min, max);
+
+ cpufreq_verify_within_limits(policy, min, max);
+
+ pr_debug("msm_perf: CPU%u policy after: %u:%u kHz\n", cpu,
+ policy->min, policy->max);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block perf_cpufreq_nb = {
+ .notifier_call = perf_adjust_notify,
+};
+
+static void hotplug_notify(int action)
+{
+ unsigned long flags;
+
+ if (!events_group.init_success)
+ return;
+
+ if ((action == CPU_ONLINE) || (action == CPU_DEAD)) {
+ spin_lock_irqsave(&(events_group.cpu_hotplug_lock), flags);
+ events_group.cpu_hotplug = true;
+ spin_unlock_irqrestore(&(events_group.cpu_hotplug_lock), flags);
+ wake_up_process(events_notify_thread);
+ }
+}
+
+static int events_notify_userspace(void *data)
+{
+ unsigned long flags;
+ bool notify_change;
+
+ while (1) {
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ spin_lock_irqsave(&(events_group.cpu_hotplug_lock), flags);
+
+ if (!events_group.cpu_hotplug) {
+ spin_unlock_irqrestore(&(events_group.cpu_hotplug_lock),
+ flags);
+
+ schedule();
+ if (kthread_should_stop())
+ break;
+ spin_lock_irqsave(&(events_group.cpu_hotplug_lock),
+ flags);
+ }
+
+ set_current_state(TASK_RUNNING);
+ notify_change = events_group.cpu_hotplug;
+ events_group.cpu_hotplug = false;
+ spin_unlock_irqrestore(&(events_group.cpu_hotplug_lock), flags);
+
+ if (notify_change)
+ sysfs_notify(events_kobj, NULL, "cpu_hotplug");
+ }
+
+ return 0;
+}
+
+/*
+ * Attempt to offline CPUs based on their power cost.
+ * CPUs with higher power costs are offlined first.
+ */
+static int __ref rm_high_pwr_cost_cpus(struct cluster *cl)
+{
+ unsigned int cpu, i;
+ struct cpu_pwr_stats *per_cpu_info = get_cpu_pwr_stats();
+ struct cpu_pstate_pwr *costs;
+ unsigned int *pcpu_pwr;
+ unsigned int max_cost_cpu, max_cost;
+ int any_cpu = -1;
+
+ if (!per_cpu_info)
+ return -EAGAIN;
+
+ for_each_cpu(cpu, cl->cpus) {
+ costs = per_cpu_info[cpu].ptable;
+ if (!costs || !costs[0].freq)
+ continue;
+
+ i = 1;
+ while (costs[i].freq)
+ i++;
+
+ pcpu_pwr = &per_cpu(cpu_power_cost, cpu);
+ *pcpu_pwr = costs[i - 1].power;
+ any_cpu = (int)cpu;
+ pr_debug("msm_perf: CPU:%d Power:%u\n", cpu, *pcpu_pwr);
+ }
+
+ if (any_cpu < 0)
+ return -EAGAIN;
+
+ for (i = 0; i < cpumask_weight(cl->cpus); i++) {
+ max_cost = 0;
+ max_cost_cpu = cpumask_first(cl->cpus);
+
+ for_each_cpu(cpu, cl->cpus) {
+ pcpu_pwr = &per_cpu(cpu_power_cost, cpu);
+ if (max_cost < *pcpu_pwr) {
+ max_cost = *pcpu_pwr;
+ max_cost_cpu = cpu;
+ }
+ }
+
+ if (!cpu_online(max_cost_cpu))
+ goto end;
+
+ pr_debug("msm_perf: Offlining CPU%d Power:%d\n", max_cost_cpu,
+ max_cost);
+ cpumask_set_cpu(max_cost_cpu, cl->offlined_cpus);
+ lock_device_hotplug();
+ if (device_offline(get_cpu_device(max_cost_cpu))) {
+ cpumask_clear_cpu(max_cost_cpu, cl->offlined_cpus);
+ pr_debug("msm_perf: Offlining CPU%d failed\n",
+ max_cost_cpu);
+ }
+ unlock_device_hotplug();
+
+end:
+ pcpu_pwr = &per_cpu(cpu_power_cost, max_cost_cpu);
+ *pcpu_pwr = 0;
+ if (num_online_managed(cl->cpus) <= cl->max_cpu_request)
+ break;
+ }
+
+ if (num_online_managed(cl->cpus) > cl->max_cpu_request)
+ return -EAGAIN;
+ else
+ return 0;
+}
+
+/*
+ * try_hotplug tries to online/offline cores based on the current requirement.
+ * It loops through the currently managed CPUs and tries to online/offline
+ * them until the max_cpu_request criteria is met.
+ */
+static void __ref try_hotplug(struct cluster *data)
+{
+ unsigned int i;
+
+ if (!clusters_inited)
+ return;
+
+ pr_debug("msm_perf: Trying hotplug...%d:%d\n",
+ num_online_managed(data->cpus), num_online_cpus());
+
+ mutex_lock(&managed_cpus_lock);
+ if (num_online_managed(data->cpus) > data->max_cpu_request) {
+ if (!rm_high_pwr_cost_cpus(data)) {
+ mutex_unlock(&managed_cpus_lock);
+ return;
+ }
+
+ /*
+ * If power aware offlining fails due to power cost info
+ * being unavaiable fall back to original implementation
+ */
+ for (i = num_present_cpus() - 1; i >= 0 &&
+ i < num_present_cpus(); i--) {
+ if (!cpumask_test_cpu(i, data->cpus) || !cpu_online(i))
+ continue;
+
+ pr_debug("msm_perf: Offlining CPU%d\n", i);
+ cpumask_set_cpu(i, data->offlined_cpus);
+ lock_device_hotplug();
+ if (device_offline(get_cpu_device(i))) {
+ cpumask_clear_cpu(i, data->offlined_cpus);
+ pr_debug("msm_perf: Offlining CPU%d failed\n",
+ i);
+ unlock_device_hotplug();
+ continue;
+ }
+ unlock_device_hotplug();
+ if (num_online_managed(data->cpus) <=
+ data->max_cpu_request)
+ break;
+ }
+ } else {
+ for_each_cpu(i, data->cpus) {
+ if (cpu_online(i))
+ continue;
+ pr_debug("msm_perf: Onlining CPU%d\n", i);
+ lock_device_hotplug();
+ if (device_online(get_cpu_device(i))) {
+ pr_debug("msm_perf: Onlining CPU%d failed\n",
+ i);
+ unlock_device_hotplug();
+ continue;
+ }
+ unlock_device_hotplug();
+ cpumask_clear_cpu(i, data->offlined_cpus);
+ if (num_online_managed(data->cpus) >=
+ data->max_cpu_request)
+ break;
+ }
+ }
+ mutex_unlock(&managed_cpus_lock);
+}
+
+static void __ref release_cluster_control(struct cpumask *off_cpus)
+{
+ int cpu;
+
+ for_each_cpu(cpu, off_cpus) {
+ pr_debug("msm_perf: Release CPU %d\n", cpu);
+ lock_device_hotplug();
+ if (!device_online(get_cpu_device(cpu)))
+ cpumask_clear_cpu(cpu, off_cpus);
+ unlock_device_hotplug();
+ }
+}
+
+/* Work to evaluate current online CPU status and hotplug CPUs as per need */
+static void check_cluster_status(struct work_struct *work)
+{
+ int i;
+ struct cluster *i_cl;
+
+ for (i = 0; i < num_clusters; i++) {
+ i_cl = managed_clusters[i];
+
+ if (cpumask_empty(i_cl->cpus))
+ continue;
+
+ if (i_cl->max_cpu_request < 0) {
+ if (!cpumask_empty(i_cl->offlined_cpus))
+ release_cluster_control(i_cl->offlined_cpus);
+ continue;
+ }
+
+ if (num_online_managed(i_cl->cpus) !=
+ i_cl->max_cpu_request)
+ try_hotplug(i_cl);
+ }
+}
+
+static int __ref msm_performance_cpu_callback(struct notifier_block *nfb,
+ unsigned long action, void *hcpu)
+{
+ uint32_t cpu = (uintptr_t)hcpu;
+ unsigned int i;
+ struct cluster *i_cl = NULL;
+
+ hotplug_notify(action);
+
+ if (!clusters_inited)
+ return NOTIFY_OK;
+
+ for (i = 0; i < num_clusters; i++) {
+ if (managed_clusters[i]->cpus == NULL)
+ return NOTIFY_OK;
+ if (cpumask_test_cpu(cpu, managed_clusters[i]->cpus)) {
+ i_cl = managed_clusters[i];
+ break;
+ }
+ }
+
+ if (i_cl == NULL)
+ return NOTIFY_OK;
+
+ if (action == CPU_UP_PREPARE || action == CPU_UP_PREPARE_FROZEN) {
+ /*
+ * Prevent onlining of a managed CPU if max_cpu criteria is
+ * already satisfied
+ */
+ if (i_cl->offlined_cpus == NULL)
+ return NOTIFY_OK;
+ if (i_cl->max_cpu_request <=
+ num_online_managed(i_cl->cpus)) {
+ pr_debug("msm_perf: Prevent CPU%d onlining\n", cpu);
+ cpumask_set_cpu(cpu, i_cl->offlined_cpus);
+ return NOTIFY_BAD;
+ }
+ cpumask_clear_cpu(cpu, i_cl->offlined_cpus);
+
+ } else if (action == CPU_DEAD) {
+ if (i_cl->offlined_cpus == NULL)
+ return NOTIFY_OK;
+ if (cpumask_test_cpu(cpu, i_cl->offlined_cpus))
+ return NOTIFY_OK;
+ /*
+ * Schedule a re-evaluation to check if any more CPUs can be
+ * brought online to meet the max_cpu_request requirement. This
+ * work is delayed to account for CPU hotplug latencies
+ */
+ if (schedule_delayed_work(&evaluate_hotplug_work, 0)) {
+ trace_reevaluate_hotplug(cpumask_bits(i_cl->cpus)[0],
+ i_cl->max_cpu_request);
+ pr_debug("msm_perf: Re-evaluation scheduled %d\n", cpu);
+ } else {
+ pr_debug("msm_perf: Work scheduling failed %d\n", cpu);
+ }
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block __refdata msm_performance_cpu_notifier = {
+ .notifier_call = msm_performance_cpu_callback,
+};
+
+static int init_cluster_control(void)
+{
+ unsigned int i;
+ int ret = 0;
+
+ struct kobject *module_kobj;
+
+ managed_clusters = kcalloc(num_clusters, sizeof(struct cluster *),
+ GFP_KERNEL);
+ if (!managed_clusters)
+ return -ENOMEM;
+ for (i = 0; i < num_clusters; i++) {
+ managed_clusters[i] = kcalloc(1, sizeof(struct cluster),
+ GFP_KERNEL);
+ if (!managed_clusters[i]) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ if (!alloc_cpumask_var(&managed_clusters[i]->cpus,
+ GFP_KERNEL)) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ if (!alloc_cpumask_var(&managed_clusters[i]->offlined_cpus,
+ GFP_KERNEL)) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ managed_clusters[i]->max_cpu_request = -1;
+ managed_clusters[i]->single_enter_load = DEF_SINGLE_ENT;
+ managed_clusters[i]->single_exit_load = DEF_SINGLE_EX;
+ managed_clusters[i]->single_enter_cycles
+ = DEF_SINGLE_ENTER_CYCLE;
+ managed_clusters[i]->single_exit_cycles
+ = DEF_SINGLE_EXIT_CYCLE;
+ managed_clusters[i]->pcpu_multi_enter_load
+ = DEF_PCPU_MULTI_ENT;
+ managed_clusters[i]->pcpu_multi_exit_load = DEF_PCPU_MULTI_EX;
+ managed_clusters[i]->multi_enter_cycles = DEF_MULTI_ENTER_CYCLE;
+ managed_clusters[i]->multi_exit_cycles = DEF_MULTI_EXIT_CYCLE;
+ managed_clusters[i]->perf_cl_peak_enter_load =
+ DEF_PERF_CL_PEAK_ENT;
+ managed_clusters[i]->perf_cl_peak_exit_load =
+ DEF_PERF_CL_PEAK_EX;
+ managed_clusters[i]->perf_cl_peak_enter_cycles =
+ DEF_PERF_CL_PEAK_ENTER_CYCLE;
+ managed_clusters[i]->perf_cl_peak_exit_cycles =
+ DEF_PERF_CL_PEAK_EXIT_CYCLE;
+
+ /* Initialize trigger threshold */
+ thr.perf_cl_trigger_threshold = CLUSTER_1_THRESHOLD_FREQ;
+ thr.pwr_cl_trigger_threshold = CLUSTER_0_THRESHOLD_FREQ;
+ thr.ip_evt_threshold = INPUT_EVENT_CNT_THRESHOLD;
+ spin_lock_init(&(managed_clusters[i]->iowait_lock));
+ spin_lock_init(&(managed_clusters[i]->mode_lock));
+ spin_lock_init(&(managed_clusters[i]->timer_lock));
+ spin_lock_init(&(managed_clusters[i]->perf_cl_peak_lock));
+ init_timer(&managed_clusters[i]->mode_exit_timer);
+ managed_clusters[i]->mode_exit_timer.function =
+ single_mod_exit_timer;
+ init_timer(&managed_clusters[i]->perf_cl_peak_mode_exit_timer);
+ managed_clusters[i]->perf_cl_peak_mode_exit_timer.function =
+ perf_cl_peak_mod_exit_timer;
+ }
+
+ INIT_DELAYED_WORK(&evaluate_hotplug_work, check_cluster_status);
+ mutex_init(&managed_cpus_lock);
+
+ ip_evts = kcalloc(1, sizeof(struct input_events), GFP_KERNEL);
+ if (!ip_evts) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
+ if (!module_kobj) {
+ pr_err("msm_perf: Couldn't find module kobject\n");
+ ret = -ENOENT;
+ goto error;
+ }
+ mode_kobj = kobject_create_and_add("workload_modes", module_kobj);
+ if (!mode_kobj) {
+ pr_err("msm_perf: Failed to add mode_kobj\n");
+ ret = -ENOMEM;
+ kobject_put(module_kobj);
+ goto error;
+ }
+ ret = sysfs_create_group(mode_kobj, &attr_group);
+ if (ret) {
+ pr_err("msm_perf: Failed to create sysfs\n");
+ kobject_put(module_kobj);
+ kobject_put(mode_kobj);
+ goto error;
+ }
+ notify_thread = kthread_run(notify_userspace, NULL, "wrkld_notify");
+
+ clusters_inited = true;
+
+ return 0;
+
+error:
+ for (i = 0; i < num_clusters; i++) {
+ if (!managed_clusters[i])
+ break;
+ if (managed_clusters[i]->offlined_cpus)
+ free_cpumask_var(managed_clusters[i]->offlined_cpus);
+ if (managed_clusters[i]->cpus)
+ free_cpumask_var(managed_clusters[i]->cpus);
+ kfree(managed_clusters[i]);
+ }
+ kfree(managed_clusters);
+ return ret;
+}
+
+static int init_events_group(void)
+{
+ int ret;
+ struct kobject *module_kobj;
+
+ module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
+ if (!module_kobj) {
+ pr_err("msm_perf: Couldn't find module kobject\n");
+ return -ENOENT;
+ }
+
+ events_kobj = kobject_create_and_add("events", module_kobj);
+ if (!events_kobj) {
+ pr_err("msm_perf: Failed to add events_kobj\n");
+ return -ENOMEM;
+ }
+
+ ret = sysfs_create_group(events_kobj, &events_attr_group);
+ if (ret) {
+ pr_err("msm_perf: Failed to create sysfs\n");
+ return ret;
+ }
+
+ spin_lock_init(&(events_group.cpu_hotplug_lock));
+ events_notify_thread = kthread_run(events_notify_userspace,
+ NULL, "msm_perf:events_notify");
+ if (IS_ERR(events_notify_thread))
+ return PTR_ERR(events_notify_thread);
+
+ events_group.init_success = true;
+
+ return 0;
+}
+
+static int __init msm_performance_init(void)
+{
+ unsigned int cpu;
+
+ cpufreq_register_notifier(&perf_cpufreq_nb, CPUFREQ_POLICY_NOTIFIER);
+ cpufreq_register_notifier(&perf_govinfo_nb, CPUFREQ_GOVINFO_NOTIFIER);
+ cpufreq_register_notifier(&perf_cputransitions_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+
+ for_each_present_cpu(cpu)
+ per_cpu(cpu_stats, cpu).max = UINT_MAX;
+
+ register_cpu_notifier(&msm_performance_cpu_notifier);
+
+ init_events_group();
+
+ return 0;
+}
+late_initcall(msm_performance_init);
diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c
index 79627d0..5ca0fe5 100644
--- a/drivers/soc/qcom/rpmh.c
+++ b/drivers/soc/qcom/rpmh.c
@@ -480,7 +480,7 @@
while (n[count++])
;
count--;
- if (!count || count >= RPMH_MAX_REQ_IN_BATCH)
+ if (!count || count > RPMH_MAX_REQ_IN_BATCH)
return -EINVAL;
if (state == RPMH_ACTIVE_ONLY_STATE || state == RPMH_AWAKE_STATE) {
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index db12900..8cc77c1 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/qcom-geni-se.h>
#include <linux/spi/spi.h>
@@ -78,6 +79,8 @@
#define TIMESTAMP_AFTER (3)
#define POST_CMD_DELAY (4)
+#define SPI_CORE2X_VOTE (10000)
+
struct spi_geni_master {
struct se_geni_rsc spi_rsc;
resource_size_t phys_addr;
@@ -96,6 +99,7 @@
unsigned int rx_rem_bytes;
struct spi_transfer *cur_xfer;
struct completion xfer_done;
+ struct device *wrapper_dev;
};
static struct spi_master *get_spi_master(struct device *dev)
@@ -243,8 +247,8 @@
dev_err(mas->dev, "Invalid proto %d\n", proto);
return -ENXIO;
}
- geni_se_init(mas->base, FIFO_MODE, 0x0,
- (mas->tx_fifo_depth - 2));
+ geni_se_init(mas->base, 0x0, (mas->tx_fifo_depth - 2));
+ geni_se_select_mode(mas->base, FIFO_MODE);
mas->tx_fifo_depth = get_tx_fifo_depth(mas->base);
mas->rx_fifo_depth = get_rx_fifo_depth(mas->base);
mas->tx_fifo_width = get_tx_fifo_width(mas->base);
@@ -476,6 +480,8 @@
struct spi_geni_master *geni_mas;
struct se_geni_rsc *rsc;
struct resource *res;
+ struct platform_device *wrapper_pdev;
+ struct device_node *wrapper_ph_node;
spi = spi_alloc_master(&pdev->dev, sizeof(struct spi_geni_master));
if (!spi) {
@@ -489,6 +495,29 @@
rsc = &geni_mas->spi_rsc;
geni_mas->dev = &pdev->dev;
spi->dev.of_node = pdev->dev.of_node;
+ wrapper_ph_node = of_parse_phandle(pdev->dev.of_node,
+ "qcom,wrapper-core", 0);
+ if (IS_ERR_OR_NULL(wrapper_ph_node)) {
+ ret = PTR_ERR(wrapper_ph_node);
+ dev_err(&pdev->dev, "No wrapper core defined\n");
+ goto spi_geni_probe_err;
+ }
+ wrapper_pdev = of_find_device_by_node(wrapper_ph_node);
+ of_node_put(wrapper_ph_node);
+ if (IS_ERR_OR_NULL(wrapper_pdev)) {
+ ret = PTR_ERR(wrapper_pdev);
+ dev_err(&pdev->dev, "Cannot retrieve wrapper device\n");
+ goto spi_geni_probe_err;
+ }
+ geni_mas->wrapper_dev = &wrapper_pdev->dev;
+ geni_mas->spi_rsc.wrapper_dev = &wrapper_pdev->dev;
+ ret = geni_se_resources_init(rsc, SPI_CORE2X_VOTE,
+ (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH));
+ if (ret) {
+ dev_err(&pdev->dev, "Error geni_se_resources_init\n");
+ goto spi_geni_probe_err;
+ }
+
rsc->geni_pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR_OR_NULL(rsc->geni_pinctrl)) {
dev_err(&pdev->dev, "No pinctrl config specified!\n");
diff --git a/drivers/thermal/tsens-dbg.c b/drivers/thermal/tsens-dbg.c
index 7cd8c86..9b10a1b 100644
--- a/drivers/thermal/tsens-dbg.c
+++ b/drivers/thermal/tsens-dbg.c
@@ -35,8 +35,8 @@
#define TSENS_DEBUG_ID_MASK_1_4 0xffffffe1
#define DEBUG_SIZE 10
-#define TSENS_DEBUG_CONTROL(n) ((n) + 0x1130)
-#define TSENS_DEBUG_DATA(n) ((n) + 0x1134)
+#define TSENS_DEBUG_CONTROL(n) ((n) + 0x130)
+#define TSENS_DEBUG_DATA(n) ((n) + 0x134)
struct tsens_dbg_func {
int (*dbg_func)(struct tsens_device *, u32, u32, int *);
@@ -86,10 +86,127 @@
return 0;
}
+static int tsens_dbg_log_bus_id_data(struct tsens_device *data,
+ u32 id, u32 dbg_type, int *val)
+{
+ struct tsens_device *tmdev = NULL;
+ u32 loop = 0, i = 0;
+ uint32_t r1, r2, r3, r4, offset = 0;
+ unsigned int debug_dump;
+ unsigned int debug_id = 0, cntrl_id = 0;
+ void __iomem *srot_addr;
+ void __iomem *controller_id_addr;
+ void __iomem *debug_id_addr;
+ void __iomem *debug_data_addr;
+
+ if (!data)
+ return -EINVAL;
+
+ pr_debug("%d %d\n", id, dbg_type);
+ tmdev = data;
+ controller_id_addr = TSENS_CONTROLLER_ID(tmdev->tsens_tm_addr);
+ debug_id_addr = TSENS_DEBUG_CONTROL(tmdev->tsens_tm_addr);
+ debug_data_addr = TSENS_DEBUG_DATA(tmdev->tsens_tm_addr);
+ srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr);
+
+ cntrl_id = readl_relaxed(controller_id_addr);
+ pr_err("Controller_id: 0x%x\n", cntrl_id);
+
+ loop = 0;
+ i = 0;
+ debug_id = readl_relaxed(debug_id_addr);
+ writel_relaxed((debug_id | (i << 1) | 1),
+ TSENS_DEBUG_CONTROL(tmdev->tsens_tm_addr));
+ while (loop < TSENS_DEBUG_LOOP_COUNT_ID_0) {
+ debug_dump = readl_relaxed(debug_data_addr);
+ r1 = readl_relaxed(debug_data_addr);
+ r2 = readl_relaxed(debug_data_addr);
+ r3 = readl_relaxed(debug_data_addr);
+ r4 = readl_relaxed(debug_data_addr);
+ pr_err("cntrl:%d, bus-id:%d value:0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
+ cntrl_id, i, debug_dump, r1, r2, r3, r4);
+ loop++;
+ }
+
+ for (i = TSENS_DBG_BUS_ID_1; i <= TSENS_DBG_BUS_ID_15; i++) {
+ loop = 0;
+ debug_id = readl_relaxed(debug_id_addr);
+ debug_id = debug_id & TSENS_DEBUG_ID_MASK_1_4;
+ writel_relaxed((debug_id | (i << 1) | 1),
+ TSENS_DEBUG_CONTROL(tmdev->tsens_tm_addr));
+ while (loop < TSENS_DEBUG_LOOP_COUNT) {
+ debug_dump = readl_relaxed(debug_data_addr);
+ pr_err("cntrl:%d, bus-id:%d with value: 0x%x\n",
+ cntrl_id, i, debug_dump);
+ if (i == TSENS_DBG_BUS_ID_2)
+ usleep_range(
+ TSENS_DEBUG_BUS_ID2_MIN_CYCLE,
+ TSENS_DEBUG_BUS_ID2_MAX_CYCLE);
+ loop++;
+ }
+ }
+
+ pr_err("Start of TSENS TM dump\n");
+ for (i = 0; i < TSENS_DEBUG_OFFSET_RANGE; i++) {
+ r1 = readl_relaxed(controller_id_addr + offset);
+ r2 = readl_relaxed(controller_id_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD1));
+ r3 = readl_relaxed(controller_id_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD2));
+ r4 = readl_relaxed(controller_id_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD3));
+
+ pr_err("ctrl:%d:0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ cntrl_id, offset, r1, r2, r3, r4);
+ offset += TSENS_DEBUG_OFFSET_ROW;
+ }
+
+ offset = 0;
+ pr_err("Start of TSENS SROT dump\n");
+ for (i = 0; i < TSENS_DEBUG_OFFSET_RANGE; i++) {
+ r1 = readl_relaxed(srot_addr + offset);
+ r2 = readl_relaxed(srot_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD1));
+ r3 = readl_relaxed(srot_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD2));
+ r4 = readl_relaxed(srot_addr + (offset +
+ TSENS_DEBUG_OFFSET_WORD3));
+
+ pr_err("ctrl:%d:0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ cntrl_id, offset, r1, r2, r3, r4);
+ offset += TSENS_DEBUG_OFFSET_ROW;
+ }
+
+ loop = 0;
+ while (loop < TSENS_DEBUG_LOOP_COUNT) {
+ offset = TSENS_DEBUG_OFFSET_ROW *
+ TSENS_DEBUG_STATUS_REG_START;
+ pr_err("Start of TSENS TM dump %d\n", loop);
+ /* Limited dump of the registers for the temperature */
+ for (i = 0; i < TSENS_DEBUG_LOOP_COUNT; i++) {
+ r1 = readl_relaxed(controller_id_addr + offset);
+ r2 = readl_relaxed(controller_id_addr +
+ (offset + TSENS_DEBUG_OFFSET_WORD1));
+ r3 = readl_relaxed(controller_id_addr +
+ (offset + TSENS_DEBUG_OFFSET_WORD2));
+ r4 = readl_relaxed(controller_id_addr +
+ (offset + TSENS_DEBUG_OFFSET_WORD3));
+
+ pr_err("ctrl:%d:0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ cntrl_id, offset, r1, r2, r3, r4);
+ offset += TSENS_DEBUG_OFFSET_ROW;
+ }
+ loop++;
+ }
+
+ return 0;
+}
+
static struct tsens_dbg_func dbg_arr[] = {
[TSENS_DBG_LOG_TEMP_READS] = {tsens_dbg_log_temp_reads},
[TSENS_DBG_LOG_INTERRUPT_TIMESTAMP] = {
tsens_dbg_log_interrupt_timestamp},
+ [TSENS_DBG_LOG_BUS_ID_DATA] = {tsens_dbg_log_bus_id_data},
};
int tsens2xxx_dbg(struct tsens_device *data, u32 id, u32 dbg_type, int *val)
diff --git a/drivers/thermal/tsens.h b/drivers/thermal/tsens.h
index 3b9b01a..770b982 100644
--- a/drivers/thermal/tsens.h
+++ b/drivers/thermal/tsens.h
@@ -31,6 +31,7 @@
TSENS_DBG_POLL,
TSENS_DBG_LOG_TEMP_READS,
TSENS_DBG_LOG_INTERRUPT_TIMESTAMP,
+ TSENS_DBG_LOG_BUS_ID_DATA,
TSENS_DBG_LOG_MAX
};
@@ -109,9 +110,9 @@
unsigned int *hw_ids;
u32 temp_factor;
bool cycle_monitor;
- u32 cycle_compltn_monitor_val;
+ u32 cycle_compltn_monitor_mask;
bool wd_bark;
- u32 wd_bark_val;
+ u32 wd_bark_mask;
};
struct tsens_device {
diff --git a/drivers/thermal/tsens2xxx.c b/drivers/thermal/tsens2xxx.c
index 13b183d..55be2f9 100644
--- a/drivers/thermal/tsens2xxx.c
+++ b/drivers/thermal/tsens2xxx.c
@@ -57,6 +57,8 @@
#define TSENS_TM_CODE_BIT_MASK 0xfff
#define TSENS_TM_CODE_SIGN_BIT 0x800
#define TSENS_TM_SCALE_DECI_MILLIDEG 100
+#define TSENS_DEBUG_WDOG_TRIGGER_COUNT 5
+#define TSENS_TM_WATCHDOG_LOG(n) ((n) + 0x13c)
#define TSENS_EN BIT(0)
@@ -296,13 +298,11 @@
static irqreturn_t tsens_tm_critical_irq_thread(int irq, void *data)
{
struct tsens_device *tm = data;
- unsigned int i, status;
+ unsigned int i, status, wd_log, wd_mask;
unsigned long flags;
- void __iomem *sensor_status_addr;
- void __iomem *sensor_int_mask_addr;
+ void __iomem *sensor_status_addr, *sensor_int_mask_addr;
void __iomem *sensor_critical_addr;
- void __iomem *wd_critical_addr;
- int wd_mask;
+ void __iomem *wd_critical_addr, *wd_log_addr;
sensor_status_addr = TSENS_TM_SN_STATUS(tm->tsens_tm_addr);
sensor_int_mask_addr =
@@ -311,6 +311,7 @@
TSENS_TM_SN_CRITICAL_THRESHOLD(tm->tsens_tm_addr);
wd_critical_addr =
TSENS_TM_CRITICAL_INT_STATUS(tm->tsens_tm_addr);
+ wd_log_addr = TSENS_TM_WATCHDOG_LOG(tm->tsens_tm_addr);
if (tm->ctrl_data->wd_bark) {
wd_mask = readl_relaxed(wd_critical_addr);
@@ -325,7 +326,15 @@
writel_relaxed(wd_mask & ~(TSENS_TM_CRITICAL_WD_BARK),
(TSENS_TM_CRITICAL_INT_CLEAR
(tm->tsens_tm_addr)));
- tm->tsens_dbg.tsens_critical_wd_cnt++;
+ wd_log = readl_relaxed(wd_log_addr);
+ if (wd_log >= TSENS_DEBUG_WDOG_TRIGGER_COUNT) {
+ pr_err("Watchdog count:%d\n", wd_log);
+ if (tm->ops->dbg)
+ tm->ops->dbg(tm, 0,
+ TSENS_DBG_LOG_BUS_ID_DATA, NULL);
+ BUG();
+ }
+
return IRQ_HANDLED;
}
}
@@ -494,8 +503,7 @@
{
void __iomem *srot_addr;
void __iomem *sensor_int_mask_addr;
- unsigned int srot_val;
- int crit_mask;
+ unsigned int srot_val, crit_mask, crit_val;
srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr + 0x4);
srot_val = readl_relaxed(srot_addr);
@@ -508,13 +516,36 @@
sensor_int_mask_addr =
TSENS_TM_CRITICAL_INT_MASK(tmdev->tsens_tm_addr);
crit_mask = readl_relaxed(sensor_int_mask_addr);
- writel_relaxed(
- crit_mask | tmdev->ctrl_data->cycle_compltn_monitor_val,
- (TSENS_TM_CRITICAL_INT_MASK
- (tmdev->tsens_tm_addr)));
+ crit_val = TSENS_TM_CRITICAL_CYCLE_MONITOR;
+ if (tmdev->ctrl_data->cycle_compltn_monitor_mask)
+ writel_relaxed((crit_mask | crit_val),
+ (TSENS_TM_CRITICAL_INT_MASK
+ (tmdev->tsens_tm_addr)));
+ else
+ writel_relaxed((crit_mask & ~crit_val),
+ (TSENS_TM_CRITICAL_INT_MASK
+ (tmdev->tsens_tm_addr)));
/*Update critical cycle monitoring*/
mb();
}
+
+ if (tmdev->ctrl_data->wd_bark) {
+ sensor_int_mask_addr =
+ TSENS_TM_CRITICAL_INT_MASK(tmdev->tsens_tm_addr);
+ crit_mask = readl_relaxed(sensor_int_mask_addr);
+ crit_val = TSENS_TM_CRITICAL_WD_BARK;
+ if (tmdev->ctrl_data->wd_bark_mask)
+ writel_relaxed((crit_mask | crit_val),
+ (TSENS_TM_CRITICAL_INT_MASK
+ (tmdev->tsens_tm_addr)));
+ else
+ writel_relaxed((crit_mask & ~crit_val),
+ (TSENS_TM_CRITICAL_INT_MASK
+ (tmdev->tsens_tm_addr)));
+ /*Update watchdog monitoring*/
+ mb();
+ }
+
writel_relaxed(TSENS_TM_CRITICAL_INT_EN |
TSENS_TM_UPPER_INT_EN | TSENS_TM_LOWER_INT_EN,
TSENS_TM_INT_EN(tmdev->tsens_tm_addr));
@@ -575,24 +606,25 @@
const struct tsens_data data_tsens2xxx = {
.cycle_monitor = false,
- .cycle_compltn_monitor_val = 0,
+ .cycle_compltn_monitor_mask = 1,
.wd_bark = false,
- .wd_bark_val = 0,
+ .wd_bark_mask = 1,
.ops = &ops_tsens2xxx,
};
const struct tsens_data data_tsens23xx = {
.cycle_monitor = true,
- .cycle_compltn_monitor_val = 0,
+ .cycle_compltn_monitor_mask = 1,
.wd_bark = true,
- .wd_bark_val = 0,
+ .wd_bark_mask = 1,
.ops = &ops_tsens2xxx,
};
const struct tsens_data data_tsens24xx = {
.cycle_monitor = true,
- .cycle_compltn_monitor_val = 0,
+ .cycle_compltn_monitor_mask = 1,
.wd_bark = true,
- .wd_bark_val = 1,
+ /* Enable Watchdog monitoring by unmasking */
+ .wd_bark_mask = 0,
.ops = &ops_tsens2xxx,
};
diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c
index 2ffd0df..8108da8 100644
--- a/drivers/tty/serial/msm_geni_serial.c
+++ b/drivers/tty/serial/msm_geni_serial.c
@@ -28,8 +28,6 @@
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
-#include <linux/msm-bus.h>
-#include <linux/msm-bus-board.h>
/* UART specific GENI registers */
#define SE_UART_LOOPBACK_CFG (0x22C)
@@ -107,8 +105,6 @@
#define DEF_TX_WM (2)
#define DEF_FIFO_WIDTH_BITS (32)
#define UART_CORE2X_VOTE (10000)
-#define DEFAULT_SE_CLK (19200000)
-#define DEFAULT_BUS_WIDTH (4)
#define WAKEBYTE_TIMEOUT_MSEC (2000)
#define IPC_LOG_PWR_PAGES (2)
@@ -138,6 +134,7 @@
unsigned int rx_fifo_wc,
unsigned int rx_last_byte_valid,
unsigned int rx_last);
+ struct device *wrapper_dev;
struct se_geni_rsc serial_rsc;
int loopback;
int wakeup_irq;
@@ -1035,18 +1032,24 @@
if (!uart_console(uport)) {
/* For now only assume FIFO mode. */
msm_port->xfer_mode = FIFO_MODE;
- ret = geni_se_init(uport->membase, msm_port->xfer_mode,
+ ret = geni_se_init(uport->membase,
msm_port->rx_wm, msm_port->rx_rfr);
if (ret) {
dev_err(uport->dev, "%s: Fail\n", __func__);
goto exit_portsetup;
}
+
+ ret = geni_se_select_mode(uport->membase, msm_port->xfer_mode);
+ if (ret)
+ goto exit_portsetup;
+
se_get_packing_config(8, 4, false, &cfg0, &cfg1);
geni_write_reg_nolog(cfg0, uport->membase,
SE_GENI_TX_PACKING_CFG0);
geni_write_reg_nolog(cfg1, uport->membase,
SE_GENI_TX_PACKING_CFG1);
}
+
msm_port->port_setup = true;
/*
* Ensure Port setup related IO completes before returning to
@@ -1435,8 +1438,9 @@
goto exit_geni_serial_earlyconsetup;
}
- geni_se_init(uport->membase, FIFO_MODE, (DEF_FIFO_DEPTH_WORDS >> 1),
- (DEF_FIFO_DEPTH_WORDS - 2));
+ geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),
+ (DEF_FIFO_DEPTH_WORDS - 2));
+ geni_se_select_mode(uport->membase, FIFO_MODE);
/*
* Ignore Flow control.
* Disable Tx Parity.
@@ -1599,6 +1603,8 @@
struct uart_driver *drv;
const struct of_device_id *id;
bool is_console = false;
+ struct platform_device *wrapper_pdev;
+ struct device_node *wrapper_ph_node;
id = of_match_device(msm_geni_device_tbl, &pdev->dev);
if (id) {
@@ -1642,23 +1648,24 @@
uport->dev = &pdev->dev;
- if (!(of_property_read_u32(pdev->dev.of_node, "qcom,bus-mas",
- &dev_port->serial_rsc.bus_mas))) {
- dev_port->serial_rsc.bus_bw =
- msm_bus_scale_register(
- dev_port->serial_rsc.bus_mas,
- MSM_BUS_SLAVE_EBI_CH0,
- (char *)dev_name(&pdev->dev),
- false);
- if (IS_ERR_OR_NULL(dev_port->serial_rsc.bus_bw)) {
- ret = PTR_ERR(dev_port->serial_rsc.bus_bw);
- goto exit_geni_serial_probe;
- }
- dev_port->serial_rsc.ab = UART_CORE2X_VOTE;
- dev_port->serial_rsc.ib = DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH;
- } else {
- dev_info(&pdev->dev, "No bus master specified\n");
+ wrapper_ph_node = of_parse_phandle(pdev->dev.of_node,
+ "qcom,wrapper-core", 0);
+ if (IS_ERR_OR_NULL(wrapper_ph_node)) {
+ ret = PTR_ERR(wrapper_ph_node);
+ goto exit_geni_serial_probe;
}
+ wrapper_pdev = of_find_device_by_node(wrapper_ph_node);
+ of_node_put(wrapper_ph_node);
+ if (IS_ERR_OR_NULL(wrapper_pdev)) {
+ ret = PTR_ERR(wrapper_pdev);
+ goto exit_geni_serial_probe;
+ }
+ dev_port->wrapper_dev = &wrapper_pdev->dev;
+ dev_port->serial_rsc.wrapper_dev = &wrapper_pdev->dev;
+ ret = geni_se_resources_init(&dev_port->serial_rsc, UART_CORE2X_VOTE,
+ (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH));
+ if (ret)
+ goto exit_geni_serial_probe;
if (of_property_read_u8(pdev->dev.of_node, "qcom,wakeup-byte",
&dev_port->wakeup_byte))
@@ -1777,7 +1784,6 @@
wakeup_source_trash(&port->geni_wake);
uart_remove_one_port(drv, &port->uport);
- msm_bus_scale_unregister(port->serial_rsc.bus_bw);
return 0;
}
@@ -1830,6 +1836,7 @@
if (uart_console(uport)) {
uart_suspend_port((struct uart_driver *)uport->private_data,
uport);
+ se_geni_resources_off(&port->serial_rsc);
} else {
if (!pm_runtime_status_suspended(dev)) {
dev_info(dev, "%s: Is still active\n", __func__);
diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h
index 32c5890..7f7e9a7 100644
--- a/include/linux/dma-iommu.h
+++ b/include/linux/dma-iommu.h
@@ -61,6 +61,10 @@
enum dma_data_direction dir, unsigned long attrs);
void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction dir, unsigned long attrs);
+dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
+ size_t size, enum dma_data_direction dir, unsigned long attrs);
+void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir, unsigned long attrs);
int iommu_dma_supported(struct device *dev, u64 mask);
int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index 12b3d51e8..657ac07 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -14,18 +14,22 @@
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
-#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/dma-direction.h>
+#include <linux/io.h>
+#include <linux/list.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
-#include <linux/pm_runtime.h>
+/* Transfer mode supported by GENI Serial Engines */
enum se_xfer_mode {
INVALID,
FIFO_MODE,
GSI_DMA,
+ SE_DMA,
};
+/* Protocols supported by GENI Serial Engines */
enum se_protocol_types {
NONE,
SPI,
@@ -34,13 +38,28 @@
I3C
};
+/**
+ * struct geni_se_rsc - GENI Serial Engine Resource
+ * @wrapper_dev: Pointer to the parent QUPv3 core.
+ * @se_clk: Handle to the core serial engine clock.
+ * @m_ahb_clk: Handle to the primary AHB clock.
+ * @s_ahb_clk: Handle to the secondary AHB clock.
+ * @ab_list: List Head of Average bus banwidth list.
+ * @ab: Average bus bandwidth request value.
+ * @ib_list: List Head of Instantaneous bus banwidth list.
+ * @ib: Instantaneous bus bandwidth request value.
+ * @geni_pinctrl: Handle to the pinctrl configuration.
+ * @geni_gpio_active: Handle to the default/active pinctrl state.
+ * @geni_gpi_sleep: Handle to the sleep pinctrl state.
+ */
struct se_geni_rsc {
+ struct device *wrapper_dev;
struct clk *se_clk;
struct clk *m_ahb_clk;
struct clk *s_ahb_clk;
- struct msm_bus_client_handle *bus_bw;
- unsigned int bus_mas;
+ struct list_head ab_list;
unsigned long ab;
+ struct list_head ib_list;
unsigned long ib;
struct pinctrl *geni_pinctrl;
struct pinctrl_state *geni_gpio_active;
@@ -64,6 +83,7 @@
#define GENI_FW_REVISION_RO (0x68)
#define GENI_FW_S_REVISION_RO (0x6C)
#define SE_GENI_CLK_SEL (0x7C)
+#define SE_GENI_BYTE_GRAN (0x254)
#define SE_GENI_DMA_MODE_EN (0x258)
#define SE_GENI_TX_PACKING_CFG0 (0x260)
#define SE_GENI_TX_PACKING_CFG1 (0x264)
@@ -182,11 +202,11 @@
#define M_TX_FIFO_WR_ERR_EN (BIT(29))
#define M_TX_FIFO_WATERMARK_EN (BIT(30))
#define M_SEC_IRQ_EN (BIT(31))
-#define M_COMMON_GENI_M_IRQ_EN (GENMASK(3, 0) | M_TIMESTAMP_EN | \
- GENMASK(14, 8) | M_IO_DATA_DEASSERT_EN | \
+#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
+ M_IO_DATA_DEASSERT_EN | \
M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
- M_TX_FIFO_WR_ERR_EN | M_SEC_IRQ_EN)
+ M_TX_FIFO_WR_ERR_EN)
/* GENI_S_IRQ_EN fields */
#define S_CMD_DONE_EN (BIT(0))
@@ -208,7 +228,7 @@
#define S_RX_FIFO_WR_ERR_EN (BIT(25))
#define S_RX_FIFO_WATERMARK_EN (BIT(26))
#define S_RX_FIFO_LAST_EN (BIT(27))
-#define S_COMMON_GENI_S_IRQ_EN (GENMASK(3, 0) | GENMASK(14, 8) | \
+#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
@@ -261,304 +281,557 @@
#define RX_DMA_IRQ_DELAY_MSK (GENMASK(8, 6))
#define RX_DMA_IRQ_DELAY_SHFT (6)
+#define SE_DMA_TX_PTR_L (0xC30)
+#define SE_DMA_TX_PTR_H (0xC34)
+#define SE_DMA_TX_ATTR (0xC38)
+#define SE_DMA_TX_LEN (0xC3C)
+#define SE_DMA_TX_IRQ_STAT (0xC40)
+#define SE_DMA_TX_IRQ_CLR (0xC44)
+#define SE_DMA_TX_IRQ_EN (0xC48)
+#define SE_DMA_TX_IRQ_EN_SET (0xC4C)
+#define SE_DMA_TX_IRQ_EN_CLR (0xC50)
+#define SE_DMA_TX_LEN_IN (0xC54)
+#define SE_DMA_TX_FSM_RST (0xC58)
+#define SE_DMA_TX_MAX_BURST (0xC5C)
+
+#define SE_DMA_RX_PTR_L (0xD30)
+#define SE_DMA_RX_PTR_H (0xD34)
+#define SE_DMA_RX_ATTR (0xD38)
+#define SE_DMA_RX_LEN (0xD3C)
+#define SE_DMA_RX_IRQ_STAT (0xD40)
+#define SE_DMA_RX_IRQ_CLR (0xD44)
+#define SE_DMA_RX_IRQ_EN (0xD48)
+#define SE_DMA_RX_IRQ_EN_SET (0xD4C)
+#define SE_DMA_RX_IRQ_EN_CLR (0xD50)
+#define SE_DMA_RX_LEN_IN (0xD54)
+#define SE_DMA_RX_FSM_RST (0xD58)
+#define SE_DMA_RX_MAX_BURST (0xD5C)
+#define SE_DMA_RX_FLUSH (0xD60)
+
+#define DEFAULT_BUS_WIDTH (4)
+#define DEFAULT_SE_CLK (19200000)
+
+#define GENI_SE_ERR(log_ctx, print, dev, x...) do { \
+if (log_ctx) \
+ ipc_log_string(log_ctx, x); \
+if (print) { \
+ if (dev) \
+ dev_err((dev), x); \
+ else \
+ pr_err(x); \
+} \
+} while (0)
+
+#define GENI_SE_DBG(log_ctx, print, dev, x...) do { \
+if (log_ctx) \
+ ipc_log_string(log_ctx, x); \
+if (print) { \
+ if (dev) \
+ dev_dbg((dev), x); \
+ else \
+ pr_debug(x); \
+} \
+} while (0)
+
+
+#ifdef CONFIG_QCOM_GENI_SE
+/**
+ * geni_read_reg_nolog() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg_nolog(void __iomem *base, int offset);
+
+/**
+ * geni_write_reg_nolog() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ */
+void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset);
+
+/**
+ * geni_read_reg() - Helper function to read from a GENI register
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ *
+ * Return: Return the contents of the register.
+ */
+unsigned int geni_read_reg(void __iomem *base, int offset);
+
+/**
+ * geni_write_reg() - Helper function to write into a GENI register
+ * @value: Value to be written into the register.
+ * @base: Base address of the serial engine's register block.
+ * @offset: Offset within the serial engine's register block.
+ */
+void geni_write_reg(unsigned int value, void __iomem *base, int offset);
+
+/**
+ * get_se_proto() - Read the protocol configured for a serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * Return: Protocol value as configured in the serial engine.
+ */
+int get_se_proto(void __iomem *base);
+
+/**
+ * geni_se_init() - Initialize the GENI Serial Engine
+ * @base: Base address of the serial engine's register block.
+ * @rx_wm: Receive watermark to be configured.
+ * @rx_rfr_wm: Ready-for-receive watermark to be configured.
+ *
+ * This function is used to initialize the GENI serial engine, configure
+ * the transfer mode, receive watermark and ready-for-receive watermarks.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_init(void __iomem *base, unsigned int rx_wm, unsigned int rx_rfr);
+
+/**
+ * geni_se_select_mode() - Select the serial engine transfer mode
+ * @base: Base address of the serial engine's register block.
+ * @mode: Transfer mode to be selected.
+ *
+ * Return: 0 on success, standard Linux error codes on failure.
+ */
+int geni_se_select_mode(void __iomem *base, int mode);
+
+/**
+ * geni_setup_m_cmd() - Setup the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ * @cmd: Command/Operation to setup in the primary sequencer.
+ * @params: Parameter for the sequencer command.
+ *
+ * This function is used to configure the primary sequencer with the
+ * command and its assoicated parameters.
+ */
+void geni_setup_m_cmd(void __iomem *base, u32 cmd, u32 params);
+
+/**
+ * geni_setup_s_cmd() - Setup the secondary sequencer
+ * @base: Base address of the serial engine's register block.
+ * @cmd: Command/Operation to setup in the secondary sequencer.
+ * @params: Parameter for the sequencer command.
+ *
+ * This function is used to configure the secondary sequencer with the
+ * command and its assoicated parameters.
+ */
+void geni_setup_s_cmd(void __iomem *base, u32 cmd, u32 params);
+
+/**
+ * geni_cancel_m_cmd() - Cancel the command configured in the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to cancel the currently configured command in the
+ * primary sequencer.
+ */
+void geni_cancel_m_cmd(void __iomem *base);
+
+/**
+ * geni_cancel_s_cmd() - Cancel the command configured in the secondary
+ * sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to cancel the currently configured command in the
+ * secondary sequencer.
+ */
+void geni_cancel_s_cmd(void __iomem *base);
+
+/**
+ * geni_abort_m_cmd() - Abort the command configured in the primary sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to force abort the currently configured command in the
+ * primary sequencer.
+ */
+void geni_abort_m_cmd(void __iomem *base);
+
+/**
+ * geni_abort_s_cmd() - Abort the command configured in the secondary
+ * sequencer
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to force abort the currently configured command in the
+ * secondary sequencer.
+ */
+void geni_abort_s_cmd(void __iomem *base);
+
+/**
+ * get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the depth i.e. number of elements in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo depth in units of FIFO words.
+ */
+int get_tx_fifo_depth(void __iomem *base);
+
+/**
+ * get_tx_fifo_width() - Get the TX fifo width of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the width i.e. word size per element in the
+ * TX fifo of the serial engine.
+ *
+ * Return: TX fifo width in bits.
+ */
+int get_tx_fifo_width(void __iomem *base);
+
+/**
+ * get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
+ * @base: Base address of the serial engine's register block.
+ *
+ * This function is used to get the depth i.e. number of elements in the
+ * RX fifo of the serial engine.
+ *
+ * Return: RX fifo depth in units of FIFO words.
+ */
+int get_rx_fifo_depth(void __iomem *base);
+
+/**
+ * se_get_packing_config() - Get the packing configuration based on input
+ * @bpw: Bits of data per transfer word.
+ * @pack_words: Number of words per fifo element.
+ * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
+ * @cfg0: Output buffer to hold the first half of configuration.
+ * @cfg1: Output buffer to hold the second half of configuration.
+ *
+ * This function is used to calculate the packing configuration based on
+ * the input packing requirement and the configuration logic.
+ */
+void se_get_packing_config(int bpw, int pack_words, bool msb_to_lsb,
+ unsigned long *cfg0, unsigned long *cfg1);
+
+/**
+ * se_config_packing() - Packing configuration of the serial engine
+ * @base: Base address of the serial engine's register block.
+ * @bpw: Bits of data per transfer word.
+ * @pack_words: Number of words per fifo element.
+ * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
+ *
+ * This function is used to configure the packing rules for the current
+ * transfer.
+ */
+void se_config_packing(void __iomem *base, int bpw, int pack_words,
+ bool msb_to_lsb);
+
+/**
+ * se_geni_resources_off() - Turn off resources associated with the serial
+ * engine
+ * @rsc: Handle to resources associated with the serial engine.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int se_geni_resources_off(struct se_geni_rsc *rsc);
+
+/**
+ * se_geni_resources_on() - Turn on resources associated with the serial
+ * engine
+ * @rsc: Handle to resources associated with the serial engine.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int se_geni_resources_on(struct se_geni_rsc *rsc);
+
+/**
+ * geni_se_resources_init() - Init the SE resource structure
+ * @rsc: SE resource structure to be initialized.
+ * @ab: Initial Average bus bandwidth request value.
+ * @ib: Initial Instantaneous bus bandwidth request value.
+ *
+ * Return: 0 on success, standard Linux error codes on failure.
+ */
+int geni_se_resources_init(struct se_geni_rsc *rsc,
+ unsigned long ab, unsigned long ib);
+
+/**
+ * geni_se_tx_dma_prep() - Prepare the Serial Engine for TX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
+ * @base: Base address of the SE register block.
+ * @tx_buf: Pointer to the TX buffer.
+ * @tx_len: Length of the TX buffer.
+ * @tx_dma: Pointer to store the mapped DMA address.
+ *
+ * This function is used to prepare the buffers for DMA TX.
+ *
+ * Return: 0 on success, standard Linux error codes on error/failure.
+ */
+int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base,
+ void *tx_buf, int tx_len, dma_addr_t *tx_dma);
+
+/**
+ * geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
+ * @base: Base address of the SE register block.
+ * @rx_buf: Pointer to the RX buffer.
+ * @rx_len: Length of the RX buffer.
+ * @rx_dma: Pointer to store the mapped DMA address.
+ *
+ * This function is used to prepare the buffers for DMA RX.
+ *
+ * Return: 0 on success, standard Linux error codes on error/failure.
+ */
+int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base,
+ void *rx_buf, int rx_len, dma_addr_t *rx_dma);
+
+/**
+ * geni_se_tx_dma_unprep() - Unprepare the Serial Engine after TX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
+ * @tx_dma: DMA address of the TX buffer.
+ * @tx_len: Length of the TX buffer.
+ *
+ * This function is used to unprepare the DMA buffers after DMA TX.
+ */
+void geni_se_tx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t tx_dma, int tx_len);
+
+/**
+ * geni_se_rx_dma_unprep() - Unprepare the Serial Engine after RX DMA transfer
+ * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
+ * @rx_dma: DMA address of the RX buffer.
+ * @rx_len: Length of the RX buffer.
+ *
+ * This function is used to unprepare the DMA buffers after DMA RX.
+ */
+void geni_se_rx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t rx_dma, int rx_len);
+
+/**
+ * geni_se_qupv3_hw_version() - Read the QUPv3 Hardware version
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @major: Buffer for Major Version field.
+ * @minor: Buffer for Minor Version field.
+ * @step: Buffer for Step Version field.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_qupv3_hw_version(struct device *wrapper_dev, unsigned int *major,
+ unsigned int *minor, unsigned int *step);
+
+/**
+ * geni_se_iommu_map_buf() - Map a single buffer into QUPv3 context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @buf: Address of the buffer that needs to be mapped.
+ * @size: Size of the buffer.
+ * @dir: Direction of the DMA transfer.
+ *
+ * This function is used to map an already allocated buffer into the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ void *buf, size_t size, enum dma_data_direction dir);
+
+/**
+ * geni_se_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3
+ * context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @size: Size of the buffer.
+ *
+ * This function is used to allocate a buffer and map it into the
+ * QUPv3 context bank device space.
+ *
+ * Return: address of the buffer on success, NULL or ERR_PTR on
+ * failure/error.
+ */
+void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ size_t size);
+
+/**
+ * geni_se_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @size: Size of the buffer.
+ * @dir: Direction of the DMA transfer.
+ *
+ * This function is used to unmap an already mapped buffer from the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ size_t size, enum dma_data_direction dir);
+
+/**
+ * geni_se_iommu_free_buf() - Unmap & free a single buffer from QUPv3
+ * context bank
+ * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
+ * @iova: Pointer in which the mapped virtual address is stored.
+ * @buf: Address of the buffer.
+ * @size: Size of the buffer.
+ *
+ * This function is used to unmap and free a buffer from the
+ * QUPv3 context bank device space.
+ *
+ * Return: 0 on success, standard Linux error codes on failure/error.
+ */
+int geni_se_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova,
+ void *buf, size_t size);
+
+#else
static inline unsigned int geni_read_reg_nolog(void __iomem *base, int offset)
{
- return readl_relaxed_no_log(base + offset);
+ return 0;
}
-static inline void geni_write_reg_nolog(unsigned int value, void __iomem *base,
- int offset)
+static inline void geni_write_reg_nolog(unsigned int value,
+ void __iomem *base, int offset)
{
- return writel_relaxed_no_log(value, (base + offset));
}
static inline unsigned int geni_read_reg(void __iomem *base, int offset)
{
- return readl_relaxed(base + offset);
+ return 0;
}
static inline void geni_write_reg(unsigned int value, void __iomem *base,
int offset)
{
- writel_relaxed(value, (base + offset));
}
static inline int get_se_proto(void __iomem *base)
{
- int proto = 0;
-
- proto = ((geni_read_reg(base, GENI_FW_REVISION_RO)
- & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT);
- return proto;
+ return -ENXIO;
}
-static inline int se_geni_irq_en(void __iomem *base, int mode)
-{
- int ret = 0;
- unsigned int common_geni_m_irq_en;
- unsigned int common_geni_s_irq_en;
- int proto = get_se_proto(base);
-
- common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
- common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);
- /* Common to all modes */
- common_geni_m_irq_en |= M_COMMON_GENI_M_IRQ_EN;
- common_geni_s_irq_en |= S_COMMON_GENI_S_IRQ_EN;
-
- switch (mode) {
- case FIFO_MODE:
- {
- if (proto != UART) {
- common_geni_m_irq_en |=
- (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
- M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
- common_geni_s_irq_en |= S_CMD_DONE_EN;
- }
- break;
- }
- case GSI_DMA:
- break;
- default:
- pr_err("%s: Invalid mode %d\n", __func__, mode);
- ret = -ENXIO;
- goto exit_irq_en;
- }
-
-
- geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);
- geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN);
-exit_irq_en:
- return ret;
-}
-
-
-static inline void se_set_rx_rfr_wm(void __iomem *base, unsigned int rx_wm,
- unsigned int rx_rfr)
-{
- geni_write_reg(rx_wm, base, SE_GENI_RX_WATERMARK_REG);
- geni_write_reg(rx_rfr, base, SE_GENI_RX_RFR_WATERMARK_REG);
-}
-
-static inline int se_io_set_mode(void __iomem *base, int mode)
-{
- int ret = 0;
- unsigned int io_mode = 0;
- unsigned int geni_dma_mode = 0;
- unsigned int gsi_event_en = 0;
-
- io_mode = geni_read_reg(base, SE_IRQ_EN);
- geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
- gsi_event_en = geni_read_reg(base, SE_GSI_EVENT_EN);
-
- switch (mode) {
- case FIFO_MODE:
- {
- io_mode |= (GENI_M_IRQ_EN | GENI_S_IRQ_EN);
- io_mode |= (DMA_TX_IRQ_EN | DMA_RX_IRQ_EN);
- geni_dma_mode &= ~GENI_DMA_MODE_EN;
- gsi_event_en = 0;
- break;
-
- }
- case GSI_DMA:
- geni_dma_mode |= GENI_DMA_MODE_EN;
- io_mode &= ~(DMA_TX_IRQ_EN | DMA_RX_IRQ_EN);
- gsi_event_en |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN |
- GENI_M_EVENT_EN | GENI_S_EVENT_EN);
- break;
- default:
- ret = -ENXIO;
- goto exit_set_mode;
- }
- geni_write_reg(io_mode, base, SE_IRQ_EN);
- geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
- geni_write_reg(gsi_event_en, base, SE_GSI_EVENT_EN);
-exit_set_mode:
- return ret;
-}
-
-static inline void se_io_init(void __iomem *base)
-{
- unsigned int io_op_ctrl = 0;
- unsigned int geni_cgc_ctrl;
- unsigned int dma_general_cfg;
-
- geni_cgc_ctrl = geni_read_reg(base, GENI_CGC_CTRL);
- dma_general_cfg = geni_read_reg(base, SE_DMA_GENERAL_CFG);
- geni_cgc_ctrl |= DEFAULT_CGC_EN;
- dma_general_cfg |= (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON |
- DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON);
- io_op_ctrl |= DEFAULT_IO_OUTPUT_CTRL_MSK;
- geni_write_reg(geni_cgc_ctrl, base, GENI_CGC_CTRL);
- geni_write_reg(dma_general_cfg, base, SE_DMA_GENERAL_CFG);
-
- geni_write_reg(io_op_ctrl, base, GENI_OUTPUT_CTRL);
- geni_write_reg(FORCE_DEFAULT, base, GENI_FORCE_DEFAULT_REG);
-}
-
-static inline int geni_se_init(void __iomem *base, int mode,
+static inline int geni_se_init(void __iomem *base,
unsigned int rx_wm, unsigned int rx_rfr)
{
- int ret = 0;
+ return -ENXIO;
+}
- se_io_init(base);
- ret = se_io_set_mode(base, mode);
- if (ret)
- goto exit_geni_se_init;
-
- se_set_rx_rfr_wm(base, rx_wm, rx_rfr);
- ret = se_geni_irq_en(base, mode);
- if (ret)
- goto exit_geni_se_init;
-
-exit_geni_se_init:
- return ret;
+static inline int geni_se_select_mode(void __iomem *base, int mode)
+{
+ return -ENXIO;
}
static inline void geni_setup_m_cmd(void __iomem *base, u32 cmd,
u32 params)
{
- u32 m_cmd = geni_read_reg(base, SE_GENI_M_CMD0);
-
- m_cmd &= ~(M_OPCODE_MSK | M_PARAMS_MSK);
- m_cmd |= (cmd << M_OPCODE_SHFT);
- m_cmd |= (params & M_PARAMS_MSK);
- geni_write_reg(m_cmd, base, SE_GENI_M_CMD0);
}
static inline void geni_setup_s_cmd(void __iomem *base, u32 cmd,
u32 params)
{
- u32 s_cmd = geni_read_reg(base, SE_GENI_S_CMD0);
-
- s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
- s_cmd |= (cmd << S_OPCODE_SHFT);
- s_cmd |= (params & S_PARAMS_MSK);
- geni_write_reg(s_cmd, base, SE_GENI_S_CMD0);
}
static inline void geni_cancel_m_cmd(void __iomem *base)
{
- geni_write_reg(M_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG);
}
static inline void geni_cancel_s_cmd(void __iomem *base)
{
- geni_write_reg(S_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG);
}
static inline void geni_abort_m_cmd(void __iomem *base)
{
- geni_write_reg(M_GENI_CMD_ABORT, base, SE_GENI_M_CMD_CTRL_REG);
}
static inline void geni_abort_s_cmd(void __iomem *base)
{
- geni_write_reg(S_GENI_CMD_ABORT, base, SE_GENI_S_CMD_CTRL_REG);
}
static inline int get_tx_fifo_depth(void __iomem *base)
{
- int tx_fifo_depth;
-
- tx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_0)
- & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT);
- return tx_fifo_depth;
+ return -ENXIO;
}
static inline int get_tx_fifo_width(void __iomem *base)
{
- int tx_fifo_width;
-
- tx_fifo_width = ((geni_read_reg(base, SE_HW_PARAM_0)
- & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT);
- return tx_fifo_width;
+ return -ENXIO;
}
static inline int get_rx_fifo_depth(void __iomem *base)
{
- int rx_fifo_depth;
-
- rx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_1)
- & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT);
- return rx_fifo_depth;
+ return -ENXIO;
}
static inline void se_get_packing_config(int bpw, int pack_words,
bool msb_to_lsb, unsigned long *cfg0,
unsigned long *cfg1)
{
- u32 cfg[4] = {0};
- int len = ((bpw < 8) ? (bpw - 1) : 7);
- int idx = ((msb_to_lsb == 1) ? len : 0);
- int iter = (bpw * pack_words) >> 3;
- int i;
-
- for (i = 0; i < iter; i++) {
- cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1));
- idx += (len + 1);
- if (i == iter - 1)
- cfg[i] |= 1;
- }
- *cfg0 = cfg[0] | (cfg[1] << 10);
- *cfg1 = cfg[2] | (cfg[3] << 10);
}
static inline void se_config_packing(void __iomem *base, int bpw,
int pack_words, bool msb_to_lsb)
{
- unsigned long cfg0, cfg1;
-
- se_get_packing_config(bpw, pack_words, msb_to_lsb, &cfg0, &cfg1);
- geni_write_reg(cfg0, base, SE_GENI_TX_PACKING_CFG0);
- geni_write_reg(cfg1, base, SE_GENI_TX_PACKING_CFG1);
- geni_write_reg(cfg0, base, SE_GENI_RX_PACKING_CFG0);
- geni_write_reg(cfg1, base, SE_GENI_RX_PACKING_CFG1);
-}
-
-/*
- * Power/Resource Management functions
- */
-
-static inline int se_geni_clks_off(struct se_geni_rsc *rsc)
-{
- int ret = 0;
-
- clk_disable_unprepare(rsc->se_clk);
- clk_disable_unprepare(rsc->m_ahb_clk);
- clk_disable_unprepare(rsc->s_ahb_clk);
- return ret;
-}
-
-static inline int se_geni_resources_off(struct se_geni_rsc *rsc)
-{
- int ret = 0;
-
- ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_sleep);
- se_geni_clks_off(rsc);
- if (rsc->bus_bw)
- msm_bus_scale_update_bw(rsc->bus_bw, 0, 0);
- return ret;
-}
-
-static inline int se_geni_clks_on(struct se_geni_rsc *rsc)
-{
- int ret = 0;
-
- clk_prepare_enable(rsc->se_clk);
- clk_prepare_enable(rsc->m_ahb_clk);
- clk_prepare_enable(rsc->s_ahb_clk);
- return ret;
}
static inline int se_geni_resources_on(struct se_geni_rsc *rsc)
{
- int ret = 0;
-
- if (rsc->bus_bw)
- msm_bus_scale_update_bw(rsc->bus_bw, rsc->ab, rsc->ib);
- se_geni_clks_on(rsc);
- ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_active);
- return ret;
+ return -ENXIO;
}
+
+static inline int se_geni_resources_off(struct se_geni_rsc *rsc)
+{
+ return -ENXIO;
+}
+
+static inline int geni_se_resources_init(struct se_geni_rsc *rsc,
+ unsigned long ab, unsigned long ib)
+{
+ return -ENXIO;
+}
+
+static inline int geni_se_tx_dma_prep(struct device *wrapper_dev,
+ void __iomem *base, void *tx_buf, int tx_len, dma_addr_t *tx_dma)
+{
+ return -ENXIO;
+}
+
+static inline int geni_se_rx_dma_prep(struct device *wrapper_dev,
+ void __iomem *base, void *rx_buf, int rx_len, dma_addr_t *rx_dma)
+{
+ return -ENXIO;
+}
+
+static inline void geni_se_tx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t tx_dma, int tx_len)
+{
+}
+
+static inline void geni_se_rx_dma_unprep(struct device *wrapper_dev,
+ dma_addr_t rx_dma, int rx_len)
+{
+}
+
+static inline int geni_se_qupv3_hw_version(struct device *wrapper_dev,
+ unsigned int *major, unsigned int *minor, unsigned int *step)
+{
+ return -ENXIO;
+}
+
+static inline int geni_se_iommu_map_buf(struct device *wrapper_dev,
+ dma_addr_t *iova, void *buf, size_t size, enum dma_data_direction dir)
+{
+ return -ENXIO;
+}
+
+static inline void *geni_se_iommu_alloc_buf(struct device *wrapper_dev,
+ dma_addr_t *iova, size_t size)
+{
+ return NULL;
+}
+
+static inline int geni_se_iommu_unmap_buf(struct device *wrapper_dev,
+ dma_addr_t *iova, size_t size, enum dma_data_direction dir)
+{
+ return -ENXIO;
+
+}
+
+static inline int geni_se_iommu_free_buf(struct device *wrapper_dev,
+ dma_addr_t *iova, void *buf, size_t size)
+{
+ return -ENXIO;
+}
+
+#endif
#endif
diff --git a/include/trace/events/power.h b/include/trace/events/power.h
index d55175e..57693e7 100644
--- a/include/trace/events/power.h
+++ b/include/trace/events/power.h
@@ -794,6 +794,323 @@
__entry->nl, __entry->pl, __entry->flags)
);
+DECLARE_EVENT_CLASS(kpm_module,
+
+ TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus),
+
+ TP_ARGS(managed_cpus, max_cpus),
+
+ TP_STRUCT__entry(
+ __field(u32, managed_cpus)
+ __field(u32, max_cpus)
+ ),
+
+ TP_fast_assign(
+ __entry->managed_cpus = managed_cpus;
+ __entry->max_cpus = max_cpus;
+ ),
+
+ TP_printk("managed:%x max_cpus=%u", (unsigned int)__entry->managed_cpus,
+ (unsigned int)__entry->max_cpus)
+);
+
+DEFINE_EVENT(kpm_module, set_max_cpus,
+ TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus),
+ TP_ARGS(managed_cpus, max_cpus)
+);
+
+DEFINE_EVENT(kpm_module, reevaluate_hotplug,
+ TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus),
+ TP_ARGS(managed_cpus, max_cpus)
+);
+
+DECLARE_EVENT_CLASS(kpm_module2,
+
+ TP_PROTO(unsigned int cpu, unsigned int enter_cycle_cnt,
+ unsigned int exit_cycle_cnt,
+ unsigned int io_busy, u64 iowait),
+
+ TP_ARGS(cpu, enter_cycle_cnt, exit_cycle_cnt, io_busy, iowait),
+
+ TP_STRUCT__entry(
+ __field(u32, cpu)
+ __field(u32, enter_cycle_cnt)
+ __field(u32, exit_cycle_cnt)
+ __field(u32, io_busy)
+ __field(u64, iowait)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->enter_cycle_cnt = enter_cycle_cnt;
+ __entry->exit_cycle_cnt = exit_cycle_cnt;
+ __entry->io_busy = io_busy;
+ __entry->iowait = iowait;
+ ),
+
+ TP_printk("CPU:%u enter_cycles=%u exit_cycles=%u io_busy=%u iowait=%lu",
+ (unsigned int)__entry->cpu,
+ (unsigned int)__entry->enter_cycle_cnt,
+ (unsigned int)__entry->exit_cycle_cnt,
+ (unsigned int)__entry->io_busy,
+ (unsigned long)__entry->iowait)
+);
+
+DEFINE_EVENT(kpm_module2, track_iowait,
+ TP_PROTO(unsigned int cpu, unsigned int enter_cycle_cnt,
+ unsigned int exit_cycle_cnt, unsigned int io_busy, u64 iowait),
+ TP_ARGS(cpu, enter_cycle_cnt, exit_cycle_cnt, io_busy, iowait)
+);
+
+DECLARE_EVENT_CLASS(cpu_modes,
+
+ TP_PROTO(unsigned int cpu, unsigned int max_load,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int total_load, unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycle_cnt,
+ unsigned int perf_cl_peak_enter_cycle_cnt,
+ unsigned int perf_cl_peak_exit_cycle_cnt,
+ unsigned int mode,
+ unsigned int cpu_cnt),
+
+ TP_ARGS(cpu, max_load, single_enter_cycle_cnt, single_exit_cycle_cnt,
+ total_load, multi_enter_cycle_cnt, multi_exit_cycle_cnt,
+ perf_cl_peak_enter_cycle_cnt, perf_cl_peak_exit_cycle_cnt, mode,
+ cpu_cnt),
+
+ TP_STRUCT__entry(
+ __field(u32, cpu)
+ __field(u32, max_load)
+ __field(u32, single_enter_cycle_cnt)
+ __field(u32, single_exit_cycle_cnt)
+ __field(u32, total_load)
+ __field(u32, multi_enter_cycle_cnt)
+ __field(u32, multi_exit_cycle_cnt)
+ __field(u32, perf_cl_peak_enter_cycle_cnt)
+ __field(u32, perf_cl_peak_exit_cycle_cnt)
+ __field(u32, mode)
+ __field(u32, cpu_cnt)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->max_load = max_load;
+ __entry->single_enter_cycle_cnt = single_enter_cycle_cnt;
+ __entry->single_exit_cycle_cnt = single_exit_cycle_cnt;
+ __entry->total_load = total_load;
+ __entry->multi_enter_cycle_cnt = multi_enter_cycle_cnt;
+ __entry->multi_exit_cycle_cnt = multi_exit_cycle_cnt;
+ __entry->perf_cl_peak_enter_cycle_cnt =
+ perf_cl_peak_enter_cycle_cnt;
+ __entry->perf_cl_peak_exit_cycle_cnt =
+ perf_cl_peak_exit_cycle_cnt;
+ __entry->mode = mode;
+ __entry->cpu_cnt = cpu_cnt;
+ ),
+
+ TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%u",
+ (unsigned int)__entry->cpu, (unsigned int)__entry->max_load,
+ (unsigned int)__entry->single_enter_cycle_cnt,
+ (unsigned int)__entry->single_exit_cycle_cnt,
+ (unsigned int)__entry->total_load,
+ (unsigned int)__entry->multi_enter_cycle_cnt,
+ (unsigned int)__entry->multi_exit_cycle_cnt,
+ (unsigned int)__entry->perf_cl_peak_enter_cycle_cnt,
+ (unsigned int)__entry->perf_cl_peak_exit_cycle_cnt,
+ (unsigned int)__entry->mode,
+ (unsigned int)__entry->cpu_cnt)
+);
+
+DEFINE_EVENT(cpu_modes, cpu_mode_detect,
+ TP_PROTO(unsigned int cpu, unsigned int max_load,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int total_load, unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycle_cnt,
+ unsigned int perf_cl_peak_enter_cycle_cnt,
+ unsigned int perf_cl_peak_exit_cycle_cnt,
+ unsigned int mode,
+ unsigned int cpu_cnt),
+ TP_ARGS(cpu, max_load, single_enter_cycle_cnt, single_exit_cycle_cnt,
+ total_load, multi_enter_cycle_cnt, multi_exit_cycle_cnt,
+ perf_cl_peak_enter_cycle_cnt, perf_cl_peak_exit_cycle_cnt,
+ mode, cpu_cnt)
+);
+
+DECLARE_EVENT_CLASS(timer_status,
+ TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycles,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int multi_enter_cycles,
+ unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycles,
+ unsigned int multi_exit_cycle_cnt, unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt,
+ single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles,
+ multi_enter_cycle_cnt, multi_exit_cycles,
+ multi_exit_cycle_cnt, timer_rate, mode),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, cpu)
+ __field(unsigned int, single_enter_cycles)
+ __field(unsigned int, single_enter_cycle_cnt)
+ __field(unsigned int, single_exit_cycles)
+ __field(unsigned int, single_exit_cycle_cnt)
+ __field(unsigned int, multi_enter_cycles)
+ __field(unsigned int, multi_enter_cycle_cnt)
+ __field(unsigned int, multi_exit_cycles)
+ __field(unsigned int, multi_exit_cycle_cnt)
+ __field(unsigned int, timer_rate)
+ __field(unsigned int, mode)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->single_enter_cycles = single_enter_cycles;
+ __entry->single_enter_cycle_cnt = single_enter_cycle_cnt;
+ __entry->single_exit_cycles = single_exit_cycles;
+ __entry->single_exit_cycle_cnt = single_exit_cycle_cnt;
+ __entry->multi_enter_cycles = multi_enter_cycles;
+ __entry->multi_enter_cycle_cnt = multi_enter_cycle_cnt;
+ __entry->multi_exit_cycles = multi_exit_cycles;
+ __entry->multi_exit_cycle_cnt = multi_exit_cycle_cnt;
+ __entry->timer_rate = timer_rate;
+ __entry->mode = mode;
+ ),
+
+ TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u",
+ (unsigned int) __entry->cpu,
+ (unsigned int) __entry->single_enter_cycles,
+ (unsigned int) __entry->single_enter_cycle_cnt,
+ (unsigned int) __entry->single_exit_cycles,
+ (unsigned int) __entry->single_exit_cycle_cnt,
+ (unsigned int) __entry->multi_enter_cycles,
+ (unsigned int) __entry->multi_enter_cycle_cnt,
+ (unsigned int) __entry->multi_exit_cycles,
+ (unsigned int) __entry->multi_exit_cycle_cnt,
+ (unsigned int) __entry->timer_rate,
+ (unsigned int) __entry->mode)
+);
+
+DEFINE_EVENT(timer_status, single_mode_timeout,
+ TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycles,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int multi_enter_cycles,
+ unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycles,
+ unsigned int multi_exit_cycle_cnt, unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt,
+ single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles,
+ multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt,
+ timer_rate, mode)
+);
+
+DEFINE_EVENT(timer_status, single_cycle_exit_timer_start,
+ TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycles,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int multi_enter_cycles,
+ unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycles,
+ unsigned int multi_exit_cycle_cnt, unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt,
+ single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles,
+ multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt,
+ timer_rate, mode)
+);
+
+DEFINE_EVENT(timer_status, single_cycle_exit_timer_stop,
+ TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles,
+ unsigned int single_enter_cycle_cnt,
+ unsigned int single_exit_cycles,
+ unsigned int single_exit_cycle_cnt,
+ unsigned int multi_enter_cycles,
+ unsigned int multi_enter_cycle_cnt,
+ unsigned int multi_exit_cycles,
+ unsigned int multi_exit_cycle_cnt, unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt,
+ single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles,
+ multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt,
+ timer_rate, mode)
+);
+
+DECLARE_EVENT_CLASS(perf_cl_peak_timer_status,
+ TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles,
+ unsigned int perf_cl_peak_enter_cycle_cnt,
+ unsigned int perf_cl_peak_exit_cycles,
+ unsigned int perf_cl_peak_exit_cycle_cnt,
+ unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt,
+ perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt,
+ timer_rate, mode),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, cpu)
+ __field(unsigned int, perf_cl_peak_enter_cycles)
+ __field(unsigned int, perf_cl_peak_enter_cycle_cnt)
+ __field(unsigned int, perf_cl_peak_exit_cycles)
+ __field(unsigned int, perf_cl_peak_exit_cycle_cnt)
+ __field(unsigned int, timer_rate)
+ __field(unsigned int, mode)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->perf_cl_peak_enter_cycles = perf_cl_peak_enter_cycles;
+ __entry->perf_cl_peak_enter_cycle_cnt =
+ perf_cl_peak_enter_cycle_cnt;
+ __entry->perf_cl_peak_exit_cycles = perf_cl_peak_exit_cycles;
+ __entry->perf_cl_peak_exit_cycle_cnt =
+ perf_cl_peak_exit_cycle_cnt;
+ __entry->timer_rate = timer_rate;
+ __entry->mode = mode;
+ ),
+
+ TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u",
+ (unsigned int) __entry->cpu,
+ (unsigned int) __entry->perf_cl_peak_enter_cycles,
+ (unsigned int) __entry->perf_cl_peak_enter_cycle_cnt,
+ (unsigned int) __entry->perf_cl_peak_exit_cycles,
+ (unsigned int) __entry->perf_cl_peak_exit_cycle_cnt,
+ (unsigned int) __entry->timer_rate,
+ (unsigned int) __entry->mode)
+);
+
+DEFINE_EVENT(perf_cl_peak_timer_status, perf_cl_peak_exit_timer_start,
+ TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles,
+ unsigned int perf_cl_peak_enter_cycle_cnt,
+ unsigned int perf_cl_peak_exit_cycles,
+ unsigned int perf_cl_peak_exit_cycle_cnt,
+ unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt,
+ perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt,
+ timer_rate, mode)
+);
+
+
+DEFINE_EVENT(perf_cl_peak_timer_status, perf_cl_peak_exit_timer_stop,
+ TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles,
+ unsigned int perf_cl_peak_enter_cycle_cnt,
+ unsigned int perf_cl_peak_exit_cycles,
+ unsigned int perf_cl_peak_exit_cycle_cnt,
+ unsigned int timer_rate,
+ unsigned int mode),
+ TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt,
+ perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt,
+ timer_rate, mode)
+);
+
#endif /* _TRACE_POWER_H */
/* This part must be outside protection */
diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h
index 817feba..ea68202 100644
--- a/include/uapi/linux/msm_ipa.h
+++ b/include/uapi/linux/msm_ipa.h
@@ -449,6 +449,7 @@
* @IPA_HW_v3_1: IPA hardware version 3.1
* @IPA_HW_v3_5: IPA hardware version 3.5
* @IPA_HW_v3_5_1: IPA hardware version 3.5.1
+ * @IPA_HW_v4_0: IPA hardware version 4.0
*/
enum ipa_hw_type {
IPA_HW_None = 0,
@@ -463,9 +464,12 @@
IPA_HW_v3_1 = 11,
IPA_HW_v3_5 = 12,
IPA_HW_v3_5_1 = 13,
+ IPA_HW_v4_0 = 14,
IPA_HW_MAX
};
+#define IPA_HW_v4_0 IPA_HW_v4_0
+
/**
* struct ipa_rule_attrib - attributes of a routing/filtering
* rule, all in LE
diff --git a/kernel/sched/tune.c b/kernel/sched/tune.c
index bae3b2b..86a167b 100644
--- a/kernel/sched/tune.c
+++ b/kernel/sched/tune.c
@@ -1066,10 +1066,6 @@
* Assume we have EM data only at the CPU and
* the upper CLUSTER level
*/
- BUG_ON(!cpumask_equal(
- sched_group_cpus(sg),
- sched_group_cpus(sd2->parent->groups)
- ));
break;
}
}