[MIPS] IP27: Fix collision with hardcoded interrupt number.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 36b662e..1fb860c 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -89,11 +89,13 @@
}
#endif
+static unsigned int rt_timer_irq;
+
void ip27_rt_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int cpuA = cputoslice(cpu) == 0;
- int irq = 9; /* XXX Assign number */
+ unsigned int irq = rt_timer_irq;
irq_enter();
write_seqlock(&xtime_lock);
@@ -179,13 +181,68 @@
return mktime(year, month, date, hour, min, sec);
}
+static void startup_rt_irq(unsigned int irq)
+{
+}
+
+static void shutdown_rt_irq(unsigned int irq)
+{
+}
+
+static void enable_rt_irq(unsigned int irq)
+{
+}
+
+static void disable_rt_irq(unsigned int irq)
+{
+}
+
+static void mask_and_ack_rt(unsigned int irq)
+{
+}
+
+static void end_rt_irq(unsigned int irq)
+{
+}
+
+static struct hw_interrupt_type rt_irq_type = {
+ .typename = "SN HUB RT timer",
+ .startup = startup_rt_irq,
+ .shutdown = shutdown_rt_irq,
+ .enable = enable_rt_irq,
+ .disable = disable_rt_irq,
+ .ack = mask_and_ack_rt,
+ .end = end_rt_irq,
+};
+
+static struct irqaction rt_irqaction = {
+ .handler = ip27_rt_timer_interrupt,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "timer"
+};
+
+extern int allocate_irqno(void);
+
static void ip27_timer_setup(struct irqaction *irq)
{
+ int irqno = allocate_irqno();
+
+ if (irqno < 0)
+ panic("Can't allocate interrupt number for timer interrupt");
+
+ irq_desc[irqno].status = IRQ_DISABLED;
+ irq_desc[irqno].action = NULL;
+ irq_desc[irqno].depth = 1;
+ irq_desc[irqno].handler = &rt_irq_type;
+
/* over-write the handler, we use our own way */
irq->handler = no_action;
/* setup irqaction */
-// setup_irq(IP27_TIMER_IRQ, irq); /* XXX Can't do this yet. */
+ irq_desc[irqno].status |= IRQ_PER_CPU;
+
+ rt_timer_irq = irqno;
}
void __init ip27_time_init(void)