| commit | 7879c157bb5e05bdc29f728ccec58b828dd82a37 | [log] [tgz] |
|---|---|---|
| author | Kuogee Hsieh <khsieh@codeaurora.org> | Wed Apr 15 13:47:01 2015 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Wed Jan 18 18:11:46 2017 -0800 |
| tree | 689e132f36d8557658faf8a08d7595bdc9b71b75 | |
| parent | bfbfa0d2bd335bbef198badeeb2efd80d15c8b47 [diff] |
msm: mdss: fixed calculation of pll fractional divider Pll unlocked due to wrong pll fractional divider calculated. Pll fraction divider should be reminder of 2^20 after vco rate divided by reference clock rate. Change-Id: I9e4c2e3c0631e533d114c3e6acf65b71b9bf00d2 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>