| commit | 3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Apr 20 14:47:25 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Apr 28 12:41:48 2016 +0200 |
| tree | 0cfdef423920ea986eaa0bec6d8892ec741bc0ce | |
| parent | 1ec7032ad517714108cc53a6ee7067276ca21e80 [diff] |
clk: tegra: Use correct parent for dpaux clock The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m. Signed-off-by: Thierry Reding <treding@nvidia.com>