| commit | 8e048b9997efbe75fe77b1f14d3af41700cc8724 | [log] [tgz] |
|---|---|---|
| author | Linus Walleij <linus.walleij@linaro.org> | Fri Nov 22 16:25:09 2013 +0100 |
| committer | Linus Walleij <linus.walleij@linaro.org> | Fri Jan 03 22:27:54 2014 +0100 |
| tree | bdb60e1592cc4af363774f07c1a2605dafa4bc89 | |
| parent | ae6e694ef566ed69a2537c80771a9031ec627494 [diff] |
clk: versatile: fixup IM-PD1 clock implementation Register both VCO clocks, give per-logical module unique names to the clocks so we can have several IM-PD1's connected (in theory). Implement all the fixed-factor clocks as children of VCO2. Tested by using the UARTs and the PL181 MMC block on the IM-PD1, works flawlessly. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>