tree d3b7c9b1ec316b1bc5838f754c43f8b8a3250049
parent 3eb61566a6efc5a56ebe1e6b86519bc5e0b39003
author Rhyland Klein <rklein@nvidia.com> 1452799475 -0500
committer Thierry Reding <treding@nvidia.com> 1454424564 +0100

clk: tegra: Fix pllx dyn step calculation

The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>