clk: msm: Update pll clock ops for SDM439/SDM429
pll hardware on SDM439/429 requires 50uSec to stabilise
after it has been brought out of reset. Update pll clock ops
where we add 50uSec delay before polling pll lock status.
Change-Id: Ib2b7c5c5be3fbb0ab64b5f9c06d6aaaede479a32
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
diff --git a/drivers/clk/msm/clock-gcc-8952.c b/drivers/clk/msm/clock-gcc-8952.c
index 6d7727f..d471138 100644
--- a/drivers/clk/msm/clock-gcc-8952.c
+++ b/drivers/clk/msm/clock-gcc-8952.c
@@ -216,6 +216,7 @@
.config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
.status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
.freq_tbl = apcs_c0_pll_freq,
+ .config_ctl_reg = (void __iomem *)APCS_C0_PLL_CONFIG_CTL,
.masks = {
.vco_mask = BM(29, 28),
.pre_div_mask = BIT(12),
@@ -283,6 +284,7 @@
.config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
.status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
.freq_tbl = apcs_c1_pll_freq,
+ .config_ctl_reg = (void __iomem *)APCS_C1_PLL_CONFIG_CTL,
.masks = {
.vco_mask = BM(29, 28),
.pre_div_mask = BIT(12),
@@ -4407,6 +4409,11 @@
if (compat_bin2 || compat_bin4 || compat_bin5)
nbases = APCS_C0_PLL_BASE;
+ if (compat_bin5 || compat_bin6) {
+ a53ss_c0_pll.c.ops = &clk_ops_acpu_pll;
+ a53ss_c1_pll.c.ops = &clk_ops_acpu_pll;
+ }
+
ret = get_mmio_addr(pdev, nbases);
if (ret)
return ret;