amd64_edac: Correct erratum 505 range
Basically we want to cover all 0x0-0xf models, i.e. Orochi and later.
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/20130819192321.GF4165@pd.tnic
Signed-off-by: Borislav Petkov <bp@suse.de>
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index b86228c..6952d43 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -206,8 +206,8 @@
if (pvt->fam == 0xf)
min_scrubrate = 0x0;
- /* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
- if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
+ /* Erratum #505 */
+ if (pvt->fam == 0x15 && pvt->model < 0x10)
f15h_select_dct(pvt, 0);
return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
@@ -219,8 +219,8 @@
u32 scrubval = 0;
int i, retval = -EINVAL;
- /* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
- if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
+ /* Erratum #505 */
+ if (pvt->fam == 0x15 && pvt->model < 0x10)
f15h_select_dct(pvt, 0);
amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);