tree e3cf04e4099a9414b15d27f6428f7726f29d7a05
parent d0d44dd4ac58bc547646a9d0e65b4648f97cb533
author Stephen Boyd <sboyd@codeaurora.org> 1389811642 -0800
committer Mike Turquette <mturquette@linaro.org> 1389902457 -0800

clk: Add set_rate_and_parent() op

Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.

Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>