| commit | 40a5dcba4e79023f0b511dc0ca498bdf9eacb5db | [log] [tgz] |
|---|---|---|
| author | Emilio López <emilio@elopez.com.ar> | Mon Dec 23 00:32:32 2013 -0300 |
| committer | Emilio López <emilio@elopez.com.ar> | Sat Dec 28 17:07:42 2013 -0300 |
| tree | cb8669f36dde36c379ae806f3c54e2e1c0d87efb | |
| parent | 0903ea60173fab226a867ceb080b2e0269a6c975 [diff] |
clk: sunxi: register factors clocks behind composite This commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>