| /* | |
| * GXBB clock tree IDs | |
| */ | |
| #ifndef __GXBB_CLKC_H | |
| #define __GXBB_CLKC_H | |
| #define CLKID_CPUCLK 1 | |
| #define CLKID_HDMI_PLL 2 | |
| #define CLKID_FCLK_DIV2 4 | |
| #define CLKID_FCLK_DIV3 5 | |
| #define CLKID_FCLK_DIV4 6 | |
| #define CLKID_CLK81 12 | |
| #define CLKID_ETH 36 | |
| #define CLKID_SD_EMMC_A 94 | |
| #define CLKID_SD_EMMC_B 95 | |
| #define CLKID_SD_EMMC_C 96 | |
| #endif /* __GXBB_CLKC_H */ |