| commit | 419b1b7ae13ed0518032ff8d564c0efc0008d20d | [log] [tgz] |
|---|---|---|
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | Wed Apr 27 15:44:19 2016 +0300 |
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | Fri Apr 29 09:56:22 2016 +0300 |
| tree | bafa4cd7432bcafe844de339d6bb43988b9e2b12 | |
| parent | 844b2f9a5d061e5d2d09b0664fad0e0bfa39dc39 [diff] [blame] |
drm/i915: Unduplicate CHV phy-releated pre pll enabling code The same logic is used for DP and HDMI so move it to intel_dpio_phy.c. v2: Rebase Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-5-git-send-email-ander.conselvan.de.oliveira@intel.com
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 123f6ba..66403b5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3595,6 +3595,7 @@ bool uniq_trans_scale); void chv_data_lane_soft_reset(struct intel_encoder *encoder, bool reset); +void chv_phy_pre_pll_enable(struct intel_encoder *encoder); int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);