ARM: dts: msm: Add PCIe endpoint node for sdxpoorwills
Add PCIe endpoint node to device tree of sdxpoorwills. PCIe core
is in endpoint mode and communicates with the PCIe root complex
on host side.
Change-Id: Ibbe9f840ac51459db7eac26b2ddb900e4d9265ce
Signed-off-by: Yan He <yanhe@codeaurora.org>
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi
index 1e212b7..60674e5 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi
@@ -982,6 +982,44 @@
};
};
+ pcie_ep {
+ pcie_ep_clkreq_default: pcie_ep_clkreq_default {
+ mux {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ };
+ config {
+ pins = "gpio56";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie_ep_perst_default: pcie_ep_perst_default {
+ mux {
+ pins = "gpio57";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio57";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie_ep_wake_default: pcie_ep_wake_default {
+ mux {
+ pins = "gpio53";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio53";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
wcd9xxx_intr {
wcd_intr_default: wcd_intr_default{
mux {
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index 5829942..19215dc 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -268,6 +268,142 @@
reg = <0x00137004 0x4>;
};
+ pcie_ep: qcom,pcie@40002000 {
+ compatible = "qcom,pcie-ep";
+
+ reg = <0x40002000 0x1000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x40001000 0x1000>,
+ <0x01c00000 0x2000>,
+ <0x01c02000 0x1000>,
+ <0x01c04000 0x1000>;
+ reg-names = "msi", "dm_core", "elbi", "iatu", "parf",
+ "phy", "mmio";
+
+ #address-cells = <0>;
+ interrupt-parent = <&pcie_ep>;
+ interrupts = <0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 140 0>;
+ interrupt-names = "int_global";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+ &pcie_ep_wake_default>;
+
+ clkreq-gpio = <&tlmm 56 0>;
+ perst-gpio = <&tlmm 57 0>;
+ wake-gpio = <&tlmm 53 0>;
+
+ gdsc-vdd-supply = <&gdsc_pcie>;
+ vreg-1.8-supply = <&pmxpoorwills_l1>;
+ vreg-0.9-supply = <&pmxpoorwills_l4>;
+
+ qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
+ qcom,vreg-0.9-voltage-level = <872000 872000 24000>;
+
+ clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>,
+ <&clock_gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_AUX_CLK>,
+ <&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
+ <&clock_gcc GCC_PCIE_SLEEP_CLK>,
+ <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "pcie_0_pipe_clk", "pcie_0_cfg_ahb_clk",
+ "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+ "pcie_0_aux_clk", "pcie_0_ldo",
+ "pcie_0_sleep_clk",
+ "pcie_0_slv_q2a_axi_clk";
+
+ resets = <&clock_gcc GCC_PCIE_BCR>,
+ <&clock_gcc GCC_PCIE_PHY_BCR>;
+
+ reset-names = "pcie_0_core_reset",
+ "pcie_0_phy_reset";
+
+ qcom,msm-bus,name = "pcie-ep";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <45 512 0 0>,
+ <45 512 500 800>;
+
+ qcom,pcie-link-speed = <2>;
+ qcom,pcie-phy-ver = <6>;
+ qcom,pcie-active-config;
+ qcom,pcie-aggregated-irq;
+ qcom,pcie-mhi-a7-irq;
+ qcom,phy-status-reg = <0x814>;
+
+ qcom,phy-init = <0x840 0x001 0x0 0x1
+ 0x094 0x000 0x0 0x1
+ 0x058 0x00f 0x0 0x1
+ 0x0a4 0x042 0x0 0x1
+ 0x110 0x024 0x0 0x1
+ 0x1bc 0x011 0x0 0x1
+ 0x0bc 0x019 0x0 0x1
+ 0x0b0 0x004 0x0 0x1
+ 0x0ac 0x0ff 0x0 0x1
+ 0x158 0x001 0x0 0x1
+ 0x074 0x028 0x0 0x1
+ 0x07c 0x00d 0x0 0x1
+ 0x084 0x000 0x0 0x1
+ 0x1b0 0x01d 0x0 0x1
+ 0x1ac 0x056 0x0 0x1
+ 0x04c 0x007 0x0 0x1
+ 0x050 0x007 0x0 0x1
+ 0x0f0 0x003 0x0 0x1
+ 0x0ec 0x0fb 0x0 0x1
+ 0x00c 0x002 0x0 0x1
+ 0x29c 0x012 0x0 0x1
+ 0x284 0x005 0x0 0x1
+ 0x234 0x0d9 0x0 0x1
+ 0x238 0x0cc 0x0 0x1
+ 0x51c 0x003 0x0 0x1
+ 0x518 0x01c 0x0 0x1
+ 0x524 0x014 0x0 0x1
+ 0x4ec 0x00e 0x0 0x1
+ 0x4f0 0x04a 0x0 0x1
+ 0x4f4 0x00f 0x0 0x1
+ 0x5b4 0x004 0x0 0x1
+ 0x434 0x07f 0x0 0x1
+ 0x444 0x070 0x0 0x1
+ 0x510 0x017 0x0 0x1
+ 0x4d8 0x001 0x0 0x1
+ 0x598 0x0e0 0x0 0x1
+ 0x59c 0x0c8 0x0 0x1
+ 0x5a0 0x0c8 0x0 0x1
+ 0x5a4 0x009 0x0 0x1
+ 0x5a8 0x0b1 0x0 0x1
+ 0x584 0x024 0x0 0x1
+ 0x588 0x0e4 0x0 0x1
+ 0x58c 0x0ec 0x0 0x1
+ 0x590 0x039 0x0 0x1
+ 0x594 0x036 0x0 0x1
+ 0x570 0x0ef 0x0 0x1
+ 0x574 0x0ef 0x0 0x1
+ 0x578 0x02f 0x0 0x1
+ 0x57c 0x0d3 0x0 0x1
+ 0x580 0x040 0x0 0x1
+ 0x4fc 0x000 0x0 0x1
+ 0x4f8 0x0c0 0x0 0x1
+ 0x9a4 0x001 0x0 0x1
+ 0x840 0x001 0x0 0x1
+ 0x848 0x001 0x0 0x1
+ 0x8a0 0x011 0x0 0x1
+ 0x988 0x088 0x0 0x1
+ 0x998 0x008 0x0 0x1
+ 0x8dc 0x00d 0x0 0x1
+ 0x800 0x000 0x0 0x1
+ 0x844 0x003 0x0 0x1>;
+
+ status = "disabled";
+ };
+
gdsc_emac: qcom,gdsc@147004 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_emac";