Merge "diag: Add new WLAN_RSN event id"
diff --git a/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt b/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt
index d9d3470..432c482 100644
--- a/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt
+++ b/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt
@@ -10,6 +10,7 @@
Required properties:
- compatible : should be "qcom,qpnp-vadc" for Voltage ADC device driver and
"qcom,qpnp-vadc-hc" for VADC_HC voltage ADC device driver.
+ should include "qcom,qpnp-adc-hc-pm5" for PMIC5.
- reg : offset and length of the PMIC Aribter register map.
- address-cells : Must be one.
- size-cells : Must be zero.
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 78aa1d7..4839df4 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -77,6 +77,21 @@
- qcom,tz-device-id : A string indicating the device ID for this SMMU known
to TZ. See msm_tz_smmu.c for a full list of mappings.
+- qcom,enable-static-cb:
+ A boolean indicating that the SMMU global register space,
+ as well as some context banks, are managed by secure software
+ and may not be modified by HLOS.
+
+- qcom,static-ns-cbs:
+ A list of u32.
+ When qcom,enable-static-cb is selected, indicates which
+ iommu context banks may be used by HLOS.
+
+- qcom,hibernation-support:
+ A boolean, indicates that hibernation should be supported and
+ all secure usecases should be disabled, since they cannot be
+ restored properly.
+
- qcom,skip-init : Disable resetting configuration for all context banks
during device reset. This is useful for targets where
some context banks are dedicated to other execution
diff --git a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
index 97b71a7..d3f765c 100644
--- a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
+++ b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
@@ -13,6 +13,7 @@
Required properties:
- compatible : should be "qcom,qpnp-adc-tm-hc" for thermal ADC driver using
refreshed BTM peripheral.
+ should include "qcom,qpnp-adc-tm-hc-pm5" for PMIC5.
- reg : offset and length of the PMIC Aribter register map.
- address-cells : Must be one.
- size-cells : Must be zero.
diff --git a/arch/arm/configs/msm8909-perf_defconfig b/arch/arm/configs/msm8909-perf_defconfig
index 6f3cee4..aee8104 100644
--- a/arch/arm/configs/msm8909-perf_defconfig
+++ b/arch/arm/configs/msm8909-perf_defconfig
@@ -425,6 +425,7 @@
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_PWM=y
CONFIG_PWM_QPNP=y
+CONFIG_QTI_MPM=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_SENSORS_SSC=y
diff --git a/arch/arm/configs/msm8909_defconfig b/arch/arm/configs/msm8909_defconfig
index f57e45d..b82c3fd 100644
--- a/arch/arm/configs/msm8909_defconfig
+++ b/arch/arm/configs/msm8909_defconfig
@@ -420,6 +420,7 @@
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_PWM=y
CONFIG_PWM_QPNP=y
+CONFIG_QTI_MPM=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_SENSORS_SSC=y
diff --git a/arch/arm/configs/msm8937-perf_defconfig b/arch/arm/configs/msm8937-perf_defconfig
index 5a6de0f..09b6f05 100644
--- a/arch/arm/configs/msm8937-perf_defconfig
+++ b/arch/arm/configs/msm8937-perf_defconfig
@@ -308,6 +308,8 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FT5X06=y
+CONFIG_TOUCHSCREEN_GEN_VKEYS=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_HBTP_INPUT=y
CONFIG_INPUT_QPNP_POWER_ON=y
diff --git a/arch/arm/configs/msm8937_defconfig b/arch/arm/configs/msm8937_defconfig
index 858b506..1fefcc616 100644
--- a/arch/arm/configs/msm8937_defconfig
+++ b/arch/arm/configs/msm8937_defconfig
@@ -313,6 +313,8 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FT5X06=y
+CONFIG_TOUCHSCREEN_GEN_VKEYS=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_HBTP_INPUT=y
CONFIG_INPUT_QPNP_POWER_ON=y
diff --git a/arch/arm/configs/sdxpoorwills-perf_defconfig b/arch/arm/configs/sdxpoorwills-perf_defconfig
index 04affb1..0e971d2 100644
--- a/arch/arm/configs/sdxpoorwills-perf_defconfig
+++ b/arch/arm/configs/sdxpoorwills-perf_defconfig
@@ -399,6 +399,7 @@
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_ON_RECURSIVE_FAULT=y
CONFIG_PANIC_TIMEOUT=5
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
diff --git a/arch/arm/configs/sdxpoorwills_defconfig b/arch/arm/configs/sdxpoorwills_defconfig
index 4232b47..52f3fda 100644
--- a/arch/arm/configs/sdxpoorwills_defconfig
+++ b/arch/arm/configs/sdxpoorwills_defconfig
@@ -411,6 +411,7 @@
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_PANIC_ON_RECURSIVE_FAULT=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_SPINLOCK=y
diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
index ab088b8..707875b 100644
--- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -27,14 +27,14 @@
vdd-supply = <&gpu_cx_gdsc>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "gcc_gpu_memnoc_gfx_clk";
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
attach-impl-defs =
diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
index e4fe2e3..0ac9c2a 100644
--- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -27,14 +27,14 @@
vdd-supply = <&gpu_cx_gdsc>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "gcc_gpu_memnoc_gfx_clk";
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
attach-impl-defs =
diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi
index dbdd9d9..36db486 100644
--- a/arch/arm64/boot/dts/qcom/msm8917.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi
@@ -1423,6 +1423,86 @@
status = "disabled";
};
+ qcom,wcnss-wlan@a000000 {
+ compatible = "qcom,wcnss_wlan";
+ reg = <0xa000000 0x280000>,
+ <0xb011008 0x4>,
+ <0xa21b000 0x3000>,
+ <0x3204000 0x100>,
+ <0x3200800 0x200>,
+ <0xa100400 0x200>,
+ <0xa205050 0x200>,
+ <0xa219000 0x20>,
+ <0xa080488 0x8>,
+ <0xa080fb0 0x8>,
+ <0xa08040c 0x8>,
+ <0xa0120a8 0x8>,
+ <0xa012448 0x8>,
+ <0xa080c00 0x1>;
+
+ reg-names = "wcnss_mmio", "wcnss_fiq",
+ "pronto_phy_base", "riva_phy_base",
+ "riva_ccu_base", "pronto_a2xb_base",
+ "pronto_ccpu_base", "pronto_saw2_base",
+ "wlan_tx_phy_aborts","wlan_brdg_err_source",
+ "wlan_tx_status", "alarms_txctl",
+ "alarms_tactl", "pronto_mcu_base";
+
+ interrupts = <0 145 0 0 146 0>;
+ interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+ qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>;
+ qcom,pronto-vddcx-supply = <&pm8937_s2_level>;
+ qcom,pronto-vddpx-supply = <&pm8937_l5>;
+ qcom,iris-vddxo-supply = <&pm8937_l7>;
+ qcom,iris-vddrfa-supply = <&pm8937_l19>;
+ qcom,iris-vddpa-supply = <&pm8937_l9>;
+ qcom,iris-vdddig-supply = <&pm8937_l5>;
+
+ qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
+ qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
+ qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
+ qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
+
+ qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddpx-voltage-level = <1800000 0 1800000>;
+
+ qcom,iris-vddxo-current = <10000>;
+ qcom,iris-vddrfa-current = <100000>;
+ qcom,iris-vddpa-current = <515000>;
+ qcom,iris-vdddig-current = <10000>;
+
+ qcom,pronto-vddmx-current = <0>;
+ qcom,pronto-vddcx-current = <0>;
+ qcom,pronto-vddpx-current = <0>;
+
+ pinctrl-names = "wcnss_default", "wcnss_sleep",
+ "wcnss_gpio_default";
+ pinctrl-0 = <&wcnss_default>;
+ pinctrl-1 = <&wcnss_sleep>;
+ pinctrl-2 = <&wcnss_gpio_default>;
+
+ gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>,
+ <&tlmm 79 0>, <&tlmm 80 0>;
+
+ clocks = <&clock_gcc clk_xo_wlan_clk>,
+ <&clock_gcc clk_rf_clk2>,
+ <&clock_debug clk_gcc_debug_mux_8937>,
+ <&clock_gcc clk_wcnss_m_clk>;
+
+ clock-names = "xo", "rf_clk", "measure", "wcnss_debug";
+
+ qcom,has-autodetect-xo;
+ qcom,is-pronto-v3;
+ qcom,has-pronto-hw;
+ qcom,has-vsys-adc-channel;
+ qcom,wcnss-adc_tm = <&pm8937_adc_tm>;
+ };
};
#include "pm8937-rpm-regulator.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi
index 9ef154a..d22101f 100644
--- a/arch/arm64/boot/dts/qcom/msm8937.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi
@@ -423,6 +423,7 @@
<0x00a6018 0x00004>;
reg-names = "cc_base", "apcs_c1_base",
"apcs_c0_base", "efuse";
+ qcom,gfx3d_clk_src-opp-store-vcorner = <&msm_gpu>;
vdd_dig-supply = <&pm8937_s2_level>;
vdd_sr2_dig-supply = <&pm8937_s2_level_ao>;
vdd_sr2_pll-supply = <&pm8937_l7_ao>;
diff --git a/arch/arm64/boot/dts/qcom/qcs605.dtsi b/arch/arm64/boot/dts/qcom/qcs605.dtsi
index 1e1d82c..be88a5d 100644
--- a/arch/arm64/boot/dts/qcom/qcs605.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs605.dtsi
@@ -66,6 +66,10 @@
status = "disabled";
};
+&dump_mem {
+ size = <0 0x800000>;
+};
+
&soc {
qcom,rmnet-ipa {
status = "disabled";
@@ -76,6 +80,12 @@
status = "disabled";
};
+&mem_dump {
+ rpmh {
+ qcom,dump-size = <0x400000>;
+ };
+};
+
&thermal_zones {
lmh-dcvs-00 {
trips {
diff --git a/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
index 09077c42..cefc078 100644
--- a/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm632-qrd.dtsi
@@ -12,3 +12,9 @@
*/
#include "sdm450-qrd-sku4.dtsi"
+
+&ssphy {
+ fpc-redrive-supply = <&pm8953_l6>;
+ qcom,redrive-voltage-level = <0 1800000 1900000>;
+ qcom,redrive-load = <105000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm632-rcm.dts b/arch/arm64/boot/dts/qcom/sdm632-rcm.dts
index 68f0ea0..fe7ab38 100644
--- a/arch/arm64/boot/dts/qcom/sdm632-rcm.dts
+++ b/arch/arm64/boot/dts/qcom/sdm632-rcm.dts
@@ -24,3 +24,32 @@
qcom,pmic-id = <0x010016 0x010011 0x0 0x0>;
};
+&soc {
+ gpio_keys {
+ /delete-node/home;
+ };
+};
+
+&tlmm {
+ tlmm_gpio_key {
+ gpio_key_active: gpio_key_active {
+ mux {
+ pins = "gpio85", "gpio86", "gpio87";
+ };
+
+ config {
+ pins = "gpio85", "gpio86", "gpio87";
+ };
+ };
+
+ gpio_key_suspend: gpio_key_suspend {
+ mux {
+ pins = "gpio85", "gpio86", "gpio87";
+ };
+
+ config {
+ pins = "gpio85", "gpio86", "gpio87";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm632-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdm632-regulator.dtsi
index b5373a2..a7580e0 100644
--- a/arch/arm64/boot/dts/qcom/sdm632-regulator.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm632-regulator.dtsi
@@ -143,10 +143,10 @@
regulator-min-microvolt = <1>;
regulator-max-microvolt = <7>;
- qcom,cpr-fuse-corners = <5>;
+ qcom,cpr-fuse-corners = <4>;
qcom,cpr-fuse-combos = <64>;
qcom,cpr-corners = <7>;
- qcom,cpr-corner-fmax-map = <1 2 3 4 7>;
+ qcom,cpr-corner-fmax-map = <1 3 4 7>;
qcom,cpr-voltage-ceiling =
<720000 790000 865000 865000 920000
@@ -171,8 +171,6 @@
<3600 3600 3830 2430 2520 2700 1790 1760
1970 1880 2110 2010 2510 4900 4370 4780>,
<3600 3600 3830 2430 2520 2700 1790 1760
- 1970 1880 2110 2010 2510 4900 4370 4780>,
- <3600 3600 3830 2430 2520 2700 1790 1760
1970 1880 2110 2010 2510 4900 4370 4780>;
qcom,allow-voltage-interpolation;
@@ -191,24 +189,27 @@
apc1_perfcl_vreg: regulator {
regulator-name = "apc1_perfcl_corner";
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <5>;
+ regulator-max-microvolt = <7>;
- qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-fuse-corners = <4>;
qcom,cpr-fuse-combos = <64>;
- qcom,cpr-corners = <5>;
- qcom,cpr-corner-fmax-map = <1 2 5>;
+ qcom,cpr-corners = <7>;
+ qcom,cpr-corner-fmax-map = <1 3 4 7>;
qcom,cpr-voltage-ceiling =
- <865000 865000 920000 990000 1065000>;
+ <720000 790000 865000 865000 920000
+ 990000 1065000>;
qcom,cpr-voltage-floor =
- <500000 500000 500000 500000 500000>;
+ <500000 500000 500000 500000 500000
+ 500000 500000>;
- qcom,mem-acc-voltage = <2 2 2 2 3>;
+ qcom,mem-acc-voltage = <1 1 2 2 2 2 3>;
qcom,corner-frequencies =
- <1094400000 1401600000 1555200000
- 1804800000 2016000000>;
+ <633600000 902400000 1094400000
+ 1401600000 1555200000 1804800000
+ 2016000000>;
qcom,cpr-ro-scaling-factor =
<3600 3600 3830 2430 2520 2700 1790 1760
@@ -216,11 +217,175 @@
<3600 3600 3830 2430 2520 2700 1790 1760
1970 1880 2110 2010 2510 4900 4370 4780>,
<3600 3600 3830 2430 2520 2700 1790 1760
+ 1970 1880 2110 2010 2510 4900 4370 4780>,
+ <3600 3600 3830 2430 2520 2700 1790 1760
1970 1880 2110 2010 2510 4900 4370 4780>;
qcom,allow-voltage-interpolation;
qcom,allow-quotient-interpolation;
qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+
+ qcom,cpr-open-loop-voltage-fuse-adjustment =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 1; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 2; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 3; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 4; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 5; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 6; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 7; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ qcom,cpr-closed-loop-voltage-fuse-adjustment =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 1; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 2; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 3; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 4; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 5; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 6; CPR rev 0..7 */
+ < 30000 0 0 0>,
+ < 30000 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+
+ /* Speed bin 7; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm632.dtsi b/arch/arm64/boot/dts/qcom/sdm632.dtsi
index 69cb36f..b54e831 100644
--- a/arch/arm64/boot/dts/qcom/sdm632.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm632.dtsi
@@ -824,10 +824,12 @@
< 1804800000 7>;
qcom,speed0-bin-v0-c1 =
< 0 0>,
- < 1094400000 1>,
- < 1401600000 2>,
- < 1555200000 3>,
- < 1804800000 4>;
+ < 633600000 1>,
+ < 902400000 2>,
+ < 1094400000 3>,
+ < 1401600000 4>,
+ < 1555200000 5>,
+ < 1804800000 6>;
qcom,speed0-bin-v0-cci =
< 0 0>,
< 307200000 1>,
@@ -848,10 +850,12 @@
< 1804800000 7>;
qcom,speed6-bin-v0-c1 =
< 0 0>,
- < 1094400000 1>,
- < 1401600000 2>,
- < 1555200000 3>,
- < 1804800000 4>;
+ < 633600000 1>,
+ < 902400000 2>,
+ < 1094400000 3>,
+ < 1401600000 4>,
+ < 1555200000 5>,
+ < 1804800000 6>;
qcom,speed6-bin-v0-cci =
< 0 0>,
< 307200000 1>,
@@ -872,11 +876,13 @@
< 1804800000 7>;
qcom,speed2-bin-v0-c1 =
< 0 0>,
- < 1094400000 1>,
- < 1401600000 2>,
- < 1555200000 3>,
- < 1804800000 4>,
- < 2016000000 5>;
+ < 633600000 1>,
+ < 902400000 2>,
+ < 1094400000 3>,
+ < 1401600000 4>,
+ < 1555200000 5>,
+ < 1804800000 6>,
+ < 2016000000 7>;
qcom,speed2-bin-v0-cci =
< 0 0>,
< 307200000 1>,
@@ -914,6 +920,8 @@
< 1804800 >;
qcom,cpufreq-table-4 =
+ < 633600 >,
+ < 902400 >,
< 1094400 >,
< 1401600 >,
< 1555200 >,
@@ -961,6 +969,8 @@
< 1536000 768000>, /* NOM+ */
< 1670400 787200>; /* TURBO */
cpu-to-dev-map-4 =
+ < 633600 307200>, /* SVS */
+ < 902400 403200>,
< 1094400 499200>, /* SVS */
< 1401600 691200>, /* NOM */
< 1555200 768000>, /* NOM+ */
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 3ca33b2..4b39207 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1096,7 +1096,7 @@
clock_debug: qcom,cc-debug {
compatible = "qcom,debugcc-sdm845";
- qcom,cc-count = <5>;
+ qcom,cc-count = <6>;
qcom,gcc = <&clock_gcc>;
qcom,videocc = <&clock_videocc>;
qcom,camcc = <&clock_camcc>;
@@ -1389,7 +1389,7 @@
};
};
- mem_dump {
+ mem_dump: mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 22b4b90..e9a913f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1276,7 +1276,7 @@
clock_debug: qcom,cc-debug@100000 {
compatible = "qcom,debugcc-sdm845";
- qcom,cc-count = <5>;
+ qcom,cc-count = <6>;
qcom,gcc = <&clock_gcc>;
qcom,videocc = <&clock_videocc>;
qcom,camcc = <&clock_camcc>;
diff --git a/drivers/char/diag/diagfwd_mhi.c b/drivers/char/diag/diagfwd_mhi.c
index f8c3fde..6f41868 100644
--- a/drivers/char/diag/diagfwd_mhi.c
+++ b/drivers/char/diag/diagfwd_mhi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -434,9 +434,10 @@
do {
if (!(atomic_read(&(read_ch->opened))))
break;
-
+ spin_lock_irqsave(&read_ch->lock, flags);
buf = diagmem_alloc(driver, DIAG_MDM_BUF_SIZE,
mhi_info->mempool);
+ spin_unlock_irqrestore(&read_ch->lock, flags);
if (!buf)
break;
@@ -743,4 +744,3 @@
diagmem_exit(driver, mhi_info->mempool);
}
}
-
diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h
index f7e9eb3..614b1c7 100644
--- a/drivers/gpu/msm/adreno-gpulist.h
+++ b/drivers/gpu/msm/adreno-gpulist.h
@@ -207,9 +207,11 @@
.major = 0,
.minor = 4,
.patchid = ANY_ID,
- .features = ADRENO_PREEMPTION | ADRENO_64BIT,
+ .features = ADRENO_PREEMPTION | ADRENO_64BIT |
+ ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
.pm4fw_name = "a530_pm4.fw",
.pfpfw_name = "a530_pfp.fw",
+ .zap_name = "a506_zap",
.gpudev = &adreno_a5xx_gpudev,
.gmem_size = (SZ_128K + SZ_8K),
.num_protected_regs = 0x20,
@@ -221,9 +223,11 @@
.major = 0,
.minor = 5,
.patchid = ANY_ID,
- .features = ADRENO_PREEMPTION | ADRENO_64BIT,
+ .features = ADRENO_PREEMPTION | ADRENO_64BIT |
+ ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
.pm4fw_name = "a530_pm4.fw",
.pfpfw_name = "a530_pfp.fw",
+ .zap_name = "a506_zap",
.gpudev = &adreno_a5xx_gpudev,
.gmem_size = (SZ_128K + SZ_8K),
.num_protected_regs = 0x20,
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c
index 7ddb6fe..876b7c9 100644
--- a/drivers/gpu/msm/adreno_a5xx.c
+++ b/drivers/gpu/msm/adreno_a5xx.c
@@ -2226,6 +2226,13 @@
upper_32_bits(gpuaddr));
/*
+ * Do not invoke to load zap shader if MMU does
+ * not support secure mode.
+ */
+ if (!device->mmu.secured)
+ return 0;
+
+ /*
* Resume call to write the zap shader base address into the
* appropriate register,
* skip if retention is supported for the CPZ register
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index f2c18b7..37330cb 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -853,6 +853,13 @@
kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI,
upper_32_bits(gpuaddr));
+ /*
+ * Do not invoke to load zap shader if MMU does
+ * not support secure mode.
+ */
+ if (!device->mmu.secured)
+ return 0;
+
/* Load the zap shader firmware through PIL if its available */
if (adreno_dev->gpucore->zap_name && !adreno_dev->zap_loaded) {
/*
diff --git a/drivers/hwmon/qpnp-adc-common.c b/drivers/hwmon/qpnp-adc-common.c
index f396c76..b900f76 100644
--- a/drivers/hwmon/qpnp-adc-common.c
+++ b/drivers/hwmon/qpnp-adc-common.c
@@ -2495,6 +2495,12 @@
}
}
+ if (of_device_is_compatible(node, "qcom,qpnp-adc-hc-pm5") ||
+ of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc-pm5"))
+ adc_prop->is_pmic_5 = true;
+ else
+ adc_prop->is_pmic_5 = false;
+
for_each_child_of_node(node, child) {
int channel_num, scaling = 0, post_scaling = 0;
int fast_avg_setup, calib_type = 0, rc, hw_settle_time = 0;
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index ed5222e..7e6af65 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -35,8 +35,6 @@
#include <linux/power_supply.h>
#include <linux/thermal.h>
-#define QPNP_VADC_HC_VREF_CODE 0x4000
-
/* QPNP VADC register definition */
#define QPNP_VADC_REVISION1 0x0
#define QPNP_VADC_REVISION2 0x1
@@ -508,7 +506,7 @@
goto fail_unlock;
}
- if (vadc->adc->adc_prop->full_scale_code == QPNP_VADC_HC_VREF_CODE) {
+ if (!vadc->adc->adc_prop->is_pmic_5) {
if (!vadc->vadc_init_calib) {
rc = qpnp_vadc_calib_device(vadc);
if (rc) {
@@ -2595,6 +2593,8 @@
},
{ .compatible = "qcom,qpnp-vadc-hc",
},
+ { .compatible = "qcom,qpnp-adc-hc-pm5",
+ },
{}
};
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index e0b2f63..1719336 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -579,6 +579,7 @@
{ ARM_SMMU_OPT_MMU500_ERRATA1, "qcom,mmu500-errata-1" },
{ ARM_SMMU_OPT_STATIC_CB, "qcom,enable-static-cb"},
{ ARM_SMMU_OPT_HALT, "qcom,enable-smmu-halt"},
+ { ARM_SMMU_OPT_HIBERNATION, "qcom,hibernation-support"},
{ 0, NULL},
};
@@ -704,6 +705,11 @@
mutex_unlock(&smmu_domain->assign_lock);
}
+static bool arm_smmu_opt_hibernation(struct arm_smmu_device *smmu)
+{
+ return smmu->options & ARM_SMMU_OPT_HIBERNATION;
+}
+
/*
* init()
* Hook for additional device tree parsing at probe time.
@@ -1859,6 +1865,14 @@
goto out_unlock;
}
+ if (arm_smmu_has_secure_vmid(smmu_domain) &&
+ arm_smmu_opt_hibernation(smmu)) {
+ dev_err(smmu->dev,
+ "Secure usecases not supported with hibernation\n");
+ ret = -EPERM;
+ goto out_unlock;
+ }
+
/*
* Mapping the requested stage onto what we support is surprisingly
* complicated, mainly because the spec allows S1+S2 SMMUs without
@@ -3994,6 +4008,33 @@
return cb;
}
+static void parse_static_cb_cfg(struct arm_smmu_device *smmu)
+{
+ u32 idx = 0;
+ u32 val;
+ int ret;
+
+ if (!(arm_smmu_is_static_cb(smmu) &&
+ arm_smmu_opt_hibernation(smmu)))
+ return;
+
+ /*
+ * Context banks may be xpu-protected. Require a devicetree property to
+ * indicate which context banks HLOS has access to.
+ */
+ bitmap_set(smmu->secure_context_map, 0, ARM_SMMU_MAX_CBS);
+ while (idx < ARM_SMMU_MAX_CBS) {
+ ret = of_property_read_u32_index(
+ smmu->dev->of_node, "qcom,static-ns-cbs",
+ idx++, &val);
+ if (ret)
+ break;
+
+ bitmap_clear(smmu->secure_context_map, val, 1);
+ dev_dbg(smmu->dev, "Detected NS context bank: %d\n", idx);
+ }
+}
+
static int arm_smmu_handoff_cbs(struct arm_smmu_device *smmu)
{
u32 i, raw_smr, raw_s2cr;
@@ -4693,6 +4734,7 @@
}
parse_driver_options(smmu);
+ parse_static_cb_cfg(smmu);
smmu->pwr = arm_smmu_init_power_resources(pdev);
if (IS_ERR(smmu->pwr))
@@ -4799,8 +4841,9 @@
if (arm_smmu_power_on(smmu->pwr))
return -EINVAL;
- if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS) ||
- !bitmap_empty(smmu->secure_context_map, ARM_SMMU_MAX_CBS))
+ if (!(bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS) &&
+ (bitmap_empty(smmu->secure_context_map, ARM_SMMU_MAX_CBS) ||
+ arm_smmu_opt_hibernation(smmu))))
dev_err(&pdev->dev, "removing device with active domains!\n");
idr_destroy(&smmu->asid_idr);
@@ -4814,10 +4857,43 @@
return 0;
}
+static int arm_smmu_pm_freeze(struct device *dev)
+{
+ struct arm_smmu_device *smmu = dev_get_drvdata(dev);
+
+ if (!arm_smmu_opt_hibernation(smmu)) {
+ dev_err(smmu->dev, "Aborting: Hibernation not supported\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int arm_smmu_pm_restore(struct device *dev)
+{
+ struct arm_smmu_device *smmu = dev_get_drvdata(dev);
+ int ret;
+
+ ret = arm_smmu_power_on(smmu->pwr);
+ if (ret)
+ return ret;
+
+ arm_smmu_device_reset(smmu);
+ arm_smmu_power_off(smmu->pwr);
+ return 0;
+}
+
+static const struct dev_pm_ops arm_smmu_pm_ops = {
+#ifdef CONFIG_PM_SLEEP
+ .freeze = arm_smmu_pm_freeze,
+ .restore = arm_smmu_pm_restore,
+#endif
+};
+
static struct platform_driver arm_smmu_driver = {
.driver = {
.name = "arm-smmu",
.of_match_table = of_match_ptr(arm_smmu_of_match),
+ .pm = &arm_smmu_pm_ops,
},
.probe = arm_smmu_device_dt_probe,
.remove = arm_smmu_device_remove,
@@ -4828,6 +4904,7 @@
{
static bool registered;
int ret = 0;
+ struct device_node *node;
ktime_t cur;
if (registered)
@@ -4839,9 +4916,12 @@
return ret;
ret = platform_driver_register(&arm_smmu_driver);
-#ifdef CONFIG_MSM_TZ_SMMU
- ret = register_iommu_sec_ptbl();
-#endif
+ /* Disable secure usecases if hibernation support is enabled */
+ node = of_find_compatible_node(NULL, NULL, "qcom,qsmmu-v500");
+ if (IS_ENABLED(CONFIG_MSM_TZ_SMMU) && node &&
+ !of_find_property(node, "qcom,hibernation-support", NULL))
+ ret = register_iommu_sec_ptbl();
+
registered = !ret;
trace_smmu_init(ktime_us_delta(ktime_get(), cur));
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index c0143db..2b31ed3 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -4510,6 +4510,7 @@
strlcpy(entry->app_name, app_name, MAX_APP_NAME_SIZE);
if (__qseecom_get_fw_size(app_name, &fw_size, &app_arch)) {
ret = -EIO;
+ kfree(entry);
goto exit_entry_free;
}
entry->app_arch = app_arch;
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index cec5a96..cc68136 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -6301,7 +6301,7 @@
return ret;
}
-static void msm_pcie_fixup_suspend(struct pci_dev *dev)
+static void msm_pcie_fixup_suspend_late(struct pci_dev *dev)
{
int ret;
struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus);
@@ -6334,8 +6334,8 @@
mutex_unlock(&pcie_dev->recovery_lock);
}
-DECLARE_PCI_FIXUP_SUSPEND(PCIE_VENDOR_ID_QCOM, PCI_ANY_ID,
- msm_pcie_fixup_suspend);
+DECLARE_PCI_FIXUP_SUSPEND_LATE(PCIE_VENDOR_ID_QCOM, PCI_ANY_ID,
+ msm_pcie_fixup_suspend_late);
/* Resume the PCIe link */
static int msm_pcie_pm_resume(struct pci_dev *dev,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index af926fb..9eb3c35 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -4718,12 +4718,12 @@
ipa3_ctx->ipa_initialization_complete = true;
mutex_unlock(&ipa3_ctx->lock);
+ ipa3_debugfs_init();
+
ipa3_trigger_ipa_ready_cbs();
complete_all(&ipa3_ctx->init_completion_obj);
pr_info("IPA driver initialization was successful.\n");
- ipa3_debugfs_init();
-
return 0;
fail_teth_bridge_driver_init:
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index 7ba0ce5..eaf138c 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -2080,12 +2080,21 @@
static int fg_adjust_recharge_soc(struct fg_chip *chip)
{
+ union power_supply_propval prop = {0, };
int rc, msoc, recharge_soc, new_recharge_soc = 0;
bool recharge_soc_status;
if (!chip->dt.auto_recharge_soc)
return 0;
+ rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_HEALTH,
+ &prop);
+ if (rc < 0) {
+ pr_err("Error in getting battery health, rc=%d\n", rc);
+ return rc;
+ }
+ chip->health = prop.intval;
+
recharge_soc = chip->dt.recharge_soc_thr;
recharge_soc_status = chip->recharge_soc_adjusted;
/*
@@ -2116,6 +2125,9 @@
if (!chip->recharge_soc_adjusted)
return 0;
+ if (chip->health != POWER_SUPPLY_HEALTH_GOOD)
+ return 0;
+
/* Restore the default value */
new_recharge_soc = recharge_soc;
chip->recharge_soc_adjusted = false;
diff --git a/drivers/regulator/cpr4-apss-regulator.c b/drivers/regulator/cpr4-apss-regulator.c
index d5a0e33..725fc58 100644
--- a/drivers/regulator/cpr4-apss-regulator.c
+++ b/drivers/regulator/cpr4-apss-regulator.c
@@ -36,8 +36,8 @@
#include "cpr3-regulator.h"
#define MSM8953_APSS_FUSE_CORNERS 4
-#define SDM632_POWER_APSS_FUSE_CORNERS 5
-#define SDM632_PERF_APSS_FUSE_CORNERS 3
+#define SDM632_POWER_APSS_FUSE_CORNERS 4
+#define SDM632_PERF_APSS_FUSE_CORNERS 4
/**
* struct cpr4_apss_fuses - APSS specific fuse data
@@ -103,27 +103,27 @@
enum cpr4_sdm632_power_apss_fuse_corner {
CPR4_SDM632_POWER_APSS_FUSE_CORNER_LOWSVS = 0,
- CPR4_SDM632_POWER_APSS_FUSE_CORNER_SVS = 1,
- CPR4_SDM632_POWER_APSS_FUSE_CORNER_SVS_L1 = 2,
- CPR4_SDM632_POWER_APSS_FUSE_CORNER_NOM = 3,
- CPR4_SDM632_POWER_APSS_FUSE_CORNER_TURBO_L1 = 4,
+ CPR4_SDM632_POWER_APSS_FUSE_CORNER_SVS_L1 = 1,
+ CPR4_SDM632_POWER_APSS_FUSE_CORNER_NOM = 2,
+ CPR4_SDM632_POWER_APSS_FUSE_CORNER_TURBO_L1 = 3,
};
static const char * const cpr4_sdm632_power_apss_fuse_corner_name[] = {
[CPR4_SDM632_POWER_APSS_FUSE_CORNER_LOWSVS] = "LowSVS",
- [CPR4_SDM632_POWER_APSS_FUSE_CORNER_SVS] = "SVS",
[CPR4_SDM632_POWER_APSS_FUSE_CORNER_SVS_L1] = "SVS_L1",
[CPR4_SDM632_POWER_APSS_FUSE_CORNER_NOM] = "NOM",
[CPR4_SDM632_POWER_APSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1",
};
enum cpr4_sdm632_perf_apss_fuse_corner {
- CPR4_SDM632_PERF_APSS_FUSE_CORNER_SVS_L1 = 0,
- CPR4_SDM632_PERF_APSS_FUSE_CORNER_NOM = 1,
- CPR4_SDM632_PERF_APSS_FUSE_CORNER_TURBO_L1 = 2,
+ CPR4_SDM632_PERF_APSS_FUSE_CORNER_LOWSVS = 0,
+ CPR4_SDM632_PERF_APSS_FUSE_CORNER_SVS_L1 = 1,
+ CPR4_SDM632_PERF_APSS_FUSE_CORNER_NOM = 2,
+ CPR4_SDM632_PERF_APSS_FUSE_CORNER_TURBO_L1 = 3,
};
static const char * const cpr4_sdm632_perf_apss_fuse_corner_name[] = {
+ [CPR4_SDM632_PERF_APSS_FUSE_CORNER_LOWSVS] = "LowSVS",
[CPR4_SDM632_PERF_APSS_FUSE_CORNER_SVS_L1] = "SVS_L1",
[CPR4_SDM632_PERF_APSS_FUSE_CORNER_NOM] = "NOM",
[CPR4_SDM632_PERF_APSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1",
@@ -229,12 +229,12 @@
sdm632_apss_ro_sel_param[2][SDM632_POWER_APSS_FUSE_CORNERS][2] = {
[CPR4_APSS_POWER_CLUSTER_ID] = {
{{73, 28, 31}, {} },
- {{73, 24, 27}, {} },
{{73, 20, 23}, {} },
{{73, 16, 19}, {} },
{{73, 12, 15}, {} },
},
[CPR4_APSS_PERF_CLUSTER_ID] = {
+ {{73, 28, 31}, {} },
{{73, 8, 11}, {} },
{{73, 4, 7}, {} },
{{73, 0, 3}, {} },
@@ -245,12 +245,12 @@
sdm632_apss_init_voltage_param[2][SDM632_POWER_APSS_FUSE_CORNERS][2] = {
[CPR4_APSS_POWER_CLUSTER_ID] = {
{{74, 18, 23}, {} },
- {{74, 12, 17}, {} },
{{71, 24, 29}, {} },
{{74, 6, 11}, {} },
{{74, 0, 5}, {} },
},
[CPR4_APSS_PERF_CLUSTER_ID] = {
+ {{74, 18, 23}, {} },
{{71, 18, 23}, {} },
{{71, 12, 17}, {} },
{{71, 6, 11}, {} },
@@ -261,12 +261,12 @@
sdm632_apss_target_quot_param[2][SDM632_POWER_APSS_FUSE_CORNERS][2] = {
[CPR4_APSS_POWER_CLUSTER_ID] = {
{{75, 44, 55}, {} },
- {{75, 32, 43}, {} },
{{72, 44, 55}, {} },
{{75, 20, 31}, {} },
{{75, 8, 19}, {} },
},
[CPR4_APSS_PERF_CLUSTER_ID] = {
+ {{75, 44, 55}, {} },
{{72, 32, 43}, {} },
{{72, 20, 31}, {} },
{{72, 8, 19}, {} },
@@ -277,13 +277,13 @@
sdm632_apss_quot_offset_param[2][SDM632_POWER_APSS_FUSE_CORNERS][2] = {
[CPR4_APSS_POWER_CLUSTER_ID] = {
{{} },
- {{74, 39, 45}, {} },
{{71, 46, 52}, {} },
{{74, 32, 38}, {} },
{{74, 24, 30}, {} },
},
[CPR4_APSS_PERF_CLUSTER_ID] = {
{{} },
+ {{74, 39, 45}, {} },
{{71, 39, 45}, {} },
{{71, 32, 38}, {} },
},
@@ -322,12 +322,12 @@
sdm632_apss_fuse_ref_volt[2][SDM632_POWER_APSS_FUSE_CORNERS] = {
[CPR4_APSS_POWER_CLUSTER_ID] = {
645000,
- 720000,
790000,
865000,
1065000,
},
[CPR4_APSS_PERF_CLUSTER_ID] = {
+ 645000,
790000,
865000,
1065000,
@@ -1025,7 +1025,7 @@
} else {
corner_name = cpr4_sdm632_perf_apss_fuse_corner_name;
lowest_fuse_corner =
- CPR4_SDM632_PERF_APSS_FUSE_CORNER_SVS_L1;
+ CPR4_SDM632_PERF_APSS_FUSE_CORNER_LOWSVS;
highest_fuse_corner =
CPR4_SDM632_PERF_APSS_FUSE_CORNER_TURBO_L1;
}
diff --git a/drivers/thermal/qpnp-adc-tm.c b/drivers/thermal/qpnp-adc-tm.c
index 5c0022e..5d345cc 100644
--- a/drivers/thermal/qpnp-adc-tm.c
+++ b/drivers/thermal/qpnp-adc-tm.c
@@ -191,6 +191,8 @@
#define QPNP_BTM_MEAS_INTERVAL_CTL 0x50
#define QPNP_BTM_MEAS_INTERVAL_CTL2 0x51
+#define QPNP_BTM_MEAS_INTERVAL_CTL_PM5 0x44
+#define QPNP_BTM_MEAS_INTERVAL_CTL2_PM5 0x45
#define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
@@ -742,6 +744,7 @@
bool chan_found = false;
u8 meas_interval_timer2 = 0, timer_interval_store = 0;
uint32_t btm_chan_idx = 0;
+ bool is_pmic_5 = chip->adc->adc_prop->is_pmic_5;
while (i < chip->max_channels_available) {
if (chip->sensor[i].btm_channel_num == btm_chan) {
@@ -763,10 +766,18 @@
rc = qpnp_adc_tm_write_reg(chip,
QPNP_ADC_TM_MEAS_INTERVAL_CTL,
chip->sensor[chan_idx].meas_interval, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_MEAS_INTERVAL_CTL,
- chip->sensor[chan_idx].meas_interval, 1);
+ else {
+ if (!is_pmic_5)
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL,
+ chip->sensor[chan_idx].meas_interval,
+ 1);
+ else
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL_PM5,
+ chip->sensor[chan_idx].meas_interval,
+ 1);
+ }
if (rc < 0) {
pr_err("timer1 configure failed\n");
return rc;
@@ -778,10 +789,16 @@
rc = qpnp_adc_tm_read_reg(chip,
QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
&meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_read_reg(chip,
+ else {
+ if (!is_pmic_5)
+ rc = qpnp_adc_tm_read_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL2,
&meas_interval_timer2, 1);
+ else
+ rc = qpnp_adc_tm_read_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
+ &meas_interval_timer2, 1);
+ }
if (rc < 0) {
pr_err("timer2 configure read failed\n");
return rc;
@@ -794,10 +811,16 @@
rc = qpnp_adc_tm_write_reg(chip,
QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_MEAS_INTERVAL_CTL2,
- meas_interval_timer2, 1);
+ else {
+ if (!is_pmic_5)
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2,
+ meas_interval_timer2, 1);
+ else
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
+ meas_interval_timer2, 1);
+ }
if (rc < 0) {
pr_err("timer2 configure failed\n");
return rc;
@@ -808,10 +831,16 @@
rc = qpnp_adc_tm_read_reg(chip,
QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
&meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_read_reg(chip,
- QPNP_BTM_MEAS_INTERVAL_CTL2,
- &meas_interval_timer2, 1);
+ else {
+ if (!is_pmic_5)
+ rc = qpnp_adc_tm_read_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2,
+ &meas_interval_timer2, 1);
+ else
+ rc = qpnp_adc_tm_read_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
+ &meas_interval_timer2, 1);
+ }
if (rc < 0) {
pr_err("timer3 read failed\n");
return rc;
@@ -823,10 +852,16 @@
rc = qpnp_adc_tm_write_reg(chip,
QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_MEAS_INTERVAL_CTL2,
- meas_interval_timer2, 1);
+ else {
+ if (!is_pmic_5)
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2,
+ meas_interval_timer2, 1);
+ else
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
+ meas_interval_timer2, 1);
+ }
if (rc < 0) {
pr_err("timer3 configure failed\n");
return rc;
@@ -2997,6 +3032,7 @@
static const struct of_device_id qpnp_adc_tm_match_table[] = {
{ .compatible = "qcom,qpnp-adc-tm" },
{ .compatible = "qcom,qpnp-adc-tm-hc" },
+ { .compatible = "qcom,qpnp-adc-tm-hc-pm5" },
{}
};
diff --git a/drivers/usb/gadget/function/f_qdss.c b/drivers/usb/gadget/function/f_qdss.c
index d1c3741..0ce2c407 100644
--- a/drivers/usb/gadget/function/f_qdss.c
+++ b/drivers/usb/gadget/function/f_qdss.c
@@ -1,7 +1,7 @@
/*
* f_qdss.c -- QDSS function Driver
*
- * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -117,6 +117,39 @@
.wBytesPerInterval = 0,
};
+/* Full speed support */
+static struct usb_endpoint_descriptor qdss_fs_data_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor qdss_fs_ctrl_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor qdss_fs_ctrl_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_descriptor_header *qdss_fs_desc[] = {
+ (struct usb_descriptor_header *) &qdss_data_intf_desc,
+ (struct usb_descriptor_header *) &qdss_fs_data_desc,
+ (struct usb_descriptor_header *) &qdss_ctrl_intf_desc,
+ (struct usb_descriptor_header *) &qdss_fs_ctrl_in_desc,
+ (struct usb_descriptor_header *) &qdss_fs_ctrl_out_desc,
+ NULL,
+};
static struct usb_descriptor_header *qdss_hs_desc[] = {
(struct usb_descriptor_header *) &qdss_data_intf_desc,
(struct usb_descriptor_header *) &qdss_hs_data_desc,
@@ -138,6 +171,11 @@
NULL,
};
+static struct usb_descriptor_header *qdss_fs_data_only_desc[] = {
+ (struct usb_descriptor_header *) &qdss_data_intf_desc,
+ (struct usb_descriptor_header *) &qdss_fs_data_desc,
+ NULL,
+};
static struct usb_descriptor_header *qdss_hs_data_only_desc[] = {
(struct usb_descriptor_header *) &qdss_data_intf_desc,
(struct usb_descriptor_header *) &qdss_hs_data_desc,
@@ -367,6 +405,9 @@
if (gadget_is_dualspeed(gadget) && f->hs_descriptors)
usb_free_descriptors(f->hs_descriptors);
+
+ if (f->fs_descriptors)
+ usb_free_descriptors(f->fs_descriptors);
}
static int qdss_bind(struct usb_configuration *c, struct usb_function *f)
@@ -378,11 +419,6 @@
pr_debug("qdss_bind\n");
- if (!gadget_is_dualspeed(gadget) && !gadget_is_superspeed(gadget)) {
- pr_err("qdss_bind: full-speed is not supported\n");
- return -ENOTSUPP;
- }
-
/* Allocate data I/F */
iface = usb_interface_id(c, f);
if (iface < 0) {
@@ -447,6 +483,18 @@
ep->driver_data = qdss;
}
+ /*update fs descriptors*/
+ qdss_fs_data_desc.bEndpointAddress =
+ qdss_ss_data_desc.bEndpointAddress;
+ if (qdss->debug_inface_enabled) {
+ qdss_fs_ctrl_in_desc.bEndpointAddress =
+ qdss_ss_ctrl_in_desc.bEndpointAddress;
+ qdss_fs_ctrl_out_desc.bEndpointAddress =
+ qdss_ss_ctrl_out_desc.bEndpointAddress;
+ f->fs_descriptors = usb_copy_descriptors(qdss_fs_desc);
+ } else
+ f->fs_descriptors = usb_copy_descriptors(
+ qdss_fs_data_only_desc);
/*update descriptors*/
qdss_hs_data_desc.bEndpointAddress =
qdss_ss_data_desc.bEndpointAddress;
@@ -650,7 +698,7 @@
goto fail1;
}
- if (intf == qdss->data_iface_id) {
+ if (intf == qdss->data_iface_id && !qdss->data_enabled) {
/* Increment usage count on connect */
usb_gadget_autopm_get_async(qdss->gadget);
@@ -1144,7 +1192,7 @@
struct f_qdss *usb_qdss = opts->usb_qdss;
usb_qdss->port.function.name = "usb_qdss";
- usb_qdss->port.function.fs_descriptors = qdss_hs_desc;
+ usb_qdss->port.function.fs_descriptors = qdss_fs_desc;
usb_qdss->port.function.hs_descriptors = qdss_hs_desc;
usb_qdss->port.function.strings = qdss_strings;
usb_qdss->port.function.bind = qdss_bind;
diff --git a/include/crypto/ice.h b/include/crypto/ice.h
index b02a440..133041e 100644
--- a/include/crypto/ice.h
+++ b/include/crypto/ice.h
@@ -53,16 +53,22 @@
struct qcom_ice_variant_ops *qcom_ice_get_variant_ops(struct device_node *node);
struct platform_device *qcom_ice_get_pdevice(struct device_node *node);
-void qcom_ice_set_fde_flag(int flag);
-int qcom_ice_set_fde_conf(sector_t strt, sector_t size, int idx, int mode);
#ifdef CONFIG_CRYPTO_DEV_QCOM_ICE
int qcom_ice_setup_ice_hw(const char *storage_type, int enable);
+void qcom_ice_set_fde_flag(int flag);
+int qcom_ice_set_fde_conf(sector_t strt, sector_t size, int idx, int mode);
#else
static inline int qcom_ice_setup_ice_hw(const char *storage_type, int enable)
{
return 0;
}
+static inline void qcom_ice_set_fde_flag(int flag) {}
+static inline int qcom_ice_set_fde_conf(sector_t strt, sector_t size, int idx,
+ int mode)
+{
+ return 0;
+}
#endif
struct qcom_ice_variant_ops {
diff --git a/include/dt-bindings/arm/arm-smmu.h b/include/dt-bindings/arm/arm-smmu.h
index 3a1dbd3..1de45a9 100644
--- a/include/dt-bindings/arm/arm-smmu.h
+++ b/include/dt-bindings/arm/arm-smmu.h
@@ -23,5 +23,6 @@
#define ARM_SMMU_OPT_MMU500_ERRATA1 (1 << 7)
#define ARM_SMMU_OPT_STATIC_CB (1 << 8)
#define ARM_SMMU_OPT_HALT (1 << 9)
+#define ARM_SMMU_OPT_HIBERNATION (1 << 10)
#endif
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index 031573d..48fe2e9 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -1065,12 +1065,14 @@
* @full_scale_code: Full scale value with intrinsic offset removed.
* @biploar: Polarity for QPNP ADC.
* @adc_hc: Represents using HC variant of the ADC controller.
+ * @is_pmic_5: To check if PMIC5 is used.
*/
struct qpnp_adc_properties {
uint32_t adc_vdd_reference;
uint32_t full_scale_code;
bool bipolar;
bool adc_hc;
+ bool is_pmic_5;
};
/**
diff --git a/kernel/exit.c b/kernel/exit.c
index 35ff283..2c2cc1a 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -765,7 +765,11 @@
* leave this task alone and wait for reboot.
*/
if (unlikely(tsk->flags & PF_EXITING)) {
+#ifdef CONFIG_PANIC_ON_RECURSIVE_FAULT
+ panic("Recursive fault!\n");
+#else
pr_alert("Fixing recursive fault but reboot is needed!\n");
+#endif
/*
* We can do this unlocked here. The futex code uses
* this flag just to verify whether the pi state
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 558be53..079d91a 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -834,6 +834,17 @@
default 0 if !BOOTPARAM_SOFTLOCKUP_PANIC
default 1 if BOOTPARAM_SOFTLOCKUP_PANIC
+config PANIC_ON_RECURSIVE_FAULT
+ bool "Panic on recursive faults during task exit"
+ help
+ Panic upon the detection of a recursive fault during task exit,
+ rather than putting the task into an uninterruptible sleep.
+ This is particularly useful for debugging system hangs in
+ scenarios where the task experiencing the fault is critical
+ for system operation, rendering the system inoperable.
+
+ Say N if unsure.
+
config DETECT_HUNG_TASK
bool "Detect Hung Tasks"
depends on DEBUG_KERNEL
diff --git a/mm/vmpressure.c b/mm/vmpressure.c
index 1306f32..e468da6 100644
--- a/mm/vmpressure.c
+++ b/mm/vmpressure.c
@@ -423,7 +423,7 @@
void vmpressure(gfp_t gfp, struct mem_cgroup *memcg, bool tree,
unsigned long scanned, unsigned long reclaimed)
{
- if (!memcg)
+ if (!memcg && tree)
vmpressure_global(gfp, scanned, reclaimed);
if (IS_ENABLED(CONFIG_MEMCG))