ARM: dts: msm: add sdhc pinctrl drive types for SDM845
SD card interface uses fixed drive strength for each
pins. This change adds more pin drive types for different
clock rates so that driver can choose specific drive
type after clock rate is changed.
Change-Id: I0ea0110f5f111830bd8dd6a43d59ce725fc496ab
Signed-off-by: Can Guo <cang@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
index 48a4a8b..6a9a0cb 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
@@ -239,9 +239,18 @@
qcom,vdd-io-voltage-level = <1808000 2960000>;
qcom,vdd-io-current-level = <200 22000>;
- pinctrl-names = "active", "sleep";
+ pinctrl-names = "active", "sleep", "ds_400KHz",
+ "ds_50MHz", "ds_100MHz", "ds_200MHz";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+ pinctrl-2 = <&sdc2_clk_ds_400KHz
+ &sdc2_cmd_ds_400KHz &sdc2_data_ds_400KHz>;
+ pinctrl-3 = <&sdc2_clk_ds_50MHz
+ &sdc2_cmd_ds_50MHz &sdc2_data_ds_50MHz>;
+ pinctrl-4 = <&sdc2_clk_ds_100MHz
+ &sdc2_cmd_ds_100MHz &sdc2_data_ds_100MHz>;
+ pinctrl-5 = <&sdc2_clk_ds_200MHz
+ &sdc2_cmd_ds_200MHz &sdc2_data_ds_200MHz>;
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
index a0207e5..5035c9f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
@@ -142,6 +142,38 @@
};
};
+ sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
@@ -158,6 +190,38 @@
};
};
+ sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
@@ -174,6 +238,38 @@
};
};
+ sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
pcie0 {
pcie0_clkreq_default: pcie0_clkreq_default {
mux {