tree 72cd8deb50053291f585000c927896eb4638cad1
parent a82b7b9c8b6a44b0f3983fb21dff90a9d18d9539
author Anson Huang <b20788@freescale.com> 1359585224 -0500
committer Shawn Guo <shawn.guo@linaro.org> 1360509947 +0800

ARM: dts: i.MX6: Add regulator delay support

For ANATOP LDOs, vddcpu, vddsoc and vddpu
have step time settings in the misc2 register, need
to add necessary step time info for these three LDOs,
then regulator driver can add necessary delay based on
these settings.

offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc

field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>