| commit | 46a57afdd70c17cf15b2077c5ea611913f80f85f | [log] [tgz] |
|---|---|---|
| author | Gabriel Fernandez <gabriel.fernandez@linaro.org> | Wed Oct 07 11:08:57 2015 +0200 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Thu Oct 08 23:52:58 2015 -0700 |
| tree | cbf4f7eb306e7a7bbb7f42b1c30820b48c5b6710 | |
| parent | fb4738629b6c06c24ba0649ece20ecec978d8694 [diff] |
drivers: clk: st: PLL rate change implementation for DVFS Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>