tree cbf4f7eb306e7a7bbb7f42b1c30820b48c5b6710
parent fb4738629b6c06c24ba0649ece20ecec978d8694
author Gabriel Fernandez <gabriel.fernandez@linaro.org> 1444208937 +0200
committer Stephen Boyd <sboyd@codeaurora.org> 1444373578 -0700

drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>