| commit | 5c78dfe87ea04b501ee000a7f03b9432ac9d008c | [log] [tgz] |
|---|---|---|
| author | Fabio Estevam <fabio.estevam@freescale.com> | Thu Jul 04 20:01:03 2013 -0300 |
| committer | Mark Brown <broonie@linaro.org> | Fri Jul 05 10:45:49 2013 +0100 |
| tree | 3e7c444077cf12eb4fa0ecebc18534979036f46f | |
| parent | 016fcab8ff46fca29375d484226ec91932aa4a07 [diff] |
ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range. Reported-by: Oskar Schirmer <oskar@scara.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> Cc: stable@vger.kernel.org