| commit | 46c06a30dfd63b1200dda2337c145e262798b9cf | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Wed Feb 20 21:16:18 2013 +0200 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Thu Feb 21 14:01:12 2013 +0100 |
| tree | 8b212acd2a74ac42b49c51a8a4aeb3898a0570ae | |
| parent | 90a72f8774b6060975f85687e9c8a60cfb68a72c [diff] |
drm/i915: Kill pipestat[] cache Caching the PIPESTAT enable bits has been deemed pointless. Just read them from the register itself. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>