tree ef66460e003ef6650aad34233365d7c82113a1c6
parent b51312bebfa4452470c2bbf179200cb7c16d82d4
author Florian Fainelli <f.fainelli@gmail.com> 1392941488 -0800
committer Florian Fainelli <f.fainelli@gmail.com> 1410976567 -0700

ARM: BCM63XX: add BCM63138 minimal Device Tree

Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:

- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)

Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>