tree eeabe668aba9b404d9a0a383ba3461e748a9e1a2
parent b2a3c5be4d6df3b04781f430c2201cbbc9900f66
author James Hogan <james.hogan@imgtec.com> 1453460306 +0000
committer Ralf Baechle <ralf@linux-mips.org> 1462788003 +0200

MIPS: I6400: Icache fills from dcache

Coherence Manager 3 (CM3) as present in I6400 can fill icache lines
effectively from dirty dcaches, so there is no need to flush dirty lines
from dcaches through to L2 prior to icache invalidation.

Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc
evaluates to true, which avoids those dcache flushes.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>