Merge "Perf: arm64: Add additional CPUHP state for perf events"
diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt
index b29a11f..327a7d4 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm.txt
@@ -166,6 +166,8 @@
- VR device:
compatible = "qcom,qvr"
+- HDK device:
+ compatible = "qcom,hdk"
Boards (SoC type + board variant):
@@ -279,6 +281,7 @@
compatible = "qcom,sda845-cdp"
compatible = "qcom,sda845-mtp"
compatible = "qcom,sda845-qrd"
+compatible = "qcom,sda845-hdk"
compatible = "qcom,sdm670-rumi"
compatible = "qcom,sdm670-cdp"
compatible = "qcom,sdm670-mtp"
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
index cc4c3cc..06b1ed9 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
@@ -14,393 +14,15 @@
- reg
Usage: required
Value type: <prop-encoded-array>
- Definition: Addresses and sizes for the memory of the OSM controller,
- cluster PLL management, and APCS common register regions.
- Optionally, the address of the efuse registers used to
- determine the pwrcl or perfcl speed-bins and/or the ACD
- register space to initialize prior to enabling OSM.
+ Definition: Addresses and sizes for the memory of the OSM controller.
- reg-names
Usage: required
Value type: <stringlist>
Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",
- "osm_perfcl_base", "l3_pll", "pwrcl_pll", "perfcl_pll",
- "l3_sequencer", "pwrcl_sequencer", or "perfcl_sequencer".
- Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse",
- "pwrcl_acd", "perfcl_acd", "l3_acd".
+ "osm_perfcl_base".
Must be specified in the same order as the corresponding
addresses are specified in the reg property.
-
-- vdd-l3-supply
- Usage: required
- Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the L3 cluster.
-
-- vdd-pwrcl-supply
- Usage: required
- Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the Power cluster.
-
-- vdd-perfcl-supply
- Usage: required
- Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the Performance cluster.
-
-- interrupts
- Usage: required
- Value type: <prop-encoded-array>
- Definition: OSM interrupt specifier.
-
-- interrupt-names
- Usage: required
- Value type: <stringlist>
- Definition: Interrupt names. this list must match up 1-to-1 with the
- interrupts specified in the 'interrupts' property.
- "pwrcl-irq" and "perfcl-irq" must be specified.
-
-- qcom,l3-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level, and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the L3 cluster.
-
-- qcom,pwrcl-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level, and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the Power cluster.
-
-- qcom,perfcl-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the Performance cluster.
-
-- qcom,osm-no-tz
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates that there is no programming
- of the OSM hardware performed by the secure world.
-
-- qcom,osm-pll-setup
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates that the PLL setup sequence
- must be executed for each clock domain managed by the OSM
- controller.
-
-- qcom,up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the DCVS up timer value in nanoseconds
- for each of the three clock domains managed by the OSM
- controller.
-
-- qcom,down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the DCVS down timer value in nanoseconds
- for each of the three clock domains managed by the OSM
- controller.
-
-- qcom,pc-override-index
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the OSM performance index to be used
- when each cluster enters certain low power modes.
-
-- qcom,set-ret-inactive
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if domains in retention must
- be treated as inactive.
-
-- qcom,enable-llm-freq-vote
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if Limits hardware frequency
- votes must be honored by OSM.
-
-- qcom,llm-freq-up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM frequency up timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,llm-freq-down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM frequency down timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,enable-llm-volt-vote
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if Limits hardware voltage
- votes must be honored by OSM.
-
-- qcom,llm-volt-up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM voltage up timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,llm-volt-down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM voltage down timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,cc-reads
- Usage: optional
- Value type: <integer>
- Definition: Defines the number of times the cycle counters must be
- read to determine the performance level of each clock
- domain.
-
-- qcom,l-val-base
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the L_VAL
- control register for each of the three clock domains
- managed by the OSM controller.
-
-- qcom,apcs-pll-user-ctl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the PLL
- user control register for each of the three clock domains
- managed by the OSM controller.
-
-- qcom,perfcl-apcs-apm-threshold-voltage
- Usage: required
- Value type: <u32>
- Definition: Specifies the APM threshold voltage in microvolts. If the
- VDD_APCC supply voltage is above or at this level, then the
- APM is switched to use VDD_APCC. If VDD_APCC is below
- this level, then the APM is switched to use VDD_MX.
-
-- qcom,apm-mode-ctl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the APM
- control register for each of the two clusters managed
- by the OSM controller.
-
-- qcom,apm-status-ctrl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the APM
- controller status register for each of the three clock
- domains managed by the OSM controller.
-
-- qcom,perfcl-isense-addr
- Usage: required
- Value type: <u32>
- Definition: Contains the ISENSE register address.
-
-- qcom,l3-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the L3 cluster.
- The array must contain exactly three elements.
-
-- qcom,pwrcl-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the Power cluster.
- The array must contain exactly three elements.
-
-- qcom,perfcl-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the Performance cluster.
- The array must contain exactly three elements.
-
-- qcom,perfcl-apcs-mem-acc-threshold-voltage
- Usage: optional
- Value type: <u32>
- Definition: Specifies the highest MEM ACC threshold voltage in
- microvolts for the Performance cluster. This voltage is
- used to determine which MEM ACC setting is used for the
- highest frequencies. If specified, the voltage must match
- the MEM ACC threshold voltage specified for the
- corresponding CPRh device.
-
-- qcom,l3-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the L3 clock
- on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,pwrcl-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the Power
- cluster clock on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,perfcl-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the
- Performance cluster clock on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,apcs-cbc-addr
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the APCS_CBC_ADDR
- registers for all three clock domains.
-
-- qcom,apcs-ramp-ctl-addr
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the APCS_RAMP_CTL_ADDR
- registers for all three clock domains.
-
-- qcom,red-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the reduction FSM
- should be enabled.
-
-- qcom,boost-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the boost FSM should
- be enabled.
-
-- qcom,safe-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the safe FSM should
- be enabled.
-
-- qcom,ps-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the PS FSM should be
- enabled.
-
-- qcom,droop-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the droop FSM should
- be enabled.
-
-- qcom,set-c3-active
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the cores in C3 are to
- be treated as active for core count calculations.
-
-- qcom,set-c2-active
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the cores in C2 are to
- be treated as active for core count calculations.
-
-- qcom,disable-cc-dvcs
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if core count based DCVS is
- to be disabled.
-
-- qcom,apcs-pll-min-freq
- Usage: required
- Value type: <u32>
- Definition: Contains the addresses of the RAILx_CLKDOMy_PLL_MIN_FREQ
- registers for the three clock domains.
-
-- qcom,acdtd-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values to program to the ACD
- Tunable-Length Delay register for the L3, power and
- performance clusters.
-
-- qcom,acdcr-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD control register
- for the L3, power and performance clusters.
-
-- qcom,acdsscr-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD Soft Start Control
- register for the L3, power and performance clusters.
-
-- qcom,acdextint0-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the initial values for the ACD
- external interface configuration register for the L3, power
- and performance clusters.
-
-- qcom,acdextint1-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the final values for the ACD
- external interface configuration register for the L3, power
- and performance clusters.
-
-- qcom,acdautoxfer-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD auto transfer
- control register for the L3, power and performance clusters.
-
-- qcom,acdavg-init
- Usage: optional if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines if the AVG feature for ACD should be
- initialized for the L3, power and performance clusters.
- Valid values are 0 or 1.
-
-- qcom,acdavgcfg0-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG0
- registers for the L3, power and performance clusters.
-
-- qcom,acdavgcfg1-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG1
- registers for the L3, power and performance clusters.
-
-- qcom,acdavgcfg2-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG2
- registers for the L3, power and performance clusters.
-
- clock-names
Usage: required
Value type: <string>
@@ -416,156 +38,10 @@
compatible = "qcom,clk-cpu-osm";
reg = <0x17d41000 0x1400>,
<0x17d43000 0x1400>,
- <0x17d45800 0x1400>,
- <0x178d0000 0x1000>,
- <0x178c0000 0x1000>,
- <0x178b0000 0x1000>,
- <0x17d42400 0x0c00>,
- <0x17d44400 0x0c00>,
- <0x17d46c00 0x0c00>,
- <0x17930000 0x10000>,
- <0x17920000 0x10000>,
- <0x17910000 0x10000>;
- reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
- "l3_pll", "pwrcl_pll", "perfcl_pll",
- "l3_sequencer", "pwrcl_sequencer",
- "perfcl_sequencer", "l3_acd", "pwrcl_acd",
- "perfcl_acd";
-
- /* ACD configurations for L3, Silver, and Gold clusters */
- qcom,acdtd-val = <0x0000b411 0x0000b411 0x0000b411>;
- qcom,acdcr-val = <0x002c5ffd 0x002c5ffd 0x002c5ffd>;
- qcom,acdsscr-val = <0x00000901 0x00000901 0x00000901>;
- qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8 0x2cf9ae8>;
- qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe 0x2cf9afe>;
- qcom,acdautoxfer-val = <0x00000015 0x00000015 0x00000015>;
- qcom,acdavgcfg2-val = <0x0 0x56a38822 0x56a38822>;
- qcom,acdavgcfg1-val = <0x0 0x27104e20 0x27104e20>;
- qcom,acdavgcfg0-val = <0x0 0xa08007a1 0xa08007a1>;
- qcom,acdavg-init = <0 1 1>;
-
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
-
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 729600000 0x501c0526 0x00002020 0x1 6 >,
- < 806400000 0x501c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072b 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x2 9 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 748800000 0x501c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003333 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x403c0e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00004040 0x2 16 >,
- < 1593600000 0x403c1053 0x00004343 0x2 17 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 729600000 0x501c0526 0x00002020 0x1 6 >,
- < 806400000 0x501c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072b 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x2 17 >,
- < 1651200000 0x403c1156 0x00004545 0x2 18 >,
- < 1728000000 0x4044125a 0x00004848 0x2 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x2 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x2 21 >,
- < 1958400000 0x404c1566 0x00005252 0x3 22 >;
-
- qcom,l3-memacc-level-vc-bin0 = <7 63>;
- qcom,l3-memacc-level-vc-bin1 = <7 9>;
- qcom,l3-memacc-level-vc-bin2 = <7 9>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 63>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 17>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 17>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin1 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin2 = <12 18>;
-
- qcom,up-timer =
- <1000 1000 1000>;
- qcom,down-timer =
- <100000 100000 100000>;
- qcom,pc-override-index =
- <0 0 0>;
- qcom,set-ret-inactive;
- qcom,enable-llm-freq-vote;
- qcom,llm-freq-up-timer =
- <1000 1000 1000>;
- qcom,llm-freq-down-timer =
- <327675 327675 327675>;
- qcom,enable-llm-volt-vote;
- qcom,llm-volt-up-timer =
- <1000 1000 1000>;
- qcom,llm-volt-down-timer =
- <327675 327675 327675>;
- qcom,cc-reads = <10>;
- qcom,cc-delay = <5>;
- qcom,cc-factor = <100>;
- qcom,osm-clk-rate = <100000000>;
- qcom,xo-clk-rate = <19200000>;
-
- qcom,l-val-base =
- <0x178d0004 0x178c0004 0x178b0004>;
- qcom,apcs-pll-user-ctl =
- <0x178d000c 0x178c000c 0x178b000c>;
- qcom,apcs-pll-min-freq =
- <0x17d41094 0x17d43094 0x17d45894>;
- qcom,apm-mode-ctl =
- <0x0 0x0 0x17d20010>;
- qcom,apm-status-ctrl =
- <0x0 0x0 0x17d20000>;
- qcom,perfcl-isense-addr = <0x17871480>;
- qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>;
- qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>;
- qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>;
- qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>;
- qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>;
- qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>;
-
- qcom,perfcl-apcs-apm-threshold-voltage = <800000>;
- qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>;
- qcom,boost-fsm-en;
- qcom,safe-fsm-en;
- qcom,ps-fsm-en;
- qcom,droop-fsm-en;
- qcom,osm-no-tz;
- qcom,osm-pll-setup;
+ <0x17d45800 0x1400>;
+ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
clock-names = "xo_ao";
clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
#clock-cells = <1>;
- #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt
index 2a5096f..6af2bac 100644
--- a/Documentation/devicetree/bindings/pci/msm_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt
@@ -95,6 +95,9 @@
and assign for each endpoint.
- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
stable after power on, before de-assert the PERST to the endpoint.
+ - qcom,switch-latency: The time (unit: ms) to wait for the PCIe endpoint's link
+ training with switch downstream port after the link between switch upstream
+ port and RC is up.
- qcom,wr-halt-size: With base 2, this exponent determines the size of the
data that PCIe core will halt on for each write transaction.
- qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.
@@ -268,6 +271,7 @@
qcom,smmu-exist;
qcom,smmu-sid-base = <0x1480>;
qcom,ep-latency = <100>;
+ qcom,switch-latency = <100>;
qcom,wr-halt-size = <0xa>; /* 1KB */
qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
qcom,cpl-timeout = <0x2>;
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index 85b0fe9..abbc560 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -32,6 +32,7 @@
This may be a shared regulator that is already voted
on in the PIL proxy voting code (and also managed by the
modem on its own), hence we mark it as as optional.
+- vdd_mss-uV: Voltage to set for vdd_mss.
- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail.
- qcom,vdd_pll: Voltage to be set for the PLL's rail.
- reg-names: "cxrail_bhs_reg" - control register for modem power
diff --git a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt b/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
index 749c6e85..4c89846 100644
--- a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
+++ b/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
@@ -9,10 +9,18 @@
- reg-names : Indicates various client-names.
- qcom,client-id : The client id for the QMI clients.
+Optional properties:
+- qcom,guard-memory: If this dtsi property is set, then the shared memory
+ region will be guarded by SZ_4K at the start and at the end.
+ This is needed to overcome the XPU limitation on few MSM HW,
+ so as to make this memory not contiguous with other allocations
+ that may possibly happen from other clients.
+
Example:
qcom,msm_sharedmem@0dc80000 {
compatible = "qcom,sharedmem-uio";
reg = <0x0dc80000 0x00180000>,
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
};
diff --git a/arch/arm/boot/dts/qcom/pm8950.dtsi b/arch/arm/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 0000000..f47872a
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,388 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&spmi_bus {
+ qcom,pm8950@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm8950_temp_alarm: qcom,temp-alarm@2400 {
+ compatible = "qcom,qpnp-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0>;
+ label = "pm8950_tz";
+ qcom,channel-num = <8>;
+ qcom,threshold-set = <0>;
+ qcom,temp_alarm-vadc = <&pm8950_vadc>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0>,
+ <0x0 0x8 0x1>,
+ <0x0 0x8 0x4>,
+ <0x0 0x8 0x5>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8950_coincell: qcom,coincell@2800 {
+ compatible = "qcom,qpnp-coincell";
+ reg = <0x2800 0x100>;
+ };
+
+ pm8950_mpps: mpps {
+ compatible = "qcom,qpnp-pin";
+ spmi-dev-container;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ /* MPP2 - PA_THERM config */
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <1>; /* AMUX 6 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ /* MPP4 - CASE_THERM config */
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <3>; /* AMUX 8 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+ };
+
+ pm8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ gpio@c200 {
+ reg = <0xc200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ gpio@c300 {
+ reg = <0xc300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+
+ gpio@c400 {
+ reg = <0xc400 0x100>;
+ qcom,pin-num = <5>;
+ status = "disabled";
+ };
+
+ gpio@c500 {
+ reg = <0xc500 0x100>;
+ qcom,pin-num = <6>;
+ status = "disabled";
+ };
+
+ gpio@c600 {
+ reg = <0xc600 0x100>;
+ qcom,pin-num = <7>;
+ status = "disabled";
+ };
+
+ gpio@c700 {
+ reg = <0xc700 0x100>;
+ qcom,pin-num = <8>;
+ status = "disabled";
+ };
+ };
+
+ pm8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@5 {
+ label = "vcoin";
+ reg = <5>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@8 {
+ label = "die_temp";
+ reg = <8>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <3>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@c {
+ label = "ref_buf_625mv";
+ reg = <0xc>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@11 {
+ label = "pa_therm1";
+ reg = <0x11>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@32 {
+ label = "xo_therm";
+ reg = <0x32>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@3c {
+ label = "xo_therm_buf";
+ reg = <0x3c>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@13 {
+ label = "case_therm";
+ reg = <0x13>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+ };
+
+ pm8950_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0>,
+ <0x0 0x34 0x3>,
+ <0x0 0x34 0x4>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,adc_tm-vadc = <&pm8950_vadc>;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,thermal-node;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <0x7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x68>;
+ };
+ };
+
+ pm8950_rtc: qcom,pm8950_rtc {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-rtc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,qpnp-rtc-write = <0>;
+ qcom,qpnp-rtc-alarm-pwrup = <0>;
+
+ qcom,pm8950_rtc_rw@6000 {
+ reg = <0x6000 0x100>;
+ };
+
+ qcom,pm8950_rtc_alarm@6100 {
+ reg = <0x6100 0x100>;
+ interrupts = <0x0 0x61 0x1>;
+ };
+ };
+
+ qcom,leds@a300 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa300 0x100>;
+ label = "mpp";
+ };
+ };
+
+ pm8950_1: qcom,pm8950@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_pwm: pwm@bc00 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xbc00 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/pmi8950.dtsi b/arch/arm/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 0000000..0ec1f0b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,641 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/power-on.h>
+
+&spmi_bus {
+ qcom,pmi8950@2 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,secondary-pon-reset;
+ qcom,hard-reset-poweroff-type =
+ <PON_POWER_OFF_SHUTDOWN>;
+
+ pon_perph_reg: qcom,pon_perph_reg {
+ regulator-name = "pon_spare_reg";
+ qcom,pon-spare-reg-addr = <0x8c>;
+ qcom,pon-spare-reg-bit = <1>;
+ };
+ };
+
+ pmi8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+
+ chan@0 {
+ label = "usbin";
+ reg = <0>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@1 {
+ label = "dcin";
+ reg = <1>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@3 {
+ label = "vchg_sns";
+ reg = <3>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@d {
+ label = "chg_temp";
+ reg = <0xd>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <16>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@43 {
+ label = "usb_dp";
+ reg = <0x43>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@44 {
+ label = "usb_dm";
+ reg = <0x44>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+ };
+
+ pmi8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_mpps: mpps {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_charger: qcom,qpnp-smbcharger {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-smbcharger";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,iterm-ma = <100>;
+ qcom,float-voltage-mv = <4200>;
+ qcom,resume-delta-mv = <200>;
+ qcom,chg-inhibit-fg;
+ qcom,rparasitic-uohm = <100000>;
+ qcom,bms-psy-name = "bms";
+ qcom,thermal-mitigation = <1500 700 600 0>;
+ qcom,parallel-usb-min-current-ma = <1400>;
+ qcom,parallel-usb-9v-min-current-ma = <900>;
+ qcom,parallel-allowed-lowering-ma = <500>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,force-aicl-rerun;
+ qcom,aicl-rerun-period-s = <180>;
+ qcom,autoadjust-vfloat;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x2 0x10 0x0>,
+ <0x2 0x10 0x1>,
+ <0x2 0x10 0x2>,
+ <0x2 0x10 0x3>,
+ <0x2 0x10 0x4>,
+ <0x2 0x10 0x5>,
+ <0x2 0x10 0x6>,
+ <0x2 0x10 0x7>;
+
+ interrupt-names = "chg-error",
+ "chg-inhibit",
+ "chg-prechg-sft",
+ "chg-complete-chg-sft",
+ "chg-p2f-thr",
+ "chg-rechg-thr",
+ "chg-taper-thr",
+ "chg-tcc-thr";
+ };
+
+ qcom,otg@1100 {
+ reg = <0x1100 0x100>;
+ interrupts = <0x2 0x11 0x0>,
+ <0x2 0x11 0x1>,
+ <0x2 0x11 0x3>;
+ interrupt-names = "otg-fail",
+ "otg-oc",
+ "usbid-change";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts = <0x2 0x12 0x0>,
+ <0x2 0x12 0x1>,
+ <0x2 0x12 0x2>,
+ <0x2 0x12 0x3>,
+ <0x2 0x12 0x4>,
+ <0x2 0x12 0x5>,
+ <0x2 0x12 0x6>,
+ <0x2 0x12 0x7>;
+
+ interrupt-names = "batt-hot",
+ "batt-warm",
+ "batt-cold",
+ "batt-cool",
+ "batt-ov",
+ "batt-low",
+ "batt-missing",
+ "batt-term-missing";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts = <0x2 0x13 0x0>,
+ <0x2 0x13 0x1>,
+ <0x2 0x13 0x2>,
+ <0x2 0x13 0x5>;
+
+ interrupt-names = "usbin-uv",
+ "usbin-ov",
+ "usbin-src-det",
+ "aicl-done";
+ };
+
+ qcom,dc-chgpth@1400 {
+ reg = <0x1400 0x100>;
+ interrupts = <0x2 0x14 0x0>,
+ <0x2 0x14 0x1>;
+ interrupt-names = "dcin-uv",
+ "dcin-ov";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x2 0x16 0x0>,
+ <0x2 0x16 0x1>,
+ <0x2 0x16 0x2>,
+ <0x2 0x16 0x3>,
+ <0x2 0x16 0x4>,
+ <0x2 0x16 0x5>;
+
+ interrupt-names = "power-ok",
+ "temp-shutdown",
+ "wdog-timeout",
+ "flash-fail",
+ "otst2",
+ "otst3";
+ };
+
+ smbcharger_charger_otg: qcom,smbcharger-boost-otg {
+ regulator-name = "smbcharger_charger_otg";
+ };
+ };
+
+ pmi8950_fg: qcom,fg {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-fg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,resume-soc = <95>;
+ status = "okay";
+ qcom,bcl-lm-threshold-ma = <127>;
+ qcom,bcl-mh-threshold-ma = <405>;
+ qcom,fg-iterm-ma = <150>;
+ qcom,fg-chg-iterm-ma = <100>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,fg-cutoff-voltage-mv = <3500>;
+ qcom,cycle-counter-en;
+ qcom,capacity-learning-on;
+
+ qcom,fg-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0>,
+ <0x2 0x40 0x1>,
+ <0x2 0x40 0x2>,
+ <0x2 0x40 0x3>,
+ <0x2 0x40 0x4>,
+ <0x2 0x40 0x5>,
+ <0x2 0x40 0x6>;
+
+ interrupt-names = "high-soc",
+ "low-soc",
+ "full-soc",
+ "empty-soc",
+ "delta-soc",
+ "first-est-done",
+ "update-soc";
+ };
+
+ qcom,fg-batt@4100 {
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0>,
+ <0x2 0x41 0x1>,
+ <0x2 0x41 0x2>,
+ <0x2 0x41 0x3>,
+ <0x2 0x41 0x4>,
+ <0x2 0x41 0x5>,
+ <0x2 0x41 0x6>,
+ <0x2 0x41 0x7>;
+
+ interrupt-names = "soft-cold",
+ "soft-hot",
+ "vbatt-low",
+ "batt-ided",
+ "batt-id-req",
+ "batt-unknown",
+ "batt-missing",
+ "batt-match";
+ };
+
+ qcom,revid-tp-rev@1f1 {
+ reg = <0x1f1 0x1>;
+ };
+
+ qcom,fg-memif@4400 {
+ status = "okay";
+ reg = <0x4400 0x100>;
+ interrupts = <0x2 0x44 0x0>,
+ <0x2 0x44 0x2>;
+
+ interrupt-names = "mem-avail",
+ "data-rcvry-sug";
+ };
+ };
+
+ bcl@4200 {
+ compatible = "qcom,msm-bcl";
+ reg = <0x4200 0xFF 0x88E 0x2>;
+ reg-names = "fg_user_adc", "pon_spare";
+ interrupts = <0x2 0x42 0x0>,
+ <0x2 0x42 0x1>;
+ interrupt-names = "bcl-high-ibat-int",
+ "bcl-low-vbat-int";
+ qcom,vbat-scaling-factor = <39000>;
+ qcom,vbat-gain-numerator = <1>;
+ qcom,vbat-gain-denominator = <128>;
+ qcom,vbat-polling-delay-ms = <100>;
+ qcom,ibat-scaling-factor = <39000>;
+ qcom,ibat-gain-numerator = <1>;
+ qcom,ibat-gain-denominator = <128>;
+ qcom,ibat-offset-numerator = <1200>;
+ qcom,ibat-offset-denominator = <1>;
+ qcom,ibat-polling-delay-ms = <100>;
+ qcom,inhibit-derating-ua = <550000>;
+ };
+
+ qcom,leds@a100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa100 0x100>;
+ label = "mpp";
+ };
+ };
+
+ qcom,pmi8950@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmi8950_pwm: pwm@b000 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xb000 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+
+ labibb: qpnp-labibb-regulator {
+ status = "disabled";
+ spmi-dev-container;
+ compatible = "qcom,qpnp-labibb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ ibb_regulator: qcom,ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_reg";
+ regulator-name = "ibb_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-ibb-min-voltage = <1400000>;
+ qcom,qpnp-ibb-step-size = <100000>;
+ qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-use-default-voltage;
+ qcom,qpnp-ibb-init-voltage = <5500000>;
+ qcom,qpnp-ibb-init-amoled-voltage = <4000000>;
+ qcom,qpnp-ibb-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-ibb-soft-start = <1000>;
+
+ qcom,qpnp-ibb-discharge-resistor = <32>;
+ qcom,qpnp-ibb-lab-pwrup-delay = <8000>;
+ qcom,qpnp-ibb-lab-pwrdn-delay = <8000>;
+ qcom,qpnp-ibb-en-discharge;
+
+ qcom,qpnp-ibb-full-pull-down;
+ qcom,qpnp-ibb-pull-down-enable;
+ qcom,qpnp-ibb-switching-clock-frequency =
+ <1480>;
+ qcom,qpnp-ibb-limit-maximum-current = <1550>;
+ qcom,qpnp-ibb-debounce-cycle = <16>;
+ qcom,qpnp-ibb-limit-max-current-enable;
+ qcom,qpnp-ibb-ps-enable;
+ };
+
+ lab_regulator: qcom,lab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "lab";
+ regulator-name = "lab_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-lab-min-voltage = <4600000>;
+ qcom,qpnp-lab-step-size = <100000>;
+ qcom,qpnp-lab-slew-rate = <5000>;
+ qcom,qpnp-lab-use-default-voltage;
+ qcom,qpnp-lab-init-voltage = <5500000>;
+ qcom,qpnp-lab-init-amoled-voltage = <4600000>;
+ qcom,qpnp-lab-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-lab-soft-start = <800>;
+
+ qcom,qpnp-lab-full-pull-down;
+ qcom,qpnp-lab-pull-down-enable;
+ qcom,qpnp-lab-switching-clock-frequency =
+ <1600>;
+ qcom,qpnp-lab-limit-maximum-current = <800>;
+ qcom,qpnp-lab-limit-max-current-enable;
+ qcom,qpnp-lab-ps-threshold = <40>;
+ qcom,qpnp-lab-ps-enable;
+ qcom,qpnp-lab-nfet-size = <100>;
+ qcom,qpnp-lab-pfet-size = <100>;
+ qcom,qpnp-lab-max-precharge-time = <500>;
+ };
+
+ };
+
+ wled: qcom,leds@d800 {
+ compatible = "qcom,qpnp-wled";
+ reg = <0xd800 0x100>,
+ <0xd900 0x100>,
+ <0xdc00 0x100>,
+ <0xde00 0x100>;
+ reg-names = "qpnp-wled-ctrl-base",
+ "qpnp-wled-sink-base",
+ "qpnp-wled-ibb-base",
+ "qpnp-wled-lab-base";
+ interrupts = <0x3 0xd8 0x2>;
+ interrupt-names = "sc-irq";
+ status = "okay";
+ linux,name = "wled";
+ linux,default-trigger = "bkl-trigger";
+ qcom,fdbk-output = "auto";
+ qcom,vref-mv = <350>;
+ qcom,switch-freq-khz = <800>;
+ qcom,ovp-mv = <29500>;
+ qcom,ilim-ma = <980>;
+ qcom,boost-duty-ns = <26>;
+ qcom,mod-freq-khz = <9600>;
+ qcom,dim-mode = "hybrid";
+ qcom,dim-method = "linear";
+ qcom,hyb-thres = <625>;
+ qcom,sync-dly-us = <800>;
+ qcom,fs-curr-ua = <20000>;
+ qcom,led-strings-list = [00 01];
+ qcom,en-ext-pfet-sc-pro;
+ qcom,cons-sync-write-delay-us = <1000>;
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ qcom,headroom = <500>;
+ qcom,startup-dly = <128>;
+ qcom,clamp-curr = <200>;
+ qcom,pmic-charger-support;
+ qcom,self-check-enabled;
+ qcom,thermal-derate-enabled;
+ qcom,thermal-derate-threshold = <100>;
+ qcom,thermal-derate-rate = "5_PERCENT";
+ qcom,current-ramp-enabled;
+ qcom,ramp_up_step = "6P7_US";
+ qcom,ramp_dn_step = "6P7_US";
+ qcom,vph-pwr-droop-enabled;
+ qcom,vph-pwr-droop-threshold = <3000>;
+ qcom,vph-pwr-droop-debounce-time = <10>;
+ qcom,headroom-sense-ch0-enabled;
+ qcom,headroom-sense-ch1-enabled;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ pmi8950_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,default-led-trigger =
+ "flash0_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <0>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,default-led-trigger =
+ "flash1_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <1>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,default-led-trigger =
+ "torch0_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <0>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,default-led-trigger =
+ "torch1_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <1>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_switch: qcom,switch {
+ label = "switch";
+ qcom,led-name = "led:switch";
+ qcom,default-led-trigger =
+ "switch_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <2>;
+ qcom,current = <625>;
+ reg0 {
+ regulator-name = "pon_spare_reg";
+ };
+ };
+ };
+
+ pmi_haptic: qcom,haptic@c000 {
+ compatible = "qcom,qpnp-haptic";
+ reg = <0xc000 0x100>;
+ interrupts = <0x3 0xc0 0x0>,
+ <0x3 0xc0 0x1>;
+ interrupt-names = "sc-irq", "play-irq";
+ qcom,pmic-revid = <&pmi8950_revid>;
+ vcc_pon-supply = <&pon_perph_reg>;
+ qcom,play-mode = "direct";
+ qcom,wave-play-rate-us = <5263>;
+ qcom,actuator-type = "erm";
+ qcom,wave-shape = "square";
+ qcom,vmax-mv = <2000>;
+ qcom,ilim-ma = <800>;
+ qcom,sc-deb-cycles = <8>;
+ qcom,int-pwm-freq-khz = <505>;
+ qcom,en-brake;
+ qcom,brake-pattern = [03 03 00 00];
+ qcom,use-play-irq;
+ qcom,use-sc-irq;
+ qcom,wave-samples = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wave-rep-cnt = <1>;
+ qcom,wave-samp-rep-cnt = <1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi
new file mode 100644
index 0000000..d1d44ec
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi
@@ -0,0 +1,804 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1100000 0x400000>,
+ <0x1100000 0x400000>,
+ <0x1620000 0x400000>,
+ <0x1620000 0x400000>;
+
+ reg-names = "mc_virt-base", "mem_noc-base",
+ "system_noc-base", "ipa_virt-base";
+
+ /*RSCs*/
+ rsc_apps: rsc-apps {
+ cell-id = <MSM_BUS_RSC_APPS>;
+ label = "apps_rsc";
+ qcom,rsc-dev;
+ qcom,req-state = <2>;
+ };
+
+ /*BCMs*/
+ bcm_alc: bcm-alc {
+ cell-id = <MSM_BUS_BCM_ALC>;
+ label = "ALC";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ce: bcm-ce {
+ cell-id = <MSM_BUS_BCM_CE>;
+ label = "CE";
+ qcom,bcm-name = "CE";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0: bcm-mc0 {
+ cell-id = <MSM_BUS_BCM_MC0>;
+ label = "MC0";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ip0: bcm-ip0 {
+ cell-id = <MSM_BUS_BCM_IP0>;
+ label = "IP0";
+ qcom,bcm-name = "CE";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0: bcm-sh0 {
+ cell-id = <MSM_BUS_BCM_SH0>;
+ label = "SH0";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn0: bcm-pn0 {
+ cell-id = <MSM_BUS_BCM_PN0>;
+ label = "PN0";
+ qcom,bcm-name = "PN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh1: bcm-sh1 {
+ cell-id = <MSM_BUS_BCM_SH1>;
+ label = "SH1";
+ qcom,bcm-name = "SH1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh3: bcm-sh3 {
+ cell-id = <MSM_BUS_BCM_SH3>;
+ label = "SH3";
+ qcom,bcm-name = "SH3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh4: bcm-sh4 {
+ cell-id = <MSM_BUS_BCM_SH4>;
+ label = "SH4";
+ qcom,bcm-name = "SH4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn0: bcm-sn0 {
+ cell-id = <MSM_BUS_BCM_SN0>;
+ label = "SN0";
+ qcom,bcm-name = "SN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn1: bcm-sn1 {
+ cell-id = <MSM_BUS_BCM_SN1>;
+ label = "SN1";
+ qcom,bcm-name = "SN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn1: bcm-pn1 {
+ cell-id = <MSM_BUS_BCM_PN1>;
+ label = "PN1";
+ qcom,bcm-name = "PN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn2: bcm-pn2 {
+ cell-id = <MSM_BUS_BCM_PN2>;
+ label = "PN2";
+ qcom,bcm-name = "PN2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn3: bcm-sn3 {
+ cell-id = <MSM_BUS_BCM_SN3>;
+ label = "SN3";
+ qcom,bcm-name = "SN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn3: bcm-pn3 {
+ cell-id = <MSM_BUS_BCM_PN3>;
+ label = "PN3";
+ qcom,bcm-name = "PN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn5: bcm-pn5 {
+ cell-id = <MSM_BUS_BCM_PN5>;
+ label = "PN5";
+ qcom,bcm-name = "PN5";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn6: bcm-sn6 {
+ cell-id = <MSM_BUS_BCM_SN6>;
+ label = "SN6";
+ qcom,bcm-name = "SN6";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn7: bcm-sn7 {
+ cell-id = <MSM_BUS_BCM_SN7>;
+ label = "SN7";
+ qcom,bcm-name = "SN7";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn8: bcm-sn8 {
+ cell-id = <MSM_BUS_BCM_SN8>;
+ label = "SN8";
+ qcom,bcm-name = "SN8";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn9: bcm-sn9 {
+ cell-id = <MSM_BUS_BCM_SN9>;
+ label = "SN9";
+ qcom,bcm-name = "SN9";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn11: bcm-sn11 {
+ cell-id = <MSM_BUS_BCM_SN11>;
+ label = "SN11";
+ qcom,bcm-name = "SN11";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ /*Buses*/
+ fab_ipa_virt: fab-ipa_virt{
+ cell-id = <MSM_BUS_FAB_IPA_VIRT>;
+ label = "fab-ipa_virt";
+ qcom,fab-dev;
+ qcom,base-name = "ipa_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mc_virt: fab-mc_virt{
+ cell-id = <MSM_BUS_FAB_MC_VIRT>;
+ label = "fab-mc_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mem_noc: fab-mem_noc {
+ cell-id = <MSM_BUS_FAB_MEM_NOC>;
+ label = "fab-mem_noc";
+ qcom,fab-dev;
+ qcom,base-name = "mem_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <65536>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_system_noc: fab-system_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-system_noc";
+ qcom,fab-dev;
+ qcom,base-name = "system_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ /*Masters*/
+
+ mas_ipa_core_master: mas-ipa-core-master {
+ cell-id = <MSM_BUS_MASTER_IPA_CORE>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ipa_core_slave>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ };
+
+ mas_llcc_mc: mas-llcc-mc {
+ cell-id = <MSM_BUS_MASTER_LLCC>;
+ label = "mas-llcc-mc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ };
+
+ mas_acm_tcu: mas-acm-tcu {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-acm-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,bcms = <&bcm_sh1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_qnm_snoc_gc: mas-qnm-snoc-gc {
+ cell-id = <MSM_BUS_MASTER_SNOC_GC_MEM_NOC>;
+ label = "mas-qnm-snoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_xm_apps_rdwr: mas-xm-apps-rdwr {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-xm-apps-rdwr";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_llcc &slv_qns_memnoc_snoc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_qhm_audio: mas-qhm-audio {
+ cell-id = <MSM_BUS_MASTER_AUDIO>;
+ label = "mas-qhm-audio";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn2>;
+ };
+
+ mas_qhm_blsp1: mas-qhm-blsp1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-qhm-blsp1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn3>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn8>;
+ };
+
+ mas_qhm_qpic: mas-qhm-qpic {
+ cell-id = <MSM_BUS_MASTER_QPIC>;
+ label = "mas-qhm-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn3>;
+ };
+
+ mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-qhm-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qhm_spmi_fetcher1: mas-qhm-spmi-fetcher1 {
+ cell-id = <MSM_BUS_MASTER_SPMI_FETCHER>;
+ label = "mas-qhm-spmi-fetcher1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc &slv_qhs_aop>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn2>;
+ };
+
+ mas_qnm_aggre_noc: mas-qnm-aggre-noc {
+ cell-id = <MSM_BUS_MASTER_ANOC_SNOC>;
+ label = "mas-qnm-aggre-noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_xs_qdss_stm
+ &slv_qhs_qpic &slv_qxs_imem
+ &slv_qhs_ipa &slv_qhs_usb3_phy
+ &slv_qhs_aop &slv_qhs_blsp1
+ &slv_qhs_sdc1 &slv_qhs_pcie_parf
+ &slv_qhs_audio &slv_qxs_pcie
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn7>;
+ };
+
+ mas_qnm_aggre_noc_ipa: mas-qnm-aggre-noc-ipa {
+ cell-id = <MSM_BUS_MASTER_ANOC_IPA>;
+ label = "mas-qnm-aggre-noc-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_xs_qdss_stm
+ &slv_qhs_qpic &slv_qxs_imem
+ &slv_qhs_ipa &slv_qhs_usb3_phy
+ &slv_qhs_aop &slv_qhs_blsp1
+ &slv_qhs_sdc1 &slv_qhs_pcie_parf
+ &slv_qhs_audio &slv_qhs_tlmm
+ &slv_qhs_prng &slv_xs_sys_tcu_cfg
+ &slv_qhs_clk_ctl &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qnm_memnoc: mas-qnm-memnoc {
+ cell-id = <MSM_BUS_MASTER_MEM_NOC_SNOC>;
+ label = "mas-qnm-memnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qhs_tcsr
+ &slv_xs_qdss_stm &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn9>;
+ };
+
+ mas_qxm_crypto: mas-qxm-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE_0>;
+ label = "mas-qxm-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_ce>;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc_ipa>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn11>;
+ };
+
+ mas_xm_emac: mas-xm-emac {
+ cell-id = <MSM_BUS_MASTER_EMAC>;
+ label = "mas-xm-emac";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_xm_pcie: mas-xm-pcie {
+ cell-id = <MSM_BUS_MASTER_PCIE>;
+ label = "mas-xm-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn8>;
+ };
+
+ mas_xm_sdc1: mas-xm-sdc1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-xm-sdc1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn1>;
+ };
+
+ mas_xm_usb3: mas-xm-usb3 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ qcom,bcms = <&bcm_ip0>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ qcom,bcms = <&bcm_mc0>;
+ };
+
+ slv_qns_llcc:slv-qns-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC>;
+ label = "slv-qns-llcc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,connections = <&mas_llcc_mc>;
+ qcom,bcms = <&bcm_sh0>;
+ };
+
+ slv_qns_memnoc_snoc:slv-qns-memnoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_MEM_NOC_SNOC>;
+ label = "slv-qns-memnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,connections = <&mas_qnm_memnoc>;
+ qcom,bcms = <&bcm_sh4>;
+ };
+
+ slv_qhs_aop:slv-qhs-aop {
+ cell-id = <MSM_BUS_SLAVE_AOP>;
+ label = "slv-qhs-aop";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_aoss:slv-qhs-aoss {
+ cell-id = <MSM_BUS_SLAVE_AOSS>;
+ label = "slv-qhs-aoss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_audio:slv-qhs-audio {
+ cell-id = <MSM_BUS_SLAVE_AUDIO>;
+ label = "slv-qhs-audio";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_blsp1:slv-qhs-blsp1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-qhs-blsp1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_crypto_cfg:slv-qhs-crypto-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_emac_cfg:slv-qhs-emac-cfg {
+ cell-id = <MSM_BUS_SLAVE_EMAC_CFG>;
+ label = "slv-qhs-emac-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_ipa:slv-qhs-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_pcie_parf:slv-qhs-pcie-parf {
+ cell-id = <MSM_BUS_SLAVE_PCIE_PARF>;
+ label = "slv-qhs-pcie-parf";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_qpic:slv-qhs-qpic {
+ cell-id = <MSM_BUS_SLAVE_QPIC>;
+ label = "slv-qhs-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_sdc1:slv-qhs-sdc1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-qhs-sdc1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_snoc_cfg:slv-qhs-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-qhs-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qhm_snoc_cfg>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_spmi_fetcher:slv-qhs-spmi-fetcher {
+ cell-id = <MSM_BUS_SLAVE_SPMI_FETCHER>;
+ label = "slv-qhs-spmi-fetcher";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_tlmm:slv-qhs-tlmm {
+ cell-id = <MSM_BUS_SLAVE_TLMM>;
+ label = "slv-qhs-tlmm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_usb3:slv-qhs-usb3 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_usb3_phy:slv-qhs-usb3-phy {
+ cell-id = <MSM_BUS_SLAVE_USB3_PHY_CFG>;
+ label = "slv-qhs-usb3-phy";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qns_aggre_noc:slv-qns-aggre-noc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_SNOC>;
+ label = "slv-qns-aggre-noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_aggre_noc>;
+ };
+
+ slv_qns_aggre_noc_ipa:slv-qns-aggre-noc-ipa {
+ cell-id = <MSM_BUS_SLAVE_ANOC_IPA>;
+ label = "slv-qns-aggre-noc-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_aggre_noc_ipa>;
+ };
+
+ slv_qns_snoc_memnoc:slv-qns-snoc-memnoc {
+ cell-id = <MSM_BUS_SLAVE_SNOC_MEM_NOC_GC>;
+ label = "slv-qns-snoc-memnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_gc>;
+ qcom,bcms = <&bcm_sn0>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn1>;
+ };
+
+ slv_qxs_pcie:slv-qxs-pcie {
+ cell-id = <MSM_BUS_SLAVE_PCIE_0>;
+ label = "slv-qxs-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn3>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index aa8e31b..146fc9c 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -463,3 +463,4 @@
#include "sdxpoorwills-regulator.dtsi"
#include "sdxpoorwills-smp2p.dtsi"
#include "sdxpoorwills-usb.dtsi"
+#include "sdxpoorwills-bus.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index ee803e2..aec9930 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -17,6 +17,12 @@
sdm845-v2-4k-panel-mtp-overlay.dtbo \
sdm845-v2-4k-panel-cdp-overlay.dtbo \
sdm845-v2-4k-panel-qrd-overlay.dtbo \
+ sdm845-v2.1-cdp-overlay.dtbo \
+ sdm845-v2.1-mtp-overlay.dtbo \
+ sdm845-v2.1-qrd-overlay.dtbo \
+ sdm845-v2.1-4k-panel-mtp-overlay.dtbo \
+ sdm845-v2.1-4k-panel-cdp-overlay.dtbo \
+ sdm845-v2.1-4k-panel-qrd-overlay.dtbo \
sda845-cdp-overlay.dtbo \
sda845-mtp-overlay.dtbo \
sda845-qrd-overlay.dtbo \
@@ -26,6 +32,7 @@
sda845-v2-cdp-overlay.dtbo \
sda845-v2-mtp-overlay.dtbo \
sda845-v2-qrd-overlay.dtbo \
+ sda845-v2-hdk-overlay.dtbo \
sda845-v2-4k-panel-mtp-overlay.dtbo \
sda845-v2-4k-panel-cdp-overlay.dtbo \
sda845-v2-4k-panel-qrd-overlay.dtbo
@@ -44,6 +51,12 @@
sdm845-v2-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.dtb
sdm845-v2-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.dtb
sdm845-v2-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.dtb
+sdm845-v2.1-cdp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-mtp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-qrd-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.1.dtb
sda845-cdp-overlay.dtbo-base := sda845.dtb
sda845-mtp-overlay.dtbo-base := sda845.dtb
sda845-qrd-overlay.dtbo-base := sda845.dtb
@@ -53,6 +66,7 @@
sda845-v2-cdp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-mtp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-qrd-overlay.dtbo-base := sda845-v2.dtb
+sda845-v2-hdk-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-mtp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-cdp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-qrd-overlay.dtbo-base := sda845-v2.dtb
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 0000000..f47872a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,388 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&spmi_bus {
+ qcom,pm8950@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm8950_temp_alarm: qcom,temp-alarm@2400 {
+ compatible = "qcom,qpnp-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0>;
+ label = "pm8950_tz";
+ qcom,channel-num = <8>;
+ qcom,threshold-set = <0>;
+ qcom,temp_alarm-vadc = <&pm8950_vadc>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0>,
+ <0x0 0x8 0x1>,
+ <0x0 0x8 0x4>,
+ <0x0 0x8 0x5>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8950_coincell: qcom,coincell@2800 {
+ compatible = "qcom,qpnp-coincell";
+ reg = <0x2800 0x100>;
+ };
+
+ pm8950_mpps: mpps {
+ compatible = "qcom,qpnp-pin";
+ spmi-dev-container;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ /* MPP2 - PA_THERM config */
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <1>; /* AMUX 6 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ /* MPP4 - CASE_THERM config */
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <3>; /* AMUX 8 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+ };
+
+ pm8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ gpio@c200 {
+ reg = <0xc200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ gpio@c300 {
+ reg = <0xc300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+
+ gpio@c400 {
+ reg = <0xc400 0x100>;
+ qcom,pin-num = <5>;
+ status = "disabled";
+ };
+
+ gpio@c500 {
+ reg = <0xc500 0x100>;
+ qcom,pin-num = <6>;
+ status = "disabled";
+ };
+
+ gpio@c600 {
+ reg = <0xc600 0x100>;
+ qcom,pin-num = <7>;
+ status = "disabled";
+ };
+
+ gpio@c700 {
+ reg = <0xc700 0x100>;
+ qcom,pin-num = <8>;
+ status = "disabled";
+ };
+ };
+
+ pm8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@5 {
+ label = "vcoin";
+ reg = <5>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@8 {
+ label = "die_temp";
+ reg = <8>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <3>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@c {
+ label = "ref_buf_625mv";
+ reg = <0xc>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@11 {
+ label = "pa_therm1";
+ reg = <0x11>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@32 {
+ label = "xo_therm";
+ reg = <0x32>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@3c {
+ label = "xo_therm_buf";
+ reg = <0x3c>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@13 {
+ label = "case_therm";
+ reg = <0x13>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+ };
+
+ pm8950_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0>,
+ <0x0 0x34 0x3>,
+ <0x0 0x34 0x4>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,adc_tm-vadc = <&pm8950_vadc>;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,thermal-node;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <0x7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x68>;
+ };
+ };
+
+ pm8950_rtc: qcom,pm8950_rtc {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-rtc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,qpnp-rtc-write = <0>;
+ qcom,qpnp-rtc-alarm-pwrup = <0>;
+
+ qcom,pm8950_rtc_rw@6000 {
+ reg = <0x6000 0x100>;
+ };
+
+ qcom,pm8950_rtc_alarm@6100 {
+ reg = <0x6100 0x100>;
+ interrupts = <0x0 0x61 0x1>;
+ };
+ };
+
+ qcom,leds@a300 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa300 0x100>;
+ label = "mpp";
+ };
+ };
+
+ pm8950_1: qcom,pm8950@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_pwm: pwm@bc00 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xbc00 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 0000000..0ec1f0b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,641 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/power-on.h>
+
+&spmi_bus {
+ qcom,pmi8950@2 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,secondary-pon-reset;
+ qcom,hard-reset-poweroff-type =
+ <PON_POWER_OFF_SHUTDOWN>;
+
+ pon_perph_reg: qcom,pon_perph_reg {
+ regulator-name = "pon_spare_reg";
+ qcom,pon-spare-reg-addr = <0x8c>;
+ qcom,pon-spare-reg-bit = <1>;
+ };
+ };
+
+ pmi8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+
+ chan@0 {
+ label = "usbin";
+ reg = <0>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@1 {
+ label = "dcin";
+ reg = <1>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@3 {
+ label = "vchg_sns";
+ reg = <3>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@d {
+ label = "chg_temp";
+ reg = <0xd>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <16>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@43 {
+ label = "usb_dp";
+ reg = <0x43>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@44 {
+ label = "usb_dm";
+ reg = <0x44>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+ };
+
+ pmi8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_mpps: mpps {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_charger: qcom,qpnp-smbcharger {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-smbcharger";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,iterm-ma = <100>;
+ qcom,float-voltage-mv = <4200>;
+ qcom,resume-delta-mv = <200>;
+ qcom,chg-inhibit-fg;
+ qcom,rparasitic-uohm = <100000>;
+ qcom,bms-psy-name = "bms";
+ qcom,thermal-mitigation = <1500 700 600 0>;
+ qcom,parallel-usb-min-current-ma = <1400>;
+ qcom,parallel-usb-9v-min-current-ma = <900>;
+ qcom,parallel-allowed-lowering-ma = <500>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,force-aicl-rerun;
+ qcom,aicl-rerun-period-s = <180>;
+ qcom,autoadjust-vfloat;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x2 0x10 0x0>,
+ <0x2 0x10 0x1>,
+ <0x2 0x10 0x2>,
+ <0x2 0x10 0x3>,
+ <0x2 0x10 0x4>,
+ <0x2 0x10 0x5>,
+ <0x2 0x10 0x6>,
+ <0x2 0x10 0x7>;
+
+ interrupt-names = "chg-error",
+ "chg-inhibit",
+ "chg-prechg-sft",
+ "chg-complete-chg-sft",
+ "chg-p2f-thr",
+ "chg-rechg-thr",
+ "chg-taper-thr",
+ "chg-tcc-thr";
+ };
+
+ qcom,otg@1100 {
+ reg = <0x1100 0x100>;
+ interrupts = <0x2 0x11 0x0>,
+ <0x2 0x11 0x1>,
+ <0x2 0x11 0x3>;
+ interrupt-names = "otg-fail",
+ "otg-oc",
+ "usbid-change";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts = <0x2 0x12 0x0>,
+ <0x2 0x12 0x1>,
+ <0x2 0x12 0x2>,
+ <0x2 0x12 0x3>,
+ <0x2 0x12 0x4>,
+ <0x2 0x12 0x5>,
+ <0x2 0x12 0x6>,
+ <0x2 0x12 0x7>;
+
+ interrupt-names = "batt-hot",
+ "batt-warm",
+ "batt-cold",
+ "batt-cool",
+ "batt-ov",
+ "batt-low",
+ "batt-missing",
+ "batt-term-missing";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts = <0x2 0x13 0x0>,
+ <0x2 0x13 0x1>,
+ <0x2 0x13 0x2>,
+ <0x2 0x13 0x5>;
+
+ interrupt-names = "usbin-uv",
+ "usbin-ov",
+ "usbin-src-det",
+ "aicl-done";
+ };
+
+ qcom,dc-chgpth@1400 {
+ reg = <0x1400 0x100>;
+ interrupts = <0x2 0x14 0x0>,
+ <0x2 0x14 0x1>;
+ interrupt-names = "dcin-uv",
+ "dcin-ov";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x2 0x16 0x0>,
+ <0x2 0x16 0x1>,
+ <0x2 0x16 0x2>,
+ <0x2 0x16 0x3>,
+ <0x2 0x16 0x4>,
+ <0x2 0x16 0x5>;
+
+ interrupt-names = "power-ok",
+ "temp-shutdown",
+ "wdog-timeout",
+ "flash-fail",
+ "otst2",
+ "otst3";
+ };
+
+ smbcharger_charger_otg: qcom,smbcharger-boost-otg {
+ regulator-name = "smbcharger_charger_otg";
+ };
+ };
+
+ pmi8950_fg: qcom,fg {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-fg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,resume-soc = <95>;
+ status = "okay";
+ qcom,bcl-lm-threshold-ma = <127>;
+ qcom,bcl-mh-threshold-ma = <405>;
+ qcom,fg-iterm-ma = <150>;
+ qcom,fg-chg-iterm-ma = <100>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,fg-cutoff-voltage-mv = <3500>;
+ qcom,cycle-counter-en;
+ qcom,capacity-learning-on;
+
+ qcom,fg-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0>,
+ <0x2 0x40 0x1>,
+ <0x2 0x40 0x2>,
+ <0x2 0x40 0x3>,
+ <0x2 0x40 0x4>,
+ <0x2 0x40 0x5>,
+ <0x2 0x40 0x6>;
+
+ interrupt-names = "high-soc",
+ "low-soc",
+ "full-soc",
+ "empty-soc",
+ "delta-soc",
+ "first-est-done",
+ "update-soc";
+ };
+
+ qcom,fg-batt@4100 {
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0>,
+ <0x2 0x41 0x1>,
+ <0x2 0x41 0x2>,
+ <0x2 0x41 0x3>,
+ <0x2 0x41 0x4>,
+ <0x2 0x41 0x5>,
+ <0x2 0x41 0x6>,
+ <0x2 0x41 0x7>;
+
+ interrupt-names = "soft-cold",
+ "soft-hot",
+ "vbatt-low",
+ "batt-ided",
+ "batt-id-req",
+ "batt-unknown",
+ "batt-missing",
+ "batt-match";
+ };
+
+ qcom,revid-tp-rev@1f1 {
+ reg = <0x1f1 0x1>;
+ };
+
+ qcom,fg-memif@4400 {
+ status = "okay";
+ reg = <0x4400 0x100>;
+ interrupts = <0x2 0x44 0x0>,
+ <0x2 0x44 0x2>;
+
+ interrupt-names = "mem-avail",
+ "data-rcvry-sug";
+ };
+ };
+
+ bcl@4200 {
+ compatible = "qcom,msm-bcl";
+ reg = <0x4200 0xFF 0x88E 0x2>;
+ reg-names = "fg_user_adc", "pon_spare";
+ interrupts = <0x2 0x42 0x0>,
+ <0x2 0x42 0x1>;
+ interrupt-names = "bcl-high-ibat-int",
+ "bcl-low-vbat-int";
+ qcom,vbat-scaling-factor = <39000>;
+ qcom,vbat-gain-numerator = <1>;
+ qcom,vbat-gain-denominator = <128>;
+ qcom,vbat-polling-delay-ms = <100>;
+ qcom,ibat-scaling-factor = <39000>;
+ qcom,ibat-gain-numerator = <1>;
+ qcom,ibat-gain-denominator = <128>;
+ qcom,ibat-offset-numerator = <1200>;
+ qcom,ibat-offset-denominator = <1>;
+ qcom,ibat-polling-delay-ms = <100>;
+ qcom,inhibit-derating-ua = <550000>;
+ };
+
+ qcom,leds@a100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa100 0x100>;
+ label = "mpp";
+ };
+ };
+
+ qcom,pmi8950@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmi8950_pwm: pwm@b000 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xb000 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+
+ labibb: qpnp-labibb-regulator {
+ status = "disabled";
+ spmi-dev-container;
+ compatible = "qcom,qpnp-labibb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ ibb_regulator: qcom,ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_reg";
+ regulator-name = "ibb_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-ibb-min-voltage = <1400000>;
+ qcom,qpnp-ibb-step-size = <100000>;
+ qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-use-default-voltage;
+ qcom,qpnp-ibb-init-voltage = <5500000>;
+ qcom,qpnp-ibb-init-amoled-voltage = <4000000>;
+ qcom,qpnp-ibb-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-ibb-soft-start = <1000>;
+
+ qcom,qpnp-ibb-discharge-resistor = <32>;
+ qcom,qpnp-ibb-lab-pwrup-delay = <8000>;
+ qcom,qpnp-ibb-lab-pwrdn-delay = <8000>;
+ qcom,qpnp-ibb-en-discharge;
+
+ qcom,qpnp-ibb-full-pull-down;
+ qcom,qpnp-ibb-pull-down-enable;
+ qcom,qpnp-ibb-switching-clock-frequency =
+ <1480>;
+ qcom,qpnp-ibb-limit-maximum-current = <1550>;
+ qcom,qpnp-ibb-debounce-cycle = <16>;
+ qcom,qpnp-ibb-limit-max-current-enable;
+ qcom,qpnp-ibb-ps-enable;
+ };
+
+ lab_regulator: qcom,lab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "lab";
+ regulator-name = "lab_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-lab-min-voltage = <4600000>;
+ qcom,qpnp-lab-step-size = <100000>;
+ qcom,qpnp-lab-slew-rate = <5000>;
+ qcom,qpnp-lab-use-default-voltage;
+ qcom,qpnp-lab-init-voltage = <5500000>;
+ qcom,qpnp-lab-init-amoled-voltage = <4600000>;
+ qcom,qpnp-lab-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-lab-soft-start = <800>;
+
+ qcom,qpnp-lab-full-pull-down;
+ qcom,qpnp-lab-pull-down-enable;
+ qcom,qpnp-lab-switching-clock-frequency =
+ <1600>;
+ qcom,qpnp-lab-limit-maximum-current = <800>;
+ qcom,qpnp-lab-limit-max-current-enable;
+ qcom,qpnp-lab-ps-threshold = <40>;
+ qcom,qpnp-lab-ps-enable;
+ qcom,qpnp-lab-nfet-size = <100>;
+ qcom,qpnp-lab-pfet-size = <100>;
+ qcom,qpnp-lab-max-precharge-time = <500>;
+ };
+
+ };
+
+ wled: qcom,leds@d800 {
+ compatible = "qcom,qpnp-wled";
+ reg = <0xd800 0x100>,
+ <0xd900 0x100>,
+ <0xdc00 0x100>,
+ <0xde00 0x100>;
+ reg-names = "qpnp-wled-ctrl-base",
+ "qpnp-wled-sink-base",
+ "qpnp-wled-ibb-base",
+ "qpnp-wled-lab-base";
+ interrupts = <0x3 0xd8 0x2>;
+ interrupt-names = "sc-irq";
+ status = "okay";
+ linux,name = "wled";
+ linux,default-trigger = "bkl-trigger";
+ qcom,fdbk-output = "auto";
+ qcom,vref-mv = <350>;
+ qcom,switch-freq-khz = <800>;
+ qcom,ovp-mv = <29500>;
+ qcom,ilim-ma = <980>;
+ qcom,boost-duty-ns = <26>;
+ qcom,mod-freq-khz = <9600>;
+ qcom,dim-mode = "hybrid";
+ qcom,dim-method = "linear";
+ qcom,hyb-thres = <625>;
+ qcom,sync-dly-us = <800>;
+ qcom,fs-curr-ua = <20000>;
+ qcom,led-strings-list = [00 01];
+ qcom,en-ext-pfet-sc-pro;
+ qcom,cons-sync-write-delay-us = <1000>;
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ qcom,headroom = <500>;
+ qcom,startup-dly = <128>;
+ qcom,clamp-curr = <200>;
+ qcom,pmic-charger-support;
+ qcom,self-check-enabled;
+ qcom,thermal-derate-enabled;
+ qcom,thermal-derate-threshold = <100>;
+ qcom,thermal-derate-rate = "5_PERCENT";
+ qcom,current-ramp-enabled;
+ qcom,ramp_up_step = "6P7_US";
+ qcom,ramp_dn_step = "6P7_US";
+ qcom,vph-pwr-droop-enabled;
+ qcom,vph-pwr-droop-threshold = <3000>;
+ qcom,vph-pwr-droop-debounce-time = <10>;
+ qcom,headroom-sense-ch0-enabled;
+ qcom,headroom-sense-ch1-enabled;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ pmi8950_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,default-led-trigger =
+ "flash0_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <0>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,default-led-trigger =
+ "flash1_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <1>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,default-led-trigger =
+ "torch0_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <0>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,default-led-trigger =
+ "torch1_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <1>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_switch: qcom,switch {
+ label = "switch";
+ qcom,led-name = "led:switch";
+ qcom,default-led-trigger =
+ "switch_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <2>;
+ qcom,current = <625>;
+ reg0 {
+ regulator-name = "pon_spare_reg";
+ };
+ };
+ };
+
+ pmi_haptic: qcom,haptic@c000 {
+ compatible = "qcom,qpnp-haptic";
+ reg = <0xc000 0x100>;
+ interrupts = <0x3 0xc0 0x0>,
+ <0x3 0xc0 0x1>;
+ interrupt-names = "sc-irq", "play-irq";
+ qcom,pmic-revid = <&pmi8950_revid>;
+ vcc_pon-supply = <&pon_perph_reg>;
+ qcom,play-mode = "direct";
+ qcom,wave-play-rate-us = <5263>;
+ qcom,actuator-type = "erm";
+ qcom,wave-shape = "square";
+ qcom,vmax-mv = <2000>;
+ qcom,ilim-ma = <800>;
+ qcom,sc-deb-cycles = <8>;
+ qcom,int-pwm-freq-khz = <505>;
+ qcom,en-brake;
+ qcom,brake-pattern = [03 03 00 00];
+ qcom,use-play-irq;
+ qcom,use-sc-irq;
+ qcom,wave-samples = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wave-rep-cnt = <1>;
+ qcom,wave-samp-rep-cnt = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts b/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts
new file mode 100644
index 0000000..f836f50
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts
@@ -0,0 +1,29 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sda845-v2-hdk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA845 v2 HDK";
+ compatible = "qcom,sda845-hdk", "qcom,sda845", "qcom,hdk";
+ qcom,msm-id = <341 0x20000>;
+ qcom,board-id = <0x01001F 0x00>;
+};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
index 71b21b9..17f8324 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
@@ -10,19 +10,14 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
+/dts-v1/;
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
+#include "sda845-v2.dtsi"
+#include "sda845-v2-hdk.dtsi"
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDA845 HDK";
+ compatible = "qcom,sda845-hdk", "qcom,sda845", "qcom,hdk";
+ qcom,board-id = <0x01001F 0x00>;
};
-
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
index 71b21b9..a8ff041 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
@@ -10,19 +10,10 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+#include "sdm845-qvr.dtsi"
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+&vendor {
+ qcom,battery-data {
+ #include "fg-gen3-batterydata-mlp356477-2800mah.dtsi"
+ };
};
-
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index a1f5262..e135a3d 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -56,7 +56,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_0>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -75,11 +75,11 @@
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_0: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -92,7 +92,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_100>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -106,11 +106,11 @@
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_100: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -123,7 +123,7 @@
reg = <0x0 0x200>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_200>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -137,11 +137,11 @@
};
L1_I_200: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_200: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_200: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -154,7 +154,7 @@
reg = <0x0 0x300>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_300>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -168,11 +168,11 @@
};
L1_I_300: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_300: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_300: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -185,7 +185,7 @@
reg = <0x0 0x400>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_400>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -199,11 +199,11 @@
};
L1_I_400: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_400: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_400: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -216,7 +216,7 @@
reg = <0x0 0x500>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_500>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -230,11 +230,11 @@
};
L1_I_500: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_500: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_500: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -247,7 +247,7 @@
reg = <0x0 0x600>;
enable-method = "psci";
efficiency = <1740>;
- cache-size = <0x10000>;
+ cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_600>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -261,11 +261,11 @@
};
L1_I_600: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x24000>;
};
L1_D_600: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x14000>;
};
L1_TLB_600: l1-tlb {
qcom,dump-size = <0x3c000>;
@@ -278,7 +278,7 @@
reg = <0x0 0x700>;
enable-method = "psci";
efficiency = <1740>;
- cache-size = <0x10000>;
+ cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_700>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -292,11 +292,11 @@
};
L1_I_700: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x24000>;
};
L1_D_700: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x14000>;
};
L1_TLB_700: l1-tlb {
qcom,dump-size = <0x3c000>;
@@ -830,6 +830,29 @@
qcom,qsee-reentrancy-support = <2>;
};
+ qcom_tzlog: tz-log@146bf720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146bf720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_rng: qrng@793000{
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 800>; /* 100 KHz */
+ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
thermal_zones: thermal-zones {};
tsens0: tsens@c222000 {
@@ -1056,7 +1079,7 @@
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 291 0>, <0 292 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
- status = "disabled";
+ status = "ok";
qcom,iommu-s1-bypass;
iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
@@ -1064,6 +1087,13 @@
iommus = <&apps_smmu 0x1833 0x0>;
};
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
};
wdog: qcom,wdt@17980000{
@@ -2031,7 +2061,7 @@
qcom,ssctl-instance-id = <0x12>;
qcom,override-acc;
qcom,qdsp6v65-1-0;
- qcom,mss_pdc_offset = <8>;
+ qcom,mss_pdc_offset = <9>;
status = "ok";
memory-region = <&pil_modem_mem>;
qcom,mem-protect-id = <0xF>;
@@ -2321,6 +2351,12 @@
iommus = <&apps_smmu 0x1805 0x0>;
dma-coherent;
};
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1806 0x0>;
+ dma-coherent;
+ };
};
bluetooth: bt_wcn3990 {
@@ -2407,7 +2443,7 @@
< MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
};
- memlat_cpu4: qcom,memlat-cpu4 {
+ memlat_cpu6: qcom,memlat-cpu6 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
@@ -2429,9 +2465,9 @@
devfreq_memlat_0: qcom,cpu0-memlat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&memlat_cpu0>;
- qcom,cachemiss-ev = <0x24>;
+ qcom,cachemiss-ev = <0x2a>;
qcom,core-dev-table =
< 748800 MHZ_TO_MBPS( 300, 4) >,
< 998400 MHZ_TO_MBPS( 451, 4) >,
@@ -2440,11 +2476,11 @@
< 1728000 MHZ_TO_MBPS(1017, 4) >;
};
- devfreq_memlat_4: qcom,cpu4-memlat-mon {
+ devfreq_memlat_6: qcom,cpu6-memlat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
- qcom,target-dev = <&memlat_cpu4>;
- qcom,cachemiss-ev = <0x24>;
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&memlat_cpu6>;
+ qcom,cachemiss-ev = <0x2a>;
qcom,core-dev-table =
< 787200 MHZ_TO_MBPS( 300, 4) >,
< 1113600 MHZ_TO_MBPS( 547, 4) >,
@@ -2460,7 +2496,7 @@
governor = "performance";
};
- l3_cpu4: qcom,l3-cpu4 {
+ l3_cpu6: qcom,l3-cpu6 {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
@@ -2469,7 +2505,7 @@
devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&l3_cpu0>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table =
@@ -2481,10 +2517,10 @@
< 1728000 1440000000 >;
};
- devfreq_l3lat_4: qcom,cpu4-l3lat-mon {
+ devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
- qcom,target-dev = <&l3_cpu4>;
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&l3_cpu6>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table =
< 1113600 566400000 >,
@@ -2521,7 +2557,7 @@
< 1209600 MHZ_TO_MBPS( 451, 4) >,
< 1612000 MHZ_TO_MBPS( 547, 4) >,
< 1728000 MHZ_TO_MBPS( 768, 4) >;
- cpu-to-dev-map-4 =
+ cpu-to-dev-map-6 =
< 1113600 MHZ_TO_MBPS( 300, 4) >,
< 1344000 MHZ_TO_MBPS( 547, 4) >,
< 1728000 MHZ_TO_MBPS( 768, 4) >,
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
index 04418d4..dc520a9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
@@ -122,8 +122,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
@@ -165,8 +166,9 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vdig", "cam_vio", "cam_vana",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <1050000 0 3312000 0>;
rgltr-max-voltage = <1050000 0 3600000 0>;
@@ -179,14 +181,17 @@
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
- <&tlmm 8 0>;
+ <&tlmm 8 0>,
+ <&tlmm 27 0>;
gpio-reset = <1>;
gpio-vana = <2>;
- gpio-req-tbl-num = <0 1 2>;
- gpio-req-tbl-flags = <1 0 0>;
+ gpio-vaf = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
- "CAM_VANA1";
+ "CAM_VANA1",
+ "CAM_VAF";
sensor-position = <0>;
sensor-mode = <0>;
cci-master = <1>;
@@ -205,8 +210,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
index 9088fac..b723802 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
@@ -122,8 +122,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
@@ -165,8 +166,9 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vdig", "cam_vio", "cam_vana",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <1050000 0 3312000 0>;
rgltr-max-voltage = <1050000 0 3600000 0>;
@@ -179,14 +181,17 @@
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
- <&tlmm 8 0>;
+ <&tlmm 8 0>,
+ <&tlmm 27 0>;
gpio-reset = <1>;
gpio-vana = <2>;
- gpio-req-tbl-num = <0 1 2>;
- gpio-req-tbl-flags = <1 0 0>;
+ gpio-vaf = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
- "CAM_VANA1";
+ "CAM_VANA1",
+ "CAM_VAF";
sensor-position = <0>;
sensor-mode = <0>;
cci-master = <1>;
@@ -205,8 +210,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index 7c9482c..744d021 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -28,7 +28,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -62,7 +62,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -97,7 +97,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
index cc609aa..fbda72c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
@@ -230,6 +230,10 @@
&soc {
/delete-node/ gpio_keys;
+ qcom,mss@4080000 {
+ /delete-property/ vdd_mss-supply;
+ };
+
qcom,lpass@17300000 {
/delete-property/ vdd_cx-supply;
};
@@ -325,8 +329,6 @@
&soc {
/* Delete all regulators */
- /delete-node/ cprh-ctrl@17dc0000;
- /delete-node/ cprh-ctrl@17db0000;
/delete-node/ rpmh-regulator-ebilvl;
/delete-node/ rpmh-regulator-smpa2;
/delete-node/ rpmh-regulator-smpa3;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
index d22c28a..f09efd4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
@@ -29,690 +29,7 @@
};
};
-&spmi_bus {
- qcom,pm8998@1 {
- /* PM8998 S12 + S11 + S10 = VDD_APC1 supply */
- pm8998_s12: regulator@3500 {
- compatible = "qcom,qpnp-regulator";
- reg = <0x3500 0x100>;
- regulator-name = "pm8998_s12";
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1136000>;
- qcom,enable-time = <500>;
- regulator-always-on;
- };
-
- /* PM8998 S13 = VDD_APC0 supply */
- pm8998_s13: regulator@3800 {
- compatible = "qcom,qpnp-regulator";
- reg = <0x3800 0x100>;
- regulator-name = "pm8998_s13";
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <996000>;
- qcom,enable-time = <500>;
- regulator-always-on;
- };
- };
-};
-
&soc {
- /* CPR controller regulators */
- apc0_cpr: cprh-ctrl@17dc0000 {
- compatible = "qcom,cprh-sdm845-v1-kbss-regulator";
- reg = <0x17dc0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17840000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc0";
- qcom,cpr-controller-id = <0>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <11>;
- qcom,cpr-step-quot-init-max = <12>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x3A003A0>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17dc3a84 0x17dc3a88 0x17840c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_SILVER_CPRH_STATUS_0",
- "APSS_SILVER_CPRH_STATUS_1",
- "SILVER_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <996000>;
- vdd-supply = <&pm8998_s13>;
-
- thread@1 {
- qcom,cpr-thread-id = <1>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_pwrcl_vreg: regulator {
- regulator-name = "apc0_pwrcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <19>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <19 19 19>;
- qcom,cpr-corners = <19>;
-
- qcom,cpr-corner-fmax-map = <6 12 17 19>;
-
- qcom,cpr-voltage-ceiling =
- <872000 872000 872000 872000 872000
- 872000 872000 872000 872000 872000
- 872000 872000 872000 872000 872000
- 872000 928000 996000 996000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 996000 996000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1651200000
- 1708800000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1651200000
- 1708800000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1670400000
- 1747200000>;
-
- qcom,cpr-ro-scaling-factor =
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <19>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_l3_vreg: regulator {
- regulator-name = "apc0_l3_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <13>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <11 11 13>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <11 11 11 11 11 11 11 11>,
- /* Speed bin 1 */
- <11 11 11 11 11 11 11 11>,
- /* Speed bin 2 */
- <13 13 13 13 13 13 13 13>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <4 7 9 11>,
- /* Speed bin 1 */
- <4 7 9 11>,
- /* Speed bin 2 */
- <4 7 9 13>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000>,
- /* Speed bin 1 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000>,
- /* Speed bin 2 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000 996000 996000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 996000
- 996000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1094400000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1094400000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1209600000
- 1305600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <11 11 13>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
- apc1_cpr: cprh-ctrl@17db0000 {
- compatible = "qcom,cprh-sdm845-v1-kbss-regulator";
- reg = <0x17db0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17830000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc1";
- qcom,cpr-controller-id = <1>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <9>;
- qcom,cpr-step-quot-init-max = <14>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,apm-threshold-voltage = <800000>;
- qcom,apm-crossover-voltage = <880000>;
- qcom,mem-acc-threshold-voltage = <852000>;
- qcom,mem-acc-crossover-voltage = <852000>;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x4200420>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17db3a84 0x17830c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1136000>;
- vdd-supply = <&pm8998_s12>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc1_perfcl_vreg: regulator {
- regulator-name = "apc1_perfcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <27>;
-
- qcom,cpr-fuse-corners = <3>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <22 24 25>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <22 22 22 22 22 22 22 22>,
- /* Speed bin 1 */
- <24 24 24 24 24 24 24 24>,
- /* Speed bin 2 */
- <25 25 25 25 25 25 25 25>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <10 17 22>,
- /* Speed bin 1 */
- <10 17 24>,
- /* Speed bin 2 */
- <10 17 25>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000 1136000 1136000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000 1136000 1136000
- 1136000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000 2035200000 2092800000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000 2035200000 2112000000
- 2208000000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <22 24 25>;
- qcom,cpr-aging-ro-scaling-factor = <1700>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
/* RPMh regulators: */
/* PM8998 S1 = VDD_EBI supply */
diff --git a/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi b/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
index d607f75..34de0a0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
@@ -132,14 +132,6 @@
};
};
-&apc0_cpr {
- qcom,cpr-ignore-invalid-fuses;
-};
-
-&apc1_cpr {
- qcom,cpr-ignore-invalid-fuses;
-};
-
&pmi8998_charger {
qcom,suspend-input;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index e7a946c..a52e269 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -207,6 +207,9 @@
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040000>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts
new file mode 100644
index 0000000..b7bc3dc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts
@@ -0,0 +1,66 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-cdp.dtsi"
+#include "sdm845-cdp-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel CDP";
+ compatible = "qcom,sdm845-cdp", "qcom,sdm845", "qcom,cdp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <1 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_rscc &sde_wb>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts
new file mode 100644
index 0000000..95bd94b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts
@@ -0,0 +1,66 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-mtp.dtsi"
+#include "sdm845-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel MTP";
+ compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <8 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_rscc &sde_wb &sde_dp>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts
new file mode 100644
index 0000000..42ccbf5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts
@@ -0,0 +1,64 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-qrd.dtsi"
+#include "sdm845-qrd-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel QRD";
+ compatible = "qcom,sdm845-qrd", "qcom,sdm845", "qcom,qrd";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <11 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,mdss-dsi-panel-orientation = "180";
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,mdss-dsi-panel-orientation = "180";
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts
new file mode 100644
index 0000000..0825f4b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-cdp.dtsi"
+#include "sdm845-cdp-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 CDP";
+ compatible = "qcom,sdm845-cdp", "qcom,sdm845", "qcom,cdp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <1 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts
new file mode 100644
index 0000000..7b3573a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-mtp.dtsi"
+#include "sdm845-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 MTP";
+ compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts
new file mode 100644
index 0000000..15d79c2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-qrd.dtsi"
+#include "sdm845-qrd-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 QRD";
+ compatible = "qcom,sdm845-qrd", "qcom,sdm845", "qcom,qrd";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <11 0>;
+};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
similarity index 61%
rename from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
rename to arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
index 71b21b9..2902a60 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
@@ -10,19 +10,13 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+/dts-v1/;
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
+#include "sdm845-v2.1.dtsi"
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 SoC";
+ compatible = "qcom,sdm845";
+ qcom,board-id = <0 0>;
};
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
index 71b21b9..018a330 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
@@ -10,19 +10,11 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+#include "sdm845-v2.dtsi"
+#include "sdm845-v2-camera.dtsi"
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 V2.1";
+ qcom,msm-id = <321 0x20001>;
};
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
index b3cb8f5..9343e2a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
@@ -22,674 +22,11 @@
/delete-property/ qcom,sdr104-wa;
};
-/delete-node/ &apc0_cpr;
-/delete-node/ &apc1_cpr;
-
&tlmm {
compatible = "qcom,sdm845-pinctrl-v2";
};
&soc {
- /* CPR controller regulators */
- apc0_cpr: cprh-ctrl@17dc0000 {
- compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
- reg = <0x17dc0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17840000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc0";
- qcom,cpr-controller-id = <0>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <11>;
- qcom,cpr-step-quot-init-max = <12>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x3E803E8>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17dc3a84 0x17dc3a88 0x17840c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_SILVER_CPRH_STATUS_0",
- "APSS_SILVER_CPRH_STATUS_1",
- "SILVER_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1000000>;
- vdd-supply = <&pm8998_s13>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_pwrcl_vreg: regulator {
- regulator-name = "apc0_pwrcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <18>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <18 18 18>;
- qcom,cpr-corners = <18>;
-
- qcom,cpr-corner-fmax-map = <6 12 15 18>;
-
- qcom,cpr-voltage-ceiling =
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 932000 1000000 1000000>;
-
- qcom,cpr-voltage-floor =
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 40000 40000>;
-
- qcom,corner-frequencies =
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1228800000
- 1324800000 1420800000 1516800000
- 1612800000 1689600000 1766400000>;
-
- qcom,cpr-ro-scaling-factor =
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- /* Speed bin 1 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- /* Speed bin 2 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- /* Speed bin 1 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- /* Speed bin 2 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <18>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
-
- thread@1 {
- qcom,cpr-thread-id = <1>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_l3_vreg: regulator {
- regulator-name = "apc0_l3_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <15>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <14 15 15>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <14 14 14 14 14 14 14 14>,
- /* Speed bin 1 */
- <15 15 15 15 15 15 15 15>,
- /* Speed bin 2 */
- <15 15 15 15 15 15 15 15>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <4 8 11 14>,
- /* Speed bin 1 */
- <4 8 11 15>,
- /* Speed bin 2 */
- <4 8 11 15>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000
- 1000000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000
- 1000000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1478400000>,
- /* Speed bin 1 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1497600000 1593600000>,
- /* Speed bin 2 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1497600000 1593600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- /* Speed bin 1 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- /* Speed bin 2 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- /* Speed bin 1 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- /* Speed bin 2 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <14 15 15>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
- apc1_cpr: cprh-ctrl@17db0000 {
- compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
- reg = <0x17db0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17830000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc1";
- qcom,cpr-controller-id = <1>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <9>;
- qcom,cpr-step-quot-init-max = <14>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,apm-threshold-voltage = <800000>;
- qcom,apm-crossover-voltage = <880000>;
- qcom,mem-acc-threshold-voltage = <852000>;
- qcom,mem-acc-crossover-voltage = <852000>;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x4880488>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17db3a84 0x17830c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1160000>;
- vdd-supply = <&pm8998_s12>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc1_perfcl_vreg: regulator {
- regulator-name = "apc1_perfcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <35>;
-
- qcom,cpr-fuse-corners = <5>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <28 31 33>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <28 28 28 28 28 28 28 28>,
- /* Speed bin 1 */
- <31 31 31 31 31 31 31 31>,
- /* Speed bin 2 */
- <33 33 33 33 33 33 33 33>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <7 14 22 27 28>,
- /* Speed bin 1 */
- <7 14 22 27 31>,
- /* Speed bin 2 */
- <7 14 22 30 33>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000 1160000 1160000
- 1160000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000 1160000 1160000
- 1160000 1160000 1160000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2400000000>,
- /* Speed bin 1 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2476800000 2553600000 2649600000
- 2707200000>,
- /* Speed bin 2 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2476800000 2553600000 2649600000
- 2707200000 2726400000 2745600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 8000 8000 8000 0 0>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- /* Speed bin 1 */
- < 8000 8000 8000 0 16000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- /* Speed bin 2 */
- < 8000 8000 8000 0 16000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 6000 6000 8000 0 0>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- /* Speed bin 1 */
- < 6000 6000 8000 0 16000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- /* Speed bin 2 */
- < 6000 6000 8000 0 16000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <27 31 33>;
- qcom,cpr-aging-ro-scaling-factor = <1700>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
gpu_gx_domain_addr: syscon@0x5091508 {
compatible = "syscon";
reg = <0x5091508 0x4>;
@@ -705,244 +42,8 @@
qcom,mss_pdc_offset = <9>;
};
-/* VDD_APC0 */
-&pm8998_s13 {
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1000000>;
-};
-
-/* VDD_APC1 */
-&pm8998_s12 {
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1160000>;
-};
-
&clock_cpucc {
compatible = "qcom,clk-cpu-osm-v2";
-
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
-
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
-
- qcom,l3-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
- < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
-
- qcom,l3-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
- < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,pwrcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,pwrcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
-
- qcom,perfcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
- < 2476800000 0x40541b81 0x00006767 0x2 28 >,
- < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
- < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
- < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
-
- qcom,perfcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
- < 2476800000 0x40541b81 0x00006767 0x2 28 >,
- < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
- < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
- < 2707200000 0x40511e8d 0x00007171 0x2 30 >,
- < 2764800000 0x40511f90 0x00007373 0x2 31 >,
- < 2784000000 0x40512091 0x00007474 0x2 32 >,
- < 2803200000 0x40512192 0x00007575 0x2 33 >;
-
- qcom,l3-memacc-level-vc-bin0 = <8 13>;
- qcom,l3-memacc-level-vc-bin1 = <8 13>;
- qcom,l3-memacc-level-vc-bin2 = <8 13>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 16>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
- qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
- qcom,perfcl-memacc-level-vc-bin2 = <14 22>;
};
&pcie1 {
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 114178d..007f231 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1207,267 +1207,15 @@
compatible = "qcom,clk-cpu-osm";
reg = <0x17d41000 0x1400>,
<0x17d43000 0x1400>,
- <0x17d45800 0x1400>,
- <0x178d0000 0x1000>,
- <0x178c0000 0x1000>,
- <0x178b0000 0x1000>,
- <0x17d42400 0x0c00>,
- <0x17d44400 0x0c00>,
- <0x17d46c00 0x0c00>,
- <0x00784130 0x4>,
- <0x00784130 0x4>,
- <0x00784130 0x4>;
- reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
- "l3_pll", "pwrcl_pll", "perfcl_pll", "l3_sequencer",
- "pwrcl_sequencer", "perfcl_sequencer", "l3_efuse",
- "pwrcl_efuse", "perfcl_efuse";
-
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
+ <0x17d45800 0x1400>;
+ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
l3-dev0 = <&l3_cpu0>;
l3-dev4 = <&l3_cpu4>;
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >;
-
- qcom,l3-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1094400000 0x402c0a39 0x00002e2e 0x1 11 >;
-
- qcom,l3-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1305600000 0x40340c44 0x00003636 0x1 13 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >;
-
- qcom,pwrcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1708800000 0x40441259 0x00004747 0x1 19 >;
-
- qcom,pwrcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >,
- < 1670400000 0x40441157 0x00004646 0x1 18 >,
- < 1747200000 0x4044125b 0x00004949 0x1 19 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >;
-
- qcom,perfcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >,
- < 2035200000 0x404c166a 0x00005555 0x1 23 >,
- < 2092800000 0x4054176d 0x00005757 0x1 24 >;
-
- qcom,perfcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >,
- < 2035200000 0x404c166a 0x00005555 0x1 23 >,
- < 2112000000 0x4054176e 0x00005858 0x1 24 >,
- < 2208000000 0x40541873 0x00005c5c 0x1 25 >;
-
- qcom,l3-memacc-level-vc-bin0 = <7 63>;
- qcom,l3-memacc-level-vc-bin1 = <7 9>;
- qcom,l3-memacc-level-vc-bin2 = <7 9>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 63>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 17>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 17>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin1 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin2 = <12 18>;
-
- qcom,up-timer =
- <1000 1000 1000>;
- qcom,down-timer =
- <100000 100000 100000>;
- qcom,set-ret-inactive;
- qcom,enable-llm-freq-vote;
- qcom,llm-freq-up-timer =
- <1000 1000 1000>;
- qcom,llm-freq-down-timer =
- <327675 327675 327675>;
- qcom,enable-llm-volt-vote;
- qcom,llm-volt-up-timer =
- <1000 1000 1000>;
- qcom,llm-volt-down-timer =
- <327675 327675 327675>;
- qcom,cc-reads = <10>;
- qcom,cc-delay = <5>;
- qcom,cc-factor = <100>;
- qcom,osm-clk-rate = <100000000>;
- qcom,xo-clk-rate = <19200000>;
-
- qcom,l-val-base =
- <0x178d0004 0x178c0004 0x178b0004>;
- qcom,apcs-pll-user-ctl =
- <0x178d000c 0x178c000c 0x178b000c>;
- qcom,apcs-pll-min-freq =
- <0x17d41094 0x17d43094 0x17d45894>;
- qcom,apm-mode-ctl =
- <0x0 0x0 0x17d20010>;
- qcom,apm-status-ctrl =
- <0x0 0x0 0x17d20000>;
- qcom,perfcl-isense-addr = <0x17871480>;
- qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>;
- qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>;
- qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>;
- qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>;
- qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>;
- qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>;
-
- qcom,perfcl-apcs-apm-threshold-voltage = <800000>;
- qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>;
- qcom,boost-fsm-en;
- qcom,safe-fsm-en;
- qcom,ps-fsm-en;
- qcom,droop-fsm-en;
-
clock-names = "xo_ao";
clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
#clock-cells = <1>;
- #reset-cells = <1>;
};
clock_debug: qcom,cc-debug@100000 {
@@ -1728,6 +1476,8 @@
vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
vdd_mx-supply = <&pm8998_s6_level>;
vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
+ vdd_mss-supply = <&pm8005_s2_level>;
+ vdd_mss-uV = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sysmon-id = <0>;
@@ -2798,6 +2548,7 @@
reg = <0x0 0x200000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
};
qcom,rmnet-ipa {
diff --git a/arch/arm64/configs/sdm670-perf_defconfig b/arch/arm64/configs/sdm670-perf_defconfig
index 485ab7e..fa397c8 100644
--- a/arch/arm64/configs/sdm670-perf_defconfig
+++ b/arch/arm64/configs/sdm670-perf_defconfig
@@ -530,7 +530,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QMP_DEBUGFS_CLIENT=y
diff --git a/arch/arm64/configs/sdm670_defconfig b/arch/arm64/configs/sdm670_defconfig
index b0d0807..c4295db 100644
--- a/arch/arm64/configs/sdm670_defconfig
+++ b/arch/arm64/configs/sdm670_defconfig
@@ -447,8 +447,6 @@
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_KRYO3XX_ARM64=y
CONFIG_EDAC_KRYO3XX_ARM64_PANIC_ON_UE=y
-CONFIG_EDAC_QCOM_LLCC=y
-CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
CONFIG_DMADEVICES=y
@@ -537,7 +535,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QCOM_DCC_V2=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index 3c5b65c..efdbfb4 100644
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -344,7 +344,6 @@
CONFIG_MFD_SPMI_PMIC=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
-CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_QPNP_LABIBB=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_REFGEN=y
@@ -527,7 +526,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QMP_DEBUGFS_CLIENT=y
diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig
index 09f81c0..8aede6e 100644
--- a/arch/arm64/configs/sdm845_defconfig
+++ b/arch/arm64/configs/sdm845_defconfig
@@ -352,7 +352,6 @@
CONFIG_MFD_SPMI_PMIC=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
-CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_QPNP_LABIBB=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_REFGEN=y
@@ -545,7 +544,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QCOM_DCC_V2=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index 876ed90..9e762d9 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -61,6 +61,7 @@
#define M_FDLIST (16)
#define M_CRCLIST (64)
#define SESSION_ID_INDEX (30)
+#define FASTRPC_CTX_MAGIC (0xbeeddeed)
#define IS_CACHE_ALIGNED(x) (((x) & ((L1_CACHE_BYTES)-1)) == 0)
@@ -76,6 +77,9 @@
#define FASTRPC_STATIC_HANDLE_MAX (20)
#define FASTRPC_LATENCY_CTRL_ENB (1)
+#define INIT_FILELEN_MAX (2*1024*1024)
+#define INIT_MEMLEN_MAX (8*1024*1024)
+
#define PERF_END (void)0
#define PERF(enb, cnt, ff) \
@@ -176,6 +180,7 @@
struct overlap **overps;
struct smq_msg msg;
uint32_t *crc;
+ unsigned int magic;
};
struct fastrpc_ctx_lst {
@@ -864,6 +869,7 @@
ctx->pid = current->pid;
ctx->tgid = fl->tgid;
init_completion(&ctx->work);
+ ctx->magic = FASTRPC_CTX_MAGIC;
spin_lock(&fl->hlock);
hlist_add_head(&ctx->hn, &clst->pending);
@@ -899,6 +905,7 @@
for (i = 0; i < nbufs; ++i)
fastrpc_mmap_free(ctx->maps[i]);
fastrpc_buf_free(ctx->buf, 1);
+ ctx->magic = 0;
kfree(ctx);
}
@@ -1089,9 +1096,10 @@
list[i].pgidx = ipage - pages;
ipage++;
}
+
/* map ion buffers */
PERF(ctx->fl->profile, ctx->fl->perf.map,
- for (i = 0; i < inbufs + outbufs; ++i) {
+ for (i = 0; rpra && i < inbufs + outbufs; ++i) {
struct fastrpc_mmap *map = ctx->maps[i];
uint64_t buf = ptr_to_uint64(lpra[i].buf.pv);
ssize_t len = lpra[i].buf.len;
@@ -1199,7 +1207,7 @@
uint64_to_ptr(rpra[i].buf.pv + rpra[i].buf.len));
}
PERF_END);
- for (i = bufs; i < bufs + handles; i++) {
+ for (i = bufs; rpra && i < bufs + handles; i++) {
rpra[i].dma.fd = ctx->fds[i];
rpra[i].dma.len = (uint32_t)lpra[i].buf.len;
rpra[i].dma.offset = (uint32_t)(uintptr_t)lpra[i].buf.pv;
@@ -1487,8 +1495,7 @@
if (fl->profile && !interrupted) {
if (invoke->handle != FASTRPC_STATIC_HANDLE_LISTENER)
fl->perf.invoke += getnstimediff(&invoket);
- if (!(invoke->handle >= 0 &&
- invoke->handle <= FASTRPC_STATIC_HANDLE_MAX))
+ if (invoke->handle > FASTRPC_STATIC_HANDLE_MAX)
fl->perf.count++;
}
return err;
@@ -1547,6 +1554,7 @@
if (err)
goto bail;
}
+
inbuf.pageslen = 1;
VERIFY(err, !fastrpc_mmap_create(fl, init->memfd, 0,
init->mem, init->memlen, mflags, &mem));
@@ -1822,64 +1830,26 @@
{
}
-static int fastrpc_search_ctx(uint64_t rctx)
-{
- struct fastrpc_apps *me = &gfa;
- struct fastrpc_file *fl;
- struct hlist_node *n, *m;
- struct smq_invoke_ctx *ictx = NULL;
- struct smq_invoke_ctx *ctx;
- int bfound = 0;
- unsigned long flags;
- unsigned long flags1;
-
- ctx = (struct smq_invoke_ctx *)(uint64_to_ptr(rctx));
- if (!ctx)
- return bfound;
-
- spin_lock_irqsave(&me->hlock, flags);
- hlist_for_each_entry_safe(fl, n, &me->drivers, hn) {
- if (ctx->fl != fl)
- continue;
- spin_lock_irqsave(&fl->hlock, flags1);
- hlist_for_each_entry_safe(ictx, m, &fl->clst.pending, hn) {
- if (ptr_to_uint64(ictx) == rctx) {
- bfound = 1;
- break;
- }
- }
- hlist_for_each_entry_safe(ictx, m, &fl->clst.interrupted, hn) {
- if (ptr_to_uint64(ictx) == rctx) {
- bfound = 1;
- break;
- }
- }
- spin_unlock_irqrestore(&fl->hlock, flags1);
- if (bfound)
- break;
- }
- spin_unlock_irqrestore(&me->hlock, flags);
- return bfound;
-}
-
void fastrpc_glink_notify_rx(void *handle, const void *priv,
const void *pkt_priv, const void *ptr, size_t size)
{
struct smq_invoke_rsp *rsp = (struct smq_invoke_rsp *)ptr;
- int bfound = 0;
+ struct smq_invoke_ctx *ctx;
+ int err = 0;
- if (!rsp || (size < sizeof(*rsp)))
+ VERIFY(err, (rsp && size >= sizeof(*rsp)));
+ if (err)
goto bail;
- bfound = fastrpc_search_ctx((uint64_t)(rsp->ctx & ~1));
- if (!bfound) {
- pr_err("adsprpc: invalid context %pK\n", (void *)rsp->ctx);
+ ctx = (struct smq_invoke_ctx *)(uint64_to_ptr(rsp->ctx & ~1));
+ VERIFY(err, (ctx && ctx->magic == FASTRPC_CTX_MAGIC));
+ if (err)
goto bail;
- }
- rsp->ctx = rsp->ctx & ~1;
- context_notify_user(uint64_to_ptr(rsp->ctx), rsp->retval);
+ context_notify_user(ctx, rsp->retval);
bail:
+ if (err)
+ pr_err("adsprpc: invalid response or context\n");
glink_rx_done(handle, ptr, true);
}
@@ -2416,6 +2386,13 @@
sizeof(p.mmap)));
if (err)
goto bail;
+
+ VERIFY(err, !IS_ERR_OR_NULL(p.mmap.vaddrin));
+ if (err)
+ goto bail;
+ VERIFY(err, p.mmap.size > 0);
+ if (err)
+ goto bail;
VERIFY(err, 0 == (err = fastrpc_internal_mmap(fl, &p.mmap)));
if (err)
goto bail;
@@ -2428,6 +2405,13 @@
sizeof(p.munmap)));
if (err)
goto bail;
+ VERIFY(err, !IS_ERR_OR_NULL(
+ uint64_to_ptr((uint64_t)p.munmap.vaddrout)));
+ if (err)
+ goto bail;
+ VERIFY(err, p.munmap.size > 0);
+ if (err)
+ goto bail;
VERIFY(err, 0 == (err = fastrpc_internal_munmap(fl,
&p.munmap)));
if (err)
@@ -2505,7 +2489,11 @@
if (err)
goto bail;
VERIFY(err, p.init.init.filelen >= 0 &&
- p.init.init.memlen >= 0);
+ p.init.init.filelen < INIT_FILELEN_MAX);
+ if (err)
+ goto bail;
+ VERIFY(err, p.init.init.memlen >= 0 &&
+ p.init.init.memlen < INIT_MEMLEN_MAX);
if (err)
goto bail;
VERIFY(err, 0 == fastrpc_init_process(fl, &p.init));
diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c
index e2d39e7..0aad08a 100644
--- a/drivers/char/diag/diag_dci.c
+++ b/drivers/char/diag/diag_dci.c
@@ -134,6 +134,35 @@
void diag_dci_record_traffic(int read_bytes, uint8_t ch_type,
uint8_t peripheral, uint8_t proc) { }
#endif
+
+static int check_peripheral_dci_support(int peripheral_id, int dci_proc_id)
+{
+ int dci_peripheral_list = 0;
+
+ if (dci_proc_id < 0 || dci_proc_id >= NUM_DCI_PROC) {
+ pr_err("diag:In %s,not a supported DCI proc id\n", __func__);
+ return 0;
+ }
+ if (peripheral_id < 0 || peripheral_id >= NUM_PERIPHERALS) {
+ pr_err("diag:In %s,not a valid peripheral id\n", __func__);
+ return 0;
+ }
+ dci_peripheral_list = dci_ops_tbl[dci_proc_id].peripheral_status;
+
+ if (dci_peripheral_list <= 0 || dci_peripheral_list > DIAG_CON_ALL) {
+ pr_err("diag:In %s,not a valid dci peripheral mask\n",
+ __func__);
+ return 0;
+ }
+ /* Remove APSS bit mask information */
+ dci_peripheral_list = dci_peripheral_list >> 1;
+
+ if ((1 << peripheral_id) & (dci_peripheral_list))
+ return 1;
+ else
+ return 0;
+}
+
static void create_dci_log_mask_tbl(unsigned char *mask, uint8_t dirty)
{
unsigned char *temp = mask;
@@ -1440,6 +1469,8 @@
struct siginfo info;
struct list_head *start, *temp;
struct diag_dci_client_tbl *entry = NULL;
+ struct pid *pid_struct = NULL;
+ struct task_struct *dci_task = NULL;
memset(&info, 0, sizeof(struct siginfo));
info.si_code = SI_QUEUE;
@@ -1457,20 +1488,32 @@
continue;
if (entry->client_info.notification_list & peripheral_mask) {
info.si_signo = entry->client_info.signal_type;
- if (entry->client &&
- entry->tgid == entry->client->tgid) {
- DIAG_LOG(DIAG_DEBUG_DCI,
- "entry tgid = %d, dci client tgid = %d\n",
- entry->tgid, entry->client->tgid);
- stat = send_sig_info(
- entry->client_info.signal_type,
- &info, entry->client);
- if (stat)
- pr_err("diag: Err sending dci signal to client, signal data: 0x%x, stat: %d\n",
+ pid_struct = find_get_pid(entry->tgid);
+ if (pid_struct) {
+ dci_task = get_pid_task(pid_struct,
+ PIDTYPE_PID);
+ if (!dci_task) {
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: dci client with pid = %d Exited..\n",
+ entry->tgid);
+ mutex_unlock(&driver->dci_mutex);
+ return;
+ }
+ if (entry->client &&
+ entry->tgid == dci_task->tgid) {
+ DIAG_LOG(DIAG_DEBUG_DCI,
+ "entry tgid = %d, dci client tgid = %d\n",
+ entry->tgid, dci_task->tgid);
+ stat = send_sig_info(
+ entry->client_info.signal_type,
+ &info, dci_task);
+ if (stat)
+ pr_err("diag: Err sending dci signal to client, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
- } else
- pr_err("diag: client data is corrupted, signal data: 0x%x, stat: %d\n",
+ } else
+ pr_err("diag: client data is corrupted, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
+ }
}
}
mutex_unlock(&driver->dci_mutex);
@@ -2396,10 +2439,12 @@
* is down. It may also mean that the peripheral doesn't
* support DCI.
*/
- err = diag_dci_write_proc(i, DIAG_CNTL_TYPE, buf,
- header_size + DCI_EVENT_MASK_SIZE);
- if (err != DIAG_DCI_NO_ERROR)
- ret = DIAG_DCI_SEND_DATA_FAIL;
+ if (check_peripheral_dci_support(i, DCI_LOCAL_PROC)) {
+ err = diag_dci_write_proc(i, DIAG_CNTL_TYPE, buf,
+ header_size + DCI_EVENT_MASK_SIZE);
+ if (err != DIAG_DCI_NO_ERROR)
+ ret = DIAG_DCI_SEND_DATA_FAIL;
+ }
}
mutex_unlock(&event_mask.lock);
@@ -2581,11 +2626,13 @@
}
write_len = dci_fill_log_mask(buf, log_mask_ptr);
for (j = 0; j < NUM_PERIPHERALS && write_len; j++) {
- err = diag_dci_write_proc(j, DIAG_CNTL_TYPE, buf,
- write_len);
- if (err != DIAG_DCI_NO_ERROR) {
- updated = 0;
- ret = DIAG_DCI_SEND_DATA_FAIL;
+ if (check_peripheral_dci_support(j, DCI_LOCAL_PROC)) {
+ err = diag_dci_write_proc(j, DIAG_CNTL_TYPE,
+ buf, write_len);
+ if (err != DIAG_DCI_NO_ERROR) {
+ updated = 0;
+ ret = DIAG_DCI_SEND_DATA_FAIL;
+ }
}
}
if (updated)
diff --git a/drivers/char/diag/diag_memorydevice.c b/drivers/char/diag/diag_memorydevice.c
index 7e3fe90..dabb1f4 100644
--- a/drivers/char/diag/diag_memorydevice.c
+++ b/drivers/char/diag/diag_memorydevice.c
@@ -218,6 +218,7 @@
uint8_t drain_again = 0;
int peripheral = 0;
struct diag_md_session_t *session_info = NULL;
+ struct pid *pid_struct = NULL;
for (i = 0; i < NUM_DIAG_MD_DEV && !err; i++) {
ch = &diag_md[i];
@@ -240,6 +241,14 @@
if ((info && (info->peripheral_mask &
MD_PERIPHERAL_MASK(peripheral)) == 0))
goto drop_data;
+ pid_struct = find_get_pid(session_info->pid);
+ if (!pid_struct) {
+ err = -ESRCH;
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: No such md_session_map[%d] with pid = %d err=%d exists..\n",
+ peripheral, session_info->pid, err);
+ goto drop_data;
+ }
/*
* If the data is from remote processor, copy the remote
* token first
@@ -259,27 +268,35 @@
}
if (i > 0) {
remote_token = diag_get_remote(i);
- err = copy_to_user(buf + ret, &remote_token,
- sizeof(int));
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ &remote_token,
+ sizeof(int));
+ if (err)
+ goto drop_data;
+ ret += sizeof(int);
+ }
+ }
+
+ /* Copy the length of data being passed */
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ (void *)&(entry->len),
+ sizeof(int));
if (err)
goto drop_data;
ret += sizeof(int);
}
- /* Copy the length of data being passed */
- err = copy_to_user(buf + ret, (void *)&(entry->len),
- sizeof(int));
- if (err)
- goto drop_data;
- ret += sizeof(int);
-
/* Copy the actual data being passed */
- err = copy_to_user(buf + ret, (void *)entry->buf,
- entry->len);
- if (err)
- goto drop_data;
- ret += entry->len;
-
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ (void *)entry->buf,
+ entry->len);
+ if (err)
+ goto drop_data;
+ ret += entry->len;
+ }
/*
* The data is now copied to the user space client,
* Notify that the write is complete and delete its
@@ -301,7 +318,11 @@
}
*pret = ret;
- err = copy_to_user(buf + sizeof(int), (void *)&num_data, sizeof(int));
+ if (pid_struct && get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + sizeof(int),
+ (void *)&num_data,
+ sizeof(int));
+ }
diag_ws_on_copy_complete(DIAG_WS_MUX);
if (drain_again)
chk_logging_wakeup();
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 543f0a2..54e6486 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -1304,11 +1304,9 @@
mutex_unlock(&driver->md_session_lock);
return -ENOMEM;
}
-
new_session->peripheral_mask = 0;
new_session->pid = current->tgid;
new_session->task = current;
-
new_session->log_mask = kzalloc(sizeof(struct diag_mask_info),
GFP_KERNEL);
if (!new_session->log_mask) {
@@ -1426,7 +1424,6 @@
struct diag_md_session_t *diag_md_session_get_pid(int pid)
{
int i;
-
for (i = 0; i < NUM_MD_SESSIONS; i++) {
if (driver->md_session_map[i] &&
driver->md_session_map[i]->pid == pid)
@@ -1542,7 +1539,10 @@
* If this session owns all the requested peripherals, then
* call function to switch the modes/masks for the md_session
*/
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
+
if (!session_info) {
*change_mode = 1;
return 0;
@@ -1571,7 +1571,9 @@
* owned by this md session
*/
change_mask = driver->md_session_mask & param->peripheral_mask;
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (session_info) {
if ((session_info->peripheral_mask & change_mask)
@@ -1999,8 +2001,9 @@
{
uint8_t hdlc_support;
struct diag_md_session_t *session_info = NULL;
-
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (copy_from_user(&hdlc_support, (void __user *)ioarg,
sizeof(uint8_t)))
return -EFAULT;
@@ -2768,10 +2771,13 @@
} else {
wait_event_interruptible(driver->wait_q,
(driver->in_busy_pktdata == 0));
+ mutex_lock(&driver->md_session_lock);
info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
ret = diag_process_apps_pkt(user_space_data, len, info);
if (ret == 1)
- diag_send_error_rsp((void *)(user_space_data), len);
+ diag_send_error_rsp((void *)(user_space_data), len,
+ info);
}
fail:
diagmem_free(driver, user_space_data, mempool);
@@ -2835,7 +2841,9 @@
/* send masks to local processor now */
if (!remote_proc) {
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (!session_info) {
pr_err("diag:In %s request came from invalid md session pid:%d",
__func__, current->tgid);
@@ -3010,7 +3018,9 @@
goto exit;
/* place holder for number of data field */
ret += sizeof(int);
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
exit_stat = diag_md_copy_to_user(buf, &ret, count,
session_info);
goto exit;
@@ -3028,7 +3038,9 @@
if (ret == -EFAULT)
goto exit;
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (session_info) {
COPY_USER_SPACE_OR_ERR(buf+4,
session_info->hdlc_disabled,
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index b59f245..fc67c1a 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -240,10 +240,11 @@
}
}
-static void pack_rsp_and_send(unsigned char *buf, int len)
+static void pack_rsp_and_send(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
int err;
- int retry_count = 0;
+ int retry_count = 0, i, rsp_ctxt;
uint32_t write_len = 0;
unsigned long flags;
unsigned char *rsp_ptr = driver->encoded_rsp_buf;
@@ -259,6 +260,26 @@
}
/*
+ * Explicitly check for the Peripheral Modem here
+ * is necessary till a way to identify a peripheral
+ * if its supporting qshrink4 feature.
+ */
+ if (info && info->peripheral_mask) {
+ if (info->peripheral_mask == DIAG_CON_ALL ||
+ (info->peripheral_mask & (1 << APPS_DATA)) ||
+ (info->peripheral_mask & (1 << PERIPHERAL_MODEM))) {
+ rsp_ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_CMD, 1);
+ } else {
+ for (i = 0; i < NUM_MD_SESSIONS; i++) {
+ if (info->peripheral_mask & (1 << i))
+ break;
+ }
+ rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, 1);
+ }
+ } else
+ rsp_ctxt = driver->rsp_buf_ctxt;
+
+ /*
* Keep trying till we get the buffer back. It should probably
* take one or two iterations. When this loops till UINT_MAX, it
* means we did not get a write complete for the previous
@@ -299,8 +320,7 @@
*(uint8_t *)(rsp_ptr + write_len) = CONTROL_CHAR;
write_len += sizeof(uint8_t);
- err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, write_len,
- driver->rsp_buf_ctxt);
+ err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, write_len, rsp_ctxt);
if (err) {
pr_err("diag: In %s, unable to write to mux, err: %d\n",
__func__, err);
@@ -310,12 +330,13 @@
}
}
-static void encode_rsp_and_send(unsigned char *buf, int len)
+static void encode_rsp_and_send(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 };
struct diag_hdlc_dest_type enc = { NULL, NULL, 0 };
unsigned char *rsp_ptr = driver->encoded_rsp_buf;
- int err, retry_count = 0;
+ int err, i, rsp_ctxt, retry_count = 0;
unsigned long flags;
if (!rsp_ptr || !buf)
@@ -328,6 +349,26 @@
}
/*
+ * Explicitly check for the Peripheral Modem here
+ * is necessary till a way to identify a peripheral
+ * if its supporting qshrink4 feature.
+ */
+ if (info && info->peripheral_mask) {
+ if (info->peripheral_mask == DIAG_CON_ALL ||
+ (info->peripheral_mask & (1 << APPS_DATA)) ||
+ (info->peripheral_mask & (1 << PERIPHERAL_MODEM))) {
+ rsp_ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_CMD, 1);
+ } else {
+ for (i = 0; i < NUM_MD_SESSIONS; i++) {
+ if (info->peripheral_mask & (1 << i))
+ break;
+ }
+ rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, 1);
+ }
+ } else
+ rsp_ctxt = driver->rsp_buf_ctxt;
+
+ /*
* Keep trying till we get the buffer back. It should probably
* take one or two iterations. When this loops till UINT_MAX, it
* means we did not get a write complete for the previous
@@ -370,7 +411,7 @@
diag_hdlc_encode(&send, &enc);
driver->encoded_rsp_len = (int)(enc.dest - (void *)rsp_ptr);
err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, driver->encoded_rsp_len,
- driver->rsp_buf_ctxt);
+ rsp_ctxt);
if (err) {
pr_err("diag: In %s, Unable to write to device, err: %d\n",
__func__, err);
@@ -381,21 +422,23 @@
memset(buf, '\0', DIAG_MAX_RSP_SIZE);
}
-void diag_send_rsp(unsigned char *buf, int len)
+static void diag_send_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
struct diag_md_session_t *session_info = NULL;
uint8_t hdlc_disabled;
- session_info = diag_md_session_get_peripheral(APPS_DATA);
+ session_info = (info) ? info :
+ diag_md_session_get_peripheral(APPS_DATA);
if (session_info)
hdlc_disabled = session_info->hdlc_disabled;
else
hdlc_disabled = driver->hdlc_disabled;
if (hdlc_disabled)
- pack_rsp_and_send(buf, len);
+ pack_rsp_and_send(buf, len, session_info);
else
- encode_rsp_and_send(buf, len);
+ encode_rsp_and_send(buf, len, session_info);
}
void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type)
@@ -926,7 +969,8 @@
return write_len;
}
-void diag_send_error_rsp(unsigned char *buf, int len)
+void diag_send_error_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
/* -1 to accommodate the first byte 0x13 */
if (len > (DIAG_MAX_RSP_SIZE - 1)) {
@@ -936,7 +980,7 @@
*(uint8_t *)driver->apps_rsp_buf = DIAG_CMD_ERROR;
memcpy((driver->apps_rsp_buf + sizeof(uint8_t)), buf, len);
- diag_send_rsp(driver->apps_rsp_buf, len + 1);
+ diag_send_rsp(driver->apps_rsp_buf, len + 1, info);
}
int diag_process_apps_pkt(unsigned char *buf, int len,
@@ -956,7 +1000,7 @@
/* Check if the command is a supported mask command */
mask_ret = diag_process_apps_masks(buf, len, info);
if (mask_ret > 0) {
- diag_send_rsp(driver->apps_rsp_buf, mask_ret);
+ diag_send_rsp(driver->apps_rsp_buf, mask_ret, info);
return 0;
}
@@ -978,7 +1022,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
@@ -988,13 +1032,15 @@
reg_item = container_of(temp_entry, struct diag_cmd_reg_t,
entry);
if (info) {
- if (MD_PERIPHERAL_MASK(reg_item->proc) &
- info->peripheral_mask)
+ if ((MD_PERIPHERAL_MASK(reg_item->proc) &
+ info->peripheral_mask) ||
+ (MD_PERIPHERAL_PD_MASK(reg_item->proc) &
+ info->peripheral_mask))
write_len = diag_send_data(reg_item, buf, len);
} else {
if (MD_PERIPHERAL_MASK(reg_item->proc) &
driver->logging_mask)
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
else
write_len = diag_send_data(reg_item, buf, len);
}
@@ -1010,13 +1056,13 @@
for (i = 0; i < 4; i++)
*(driver->apps_rsp_buf+i) = *(buf+i);
*(uint32_t *)(driver->apps_rsp_buf+4) = DIAG_MAX_REQ_SIZE;
- diag_send_rsp(driver->apps_rsp_buf, 8);
+ diag_send_rsp(driver->apps_rsp_buf, 8, info);
return 0;
} else if ((*buf == 0x4b) && (*(buf+1) == 0x12) &&
(*(uint16_t *)(buf+2) == DIAG_DIAG_STM)) {
len = diag_process_stm_cmd(buf, driver->apps_rsp_buf);
if (len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, len);
+ diag_send_rsp(driver->apps_rsp_buf, len, info);
return 0;
}
return len;
@@ -1029,7 +1075,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for time sync switch command */
@@ -1040,7 +1086,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for diag id command */
@@ -1051,14 +1097,14 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for download command */
else if ((chk_apps_master()) && (*buf == 0x3A)) {
/* send response back */
driver->apps_rsp_buf[0] = *buf;
- diag_send_rsp(driver->apps_rsp_buf, 1);
+ diag_send_rsp(driver->apps_rsp_buf, 1, info);
msleep(5000);
/* call download API */
msm_set_restart_mode(RESTART_DLOAD);
@@ -1078,7 +1124,7 @@
for (i = 0; i < 13; i++)
driver->apps_rsp_buf[i+3] = 0;
- diag_send_rsp(driver->apps_rsp_buf, 16);
+ diag_send_rsp(driver->apps_rsp_buf, 16, info);
return 0;
}
}
@@ -1087,7 +1133,7 @@
(*(buf+2) == 0x04) && (*(buf+3) == 0x0)) {
memcpy(driver->apps_rsp_buf, buf, 4);
driver->apps_rsp_buf[4] = wrap_enabled;
- diag_send_rsp(driver->apps_rsp_buf, 5);
+ diag_send_rsp(driver->apps_rsp_buf, 5, info);
return 0;
}
/* Wrap the Delayed Rsp ID */
@@ -1096,7 +1142,7 @@
wrap_enabled = true;
memcpy(driver->apps_rsp_buf, buf, 4);
driver->apps_rsp_buf[4] = wrap_count;
- diag_send_rsp(driver->apps_rsp_buf, 6);
+ diag_send_rsp(driver->apps_rsp_buf, 6, info);
return 0;
}
/* Mobile ID Rsp */
@@ -1107,7 +1153,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
}
@@ -1127,7 +1173,7 @@
for (i = 0; i < 55; i++)
driver->apps_rsp_buf[i] = 0;
- diag_send_rsp(driver->apps_rsp_buf, 55);
+ diag_send_rsp(driver->apps_rsp_buf, 55, info);
return 0;
}
/* respond to 0x7c command */
@@ -1140,14 +1186,14 @@
chk_config_get_id();
*(unsigned char *)(driver->apps_rsp_buf + 12) = '\0';
*(unsigned char *)(driver->apps_rsp_buf + 13) = '\0';
- diag_send_rsp(driver->apps_rsp_buf, 14);
+ diag_send_rsp(driver->apps_rsp_buf, 14, info);
return 0;
}
}
write_len = diag_cmd_chk_stats(buf, len, driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
write_len = diag_cmd_disable_hdlc(buf, len, driver->apps_rsp_buf,
@@ -1159,7 +1205,7 @@
* before disabling HDLC encoding on Apps processor.
*/
mutex_lock(&driver->hdlc_disable_mutex);
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
/*
* Set the value of hdlc_disabled after sending the response to
* the tools. This is required since the tools is expecting a
@@ -1179,7 +1225,7 @@
/* We have now come to the end of the function. */
if (chk_apps_only())
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
return 0;
}
@@ -1262,7 +1308,7 @@
* recovery algorithm. Send an error response if the
* packet is not in expected format.
*/
- diag_send_error_rsp(driver->hdlc_buf, driver->hdlc_buf_len);
+ diag_send_error_rsp(driver->hdlc_buf, driver->hdlc_buf_len, info);
driver->hdlc_buf_len = 0;
end:
mutex_unlock(&driver->diag_hdlc_mutex);
@@ -1535,7 +1581,7 @@
if (actual_pkt->start != CONTROL_CHAR) {
diag_hdlc_start_recovery(buf, len, info);
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
goto end;
}
mutex_lock(&driver->hdlc_recovery_mutex);
@@ -1625,15 +1671,14 @@
case TYPE_CMD:
if (peripheral >= 0 && peripheral < NUM_PERIPHERALS) {
diagfwd_write_done(peripheral, type, num);
- } else if (peripheral == APPS_DATA) {
+ }
+ if (peripheral == APPS_DATA ||
+ ctxt == DIAG_MEMORY_DEVICE_MODE) {
spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags);
driver->rsp_buf_busy = 0;
driver->encoded_rsp_len = 0;
spin_unlock_irqrestore(&driver->rsp_buf_busy_lock,
flags);
- } else {
- pr_err_ratelimited("diag: Invalid peripheral %d in %s, type: %d\n",
- peripheral, __func__, type);
}
break;
default:
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index 677099f..0e0bf2d 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -47,7 +47,8 @@
void diag_update_sleeping_process(int process_id, int data_type);
int diag_process_apps_pkt(unsigned char *buf, int len,
struct diag_md_session_t *info);
-void diag_send_error_rsp(unsigned char *buf, int len);
+void diag_send_error_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info);
void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type);
int diag_process_stm_cmd(unsigned char *buf, unsigned char *dest_buf);
void diag_md_hdlc_reset_timer_func(unsigned long pid);
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 710271e..d8c107e 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -111,6 +111,8 @@
{
int stat = 0;
struct siginfo info;
+ struct pid *pid_struct;
+ struct task_struct *result;
if (peripheral > NUM_PERIPHERALS)
return;
@@ -123,18 +125,38 @@
info.si_code = SI_QUEUE;
info.si_int = (PERIPHERAL_MASK(peripheral) | data);
info.si_signo = SIGCONT;
- if (driver->md_session_map[peripheral] &&
- driver->md_session_map[peripheral]->task) {
- if (driver->md_session_map[peripheral]->pid ==
- driver->md_session_map[peripheral]->task->tgid) {
+
+ if (!driver->md_session_map[peripheral] ||
+ driver->md_session_map[peripheral]->pid <= 0) {
+ pr_err("diag: md_session_map[%d] is invalid\n", peripheral);
+ mutex_unlock(&driver->md_session_lock);
+ return;
+ }
+
+ pid_struct = find_get_pid(
+ driver->md_session_map[peripheral]->pid);
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "md_session_map[%d] pid = %d task = %pK\n",
+ peripheral,
+ driver->md_session_map[peripheral]->pid,
+ driver->md_session_map[peripheral]->task);
+
+ if (pid_struct) {
+ result = get_pid_task(pid_struct, PIDTYPE_PID);
+
+ if (!result) {
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
- "md_session %d pid = %d, md_session %d task tgid = %d\n",
+ "diag: md_session_map[%d] with pid = %d Exited..\n",
peripheral,
- driver->md_session_map[peripheral]->pid,
- peripheral,
- driver->md_session_map[peripheral]->task->tgid);
- stat = send_sig_info(info.si_signo, &info,
- driver->md_session_map[peripheral]->task);
+ driver->md_session_map[peripheral]->pid);
+ mutex_unlock(&driver->md_session_lock);
+ return;
+ }
+
+ if (driver->md_session_map[peripheral] &&
+ driver->md_session_map[peripheral]->task == result) {
+ stat = send_sig_info(info.si_signo,
+ &info, result);
if (stat)
pr_err("diag: Err sending signal to memory device client, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
diff --git a/drivers/char/diag/diagfwd_peripheral.c b/drivers/char/diag/diagfwd_peripheral.c
index 0703c38..4d4b660 100644
--- a/drivers/char/diag/diagfwd_peripheral.c
+++ b/drivers/char/diag/diagfwd_peripheral.c
@@ -222,12 +222,22 @@
struct diagfwd_info *fwd_info = NULL;
peripheral = GET_BUF_PERIPHERAL(ctxt);
- if (peripheral < 0 || peripheral > NUM_PERIPHERALS)
+
+ /* Check for peripheral value within bounds
+ * of peripherals and UPD combined.
+ */
+ if (peripheral < 0 || peripheral > NUM_MD_SESSIONS)
return -EINVAL;
if (peripheral == APPS_DATA)
return peripheral;
+ /* With peripheral value bound checked
+ * return user pd value.
+ */
+ if (peripheral > NUM_PERIPHERALS)
+ return peripheral;
+
type = GET_BUF_TYPE(ctxt);
if (type < 0 || type >= NUM_TYPES)
return -EINVAL;
diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c
index 93a08db..701db25 100644
--- a/drivers/clk/qcom/clk-cpu-osm.c
+++ b/drivers/clk/qcom/clk-cpu-osm.c
@@ -18,7 +18,6 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/clk.h>
@@ -27,20 +26,15 @@
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
-#include <linux/pm_qos.h>
#include <linux/interrupt.h>
-#include <linux/regulator/driver.h>
-#include <linux/regmap.h>
#include <linux/uaccess.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
-#include <soc/qcom/scm.h>
#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
#include "common.h"
#include "clk-regmap.h"
-#include "clk-rcg.h"
#include "clk-voter.h"
#include "clk-debug.h"
@@ -53,105 +47,12 @@
#define MAX_CORE_COUNT 4
#define CORE_COUNT_VAL(val) ((val & GENMASK(18, 16)) >> 16)
-#define OSM_CYCLE_COUNTER_CTRL_REG 0x760
-#define OSM_CYCLE_COUNTER_USE_XO_EDGE_EN BIT(8)
-
#define OSM_REG_SIZE 32
-#define L3_EFUSE_SHIFT 29
-#define L3_EFUSE_MASK 0x7
-#define PWRCL_EFUSE_SHIFT 29
-#define PWRCL_EFUSE_MASK 0x7
-#define PERFCL_EFUSE_SHIFT 29
-#define PERFCL_EFUSE_MASK 0x7
-
#define ENABLE_REG 0x0
-#define ENABLE_OSM BIT(0)
#define FREQ_REG 0x110
#define VOLT_REG 0x114
-#define OVERRIDE_REG 0x118
-#define SPM_CC_INC_HYSTERESIS 0x1c
-#define SPM_CC_DEC_HYSTERESIS 0x20
-#define SPM_CORE_INACTIVE_MAPPING 0x28
-#define CC_ZERO_BEHAV_CTRL 0xc
-#define ENABLE_OVERRIDE BIT(0)
-#define SPM_CC_DCVS_DISABLE 0x24
-#define LLM_FREQ_VOTE_INC_HYSTERESIS 0x30
-#define LLM_FREQ_VOTE_DEC_HYSTERESIS 0x34
-#define LLM_INTF_DCVS_DISABLE 0x40
-#define LLM_VOLTAGE_VOTE_INC_HYSTERESIS 0x38
-#define LLM_VOLTAGE_VOTE_DEC_HYSTERESIS 0x3c
-#define VMIN_REDUCTION_ENABLE_REG 0x48
-#define VMIN_REDUCTION_TIMER_REG 0x4c
-#define PDN_FSM_CTRL_REG 0x54
-#define DELTA_DEX_VAL BVAL(31, 23, 0xa)
-#define IGNORE_PLL_LOCK BIT(15)
-#define CC_BOOST_FSM_EN BIT(0)
-#define CC_BOOST_FSM_TIMERS_REG0 0x58
-#define CC_BOOST_FSM_TIMERS_REG1 0x5c
-#define CC_BOOST_FSM_TIMERS_REG2 0x60
-#define DCVS_BOOST_FSM_EN_MASK BIT(2)
-#define DCVS_BOOST_FSM_TIMERS_REG0 0x64
-#define DCVS_BOOST_FSM_TIMERS_REG1 0x68
-#define DCVS_BOOST_FSM_TIMERS_REG2 0x6c
-#define PS_BOOST_FSM_EN_MASK BIT(1)
-#define PS_BOOST_FSM_TIMERS_REG0 0x74
-#define PS_BOOST_FSM_TIMERS_REG1 0x78
-#define PS_BOOST_FSM_TIMERS_REG2 0x7c
-#define BOOST_PROG_SYNC_DELAY_REG 0x80
-#define DCVS_DROOP_FSM_EN_MASK BIT(5)
-#define DROOP_PROG_SYNC_DELAY_REG 0x9c
-#define DROOP_RELEASE_TIMER_CTRL 0x88
-#define DROOP_CTRL_REG 0x84
-#define DCVS_DROOP_TIMER_CTRL 0x98
-#define PLL_SW_OVERRIDE_ENABLE 0xa0
-#define PLL_SW_OVERRIDE_DROOP_EN BIT(0)
-#define SPM_CORE_COUNT_CTRL 0x2c
#define CORE_DCVS_CTRL 0xbc
-#define OVERRIDE_CLUSTER_IDLE_ACK 0x800
-#define REQ_GEN_FSM_STATUS 0x70c
-
-#define PLL_MIN_LVAL 0x21
-#define PLL_MIN_FREQ_REG 0x94
-#define PLL_POST_DIV1 0x09
-#define PLL_POST_DIV2 0x109
-#define PLL_MODE 0x0
-#define PLL_L_VAL 0x4
-#define PLL_USER_CTRL 0xc
-#define PLL_CONFIG_CTL_LO 0x10
-#define PLL_CONFIG_CTL_HI 0x14
-#define MIN_VCO_VAL 0x2b
-
-#define MAX_VC 63
-#define MEM_ACC_LEVELS_LUT 2
-#define MAX_MEM_ACC_LEVELS 3
-#define MAX_MEM_ACC_VAL_PER_LEVEL 3
-#define MAX_MEM_ACC_VALUES (MAX_MEM_ACC_LEVELS * \
- MAX_MEM_ACC_VAL_PER_LEVEL)
-#define MEM_ACC_ADDRS 3
-
-#define ISENSE_ON_DATA 0xf
-#define ISENSE_OFF_DATA 0x0
-#define CONSTANT_32 0x20
-
-#define APM_MX_MODE 0x4100000
-#define APM_APC_MODE 0x4100002
-#define APM_READ_DATA_MASK 0xc
-#define APM_MX_MODE_VAL 0x4
-#define APM_APC_READ_VAL 0x8
-#define APM_MX_READ_VAL 0x4
-#define APM_CROSSOVER_VC 0xb0
-
-#define MEM_ACC_SEQ_CONST(n) (n)
-#define MEM_ACC_APM_READ_MASK 0xff
-#define MEMACC_CROSSOVER_VC 0xb8
-
-#define PLL_WAIT_LOCK_TIME_US 10
-#define PLL_WAIT_LOCK_TIME_NS (PLL_WAIT_LOCK_TIME_US * 1000)
-#define SAFE_FREQ_WAIT_NS 5000
-#define DEXT_DECREMENT_WAIT_NS 1000
-
-#define DATA_MEM(n) (0x400 + (n) * 4)
#define DCVS_PERF_STATE_DESIRED_REG_0_V1 0x780
#define DCVS_PERF_STATE_DESIRED_REG_0_V2 0x920
@@ -165,339 +66,52 @@
(((v2) ? OSM_CYCLE_COUNTER_STATUS_REG_0_V2 \
: OSM_CYCLE_COUNTER_STATUS_REG_0_V1) + 4 * (n))
-/* ACD registers */
-#define ACD_HW_VERSION 0x0
-#define ACDCR 0x4
-#define ACDTD 0x8
-#define ACDSSCR 0x28
-#define ACD_EXTINT_CFG 0x30
-#define ACD_DCVS_SW 0x34
-#define ACD_GFMUX_CFG 0x3c
-#define ACD_READOUT_CFG 0x48
-#define ACD_AVG_CFG_0 0x4c
-#define ACD_AVG_CFG_1 0x50
-#define ACD_AVG_CFG_2 0x54
-#define ACD_AUTOXFER_CFG 0x80
-#define ACD_AUTOXFER 0x84
-#define ACD_AUTOXFER_CTL 0x88
-#define ACD_AUTOXFER_STATUS 0x8c
-#define ACD_WRITE_CTL 0x90
-#define ACD_WRITE_STATUS 0x94
-#define ACD_READOUT 0x98
-
-#define ACD_MASTER_ONLY_REG_ADDR 0x80
-#define ACD_1P1_MAX_REG_OFFSET 0x100
-#define ACD_WRITE_CTL_UPDATE_EN BIT(0)
-#define ACD_WRITE_CTL_SELECT_SHIFT 1
-#define ACD_GFMUX_CFG_SELECT BIT(0)
-#define ACD_AUTOXFER_START_CLEAR 0
-#define ACD_AUTOXFER_START_SET 1
-#define AUTO_XFER_DONE_MASK BIT(0)
-#define ACD_DCVS_SW_DCVS_IN_PRGR_SET BIT(0)
-#define ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR 0
-#define ACD_LOCAL_TRANSFER_TIMEOUT_NS 500
-
-#define ACD_REG_RELATIVE_ADDR(addr) (addr / 4)
-#define ACD_REG_RELATIVE_ADDR_BITMASK(addr) \
- (1 << (ACD_REG_RELATIVE_ADDR(addr)))
-
-static const struct regmap_config osm_qcom_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .fast_io = true,
-};
-
-enum clk_osm_bases {
- OSM_BASE,
- PLL_BASE,
- EFUSE_BASE,
- SEQ_BASE,
- ACD_BASE,
- NUM_BASES,
-};
-
-enum clk_osm_lut_data {
- FREQ,
- FREQ_DATA,
- PLL_OVERRIDES,
- MEM_ACC_LEVEL,
- VIRTUAL_CORNER,
- NUM_FIELDS,
-};
-
struct osm_entry {
u16 virtual_corner;
u16 open_loop_volt;
- u32 freq_data;
- u32 override_data;
- u32 mem_acc_level;
long frequency;
};
-static struct dentry *osm_debugfs_base;
-
struct clk_osm {
struct clk_hw hw;
struct osm_entry osm_table[OSM_TABLE_SIZE];
struct dentry *debugfs;
- struct regulator *vdd_reg;
- struct platform_device *vdd_dev;
- void *vbases[NUM_BASES];
- unsigned long pbases[NUM_BASES];
+ void __iomem *vbase;
+ phys_addr_t pbase;
spinlock_t lock;
-
+ bool per_core_dcvs;
u32 num_entries;
u32 cluster_num;
u32 core_num;
- u32 apm_crossover_vc;
- u32 apm_threshold_vc;
- u32 mem_acc_crossover_vc;
- u32 mem_acc_threshold_vc;
- u32 min_cpr_vc;
- u32 cycle_counter_reads;
- u32 cycle_counter_delay;
- u32 cycle_counter_factor;
u64 total_cycle_counter;
u32 prev_cycle_counter;
- u32 l_val_base;
- u32 apcs_pll_user_ctl;
- u32 apcs_pll_min_freq;
- u32 cfg_gfmux_addr;
- u32 apcs_cbc_addr;
- u32 speedbin;
- u32 mem_acc_crossover_vc_addr;
- u32 mem_acc_addr[MEM_ACC_ADDRS];
- u32 mem_acc_level_vc[MEM_ACC_LEVELS_LUT];
- u32 ramp_ctl_addr;
- u32 apm_mode_ctl;
- u32 apm_status_ctl;
- u32 osm_clk_rate;
- u32 xo_clk_rate;
- bool secure_init;
- bool per_core_dcvs;
- bool red_fsm_en;
- bool boost_fsm_en;
- bool safe_fsm_en;
- bool ps_fsm_en;
- bool droop_fsm_en;
-
- struct notifier_block panic_notifier;
- u32 trace_periodic_timer;
- bool trace_en;
- bool wdog_trace_en;
-
- bool acd_init;
- u32 acd_td;
- u32 acd_cr;
- u32 acd_sscr;
- u32 acd_extint0_cfg;
- u32 acd_extint1_cfg;
- u32 acd_autoxfer_ctl;
- u32 acd_debugfs_addr;
- bool acd_avg_init;
- u32 acd_avg_cfg0;
- u32 acd_avg_cfg1;
- u32 acd_avg_cfg2;
};
-static struct regulator *vdd_l3;
-static struct regulator *vdd_pwrcl;
-static struct regulator *vdd_perfcl;
-
-static inline int clk_osm_acd_mb(struct clk_osm *c)
-{
- return readl_relaxed_no_log((char *)c->vbases[ACD_BASE] +
- ACD_HW_VERSION);
-}
-
-static int clk_osm_acd_local_read_reg(struct clk_osm *c, u32 offset)
-{
- u32 reg = 0;
- int timeout;
-
- if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
- pr_err("ACD register at offset=0x%x not locally readable\n",
- offset);
- return -EINVAL;
- }
-
- /* Set select field in read control register */
- writel_relaxed(ACD_REG_RELATIVE_ADDR(offset),
- (char *)c->vbases[ACD_BASE] + ACD_READOUT_CFG);
-
- /* Clear write control register */
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Set select and update_en fields in write control register */
- reg = (ACD_REG_RELATIVE_ADDR(ACD_READOUT_CFG)
- << ACD_WRITE_CTL_SELECT_SHIFT)
- | ACD_WRITE_CTL_UPDATE_EN;
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll write status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
- timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_WRITE_STATUS);
- if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(ACD_READOUT_CFG))))
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local read timed out, offset=0x%x status=0x%x\n",
- offset, reg);
- return -ETIMEDOUT;
- }
-
- reg = readl_relaxed((char *)c->vbases[ACD_BASE] + ACD_READOUT);
- return reg;
-}
-
-static int clk_osm_acd_local_write_reg(struct clk_osm *c, u32 val, u32 offset)
-{
- u32 reg = 0;
- int timeout;
-
- if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
- pr_err("ACD register at offset=0x%x not transferrable\n",
- offset);
- return -EINVAL;
- }
-
- /* Clear write control register */
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Set select and update_en fields in write control register */
- reg = (ACD_REG_RELATIVE_ADDR(offset) << ACD_WRITE_CTL_SELECT_SHIFT)
- | ACD_WRITE_CTL_UPDATE_EN;
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll write status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
- timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_WRITE_STATUS);
- if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(offset))))
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local write timed out, offset=0x%x val=0x%x status=0x%x\n",
- offset, val, reg);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-static int clk_osm_acd_master_write_through_reg(struct clk_osm *c,
- u32 val, u32 offset)
-{
- writel_relaxed(val, (char *)c->vbases[ACD_BASE] + offset);
-
- /* Ensure writes complete before transfer to local copy */
- clk_osm_acd_mb(c);
-
- return clk_osm_acd_local_write_reg(c, val, offset);
-}
-
-static int clk_osm_acd_auto_local_write_reg(struct clk_osm *c, u32 mask)
-{
- u32 numregs, bitmask = mask;
- u32 reg = 0;
- int timeout;
-
- /* count number of bits set in register mask */
- for (numregs = 0; bitmask; numregs++)
- bitmask &= bitmask - 1;
-
- /* Program auto-transfer mask */
- writel_relaxed(mask, (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER_CFG);
-
- /* Clear start field in auto-transfer register */
- writel_relaxed(ACD_AUTOXFER_START_CLEAR,
- (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
-
- /* Set start field in auto-transfer register */
- writel_relaxed(ACD_AUTOXFER_START_SET,
- (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll auto-transfer status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS * numregs;
- timeout > 0; timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_AUTOXFER_STATUS);
- if (reg & AUTO_XFER_DONE_MASK)
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local register auto-transfer timed out, mask=0x%x registers=%d status=0x%x\n",
- mask, numregs, reg);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
static bool is_v2;
-static bool osm_tz_enabled;
static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw)
{
return container_of(_hw, struct clk_osm, hw);
}
-static inline void clk_osm_masked_write_reg(struct clk_osm *c, u32 val,
- u32 offset, u32 mask)
+static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset)
{
- u32 val2, orig_val;
-
- val2 = orig_val = readl_relaxed((char *)c->vbases[OSM_BASE] + offset);
- val2 &= ~mask;
- val2 |= val & mask;
-
- if (val2 != orig_val)
- writel_relaxed(val2, (char *)c->vbases[OSM_BASE] + offset);
-}
-
-static inline void clk_osm_write_seq_reg(struct clk_osm *c, u32 val, u32 offset)
-{
- writel_relaxed(val, (char *)c->vbases[SEQ_BASE] + offset);
-}
-
-static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset,
- int base)
-{
- writel_relaxed(val, (char *)c->vbases[base] + offset);
+ writel_relaxed(val, c->vbase + offset);
}
static inline int clk_osm_read_reg(struct clk_osm *c, u32 offset)
{
- return readl_relaxed((char *)c->vbases[OSM_BASE] + offset);
+ return readl_relaxed(c->vbase + offset);
}
static inline int clk_osm_read_reg_no_log(struct clk_osm *c, u32 offset)
{
- return readl_relaxed_no_log((char *)c->vbases[OSM_BASE] + offset);
+ return readl_relaxed_no_log(c->vbase + offset);
}
-static inline int clk_osm_mb(struct clk_osm *c, int base)
+static inline int clk_osm_mb(struct clk_osm *c)
{
- return readl_relaxed_no_log((char *)c->vbases[base] + ENABLE_REG);
+ return readl_relaxed_no_log(c->vbase + ENABLE_REG);
}
static long clk_osm_list_rate(struct clk_hw *hw, unsigned int n,
@@ -559,23 +173,6 @@
return -EINVAL;
}
-static int clk_osm_enable(struct clk_hw *hw)
-{
- struct clk_osm *cpuclk = to_clk_osm(hw);
-
- clk_osm_masked_write_reg(cpuclk, ENABLE_OSM, ENABLE_REG, ENABLE_OSM);
-
- /* Make sure the write goes through before proceeding */
- clk_osm_mb(cpuclk, OSM_BASE);
-
- /* Wait for 5us for OSM hardware to enable */
- udelay(5);
-
- pr_debug("OSM clk enabled for cluster=%d\n", cpuclk->cluster_num);
-
- return 0;
-}
-
const struct clk_ops clk_ops_cpu_osm = {
.round_rate = clk_osm_round_rate,
.list_rate = clk_osm_list_rate,
@@ -608,11 +205,10 @@
}
pr_debug("rate: %lu --> index %d\n", rate, index);
- clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG(0, is_v2),
- OSM_BASE);
+ clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG(0, is_v2));
/* Make sure the write goes through before proceeding */
- clk_osm_mb(cpuclk, OSM_BASE);
+ clk_osm_mb(cpuclk);
return 0;
}
@@ -637,7 +233,6 @@
static struct clk_ops clk_ops_l3_osm = {
- .enable = clk_osm_enable,
.round_rate = clk_osm_round_rate,
.list_rate = clk_osm_list_rate,
.recalc_rate = l3_clk_recalc_rate,
@@ -781,12 +376,6 @@
},
};
-/*
- * Use the cpu* clocks only for writing to the PERF_STATE_DESIRED registers.
- * Note that we are currently NOT programming the APSS_LMH_GFMUX_CFG &
- * APSS_OSM_GFMUX_CFG registers.
- */
-
static struct clk_hw *osm_qcom_clk_hws[] = {
[L3_CLK] = &l3_clk.hw,
[L3_CLUSTER0_VOTE_CLK] = &l3_cluster0_vote_clk.hw,
@@ -894,11 +483,10 @@
static void
osm_set_index(struct clk_osm *c, unsigned int index, unsigned int num)
{
- clk_osm_write_reg(c, index, DCVS_PERF_STATE_DESIRED_REG(num, is_v2),
- OSM_BASE);
+ clk_osm_write_reg(c, index, DCVS_PERF_STATE_DESIRED_REG(num, is_v2));
/* Make sure the write goes through before proceeding */
- clk_osm_mb(c, OSM_BASE);
+ clk_osm_mb(c);
}
static int
@@ -947,7 +535,7 @@
}
parent = to_clk_osm(p_hw);
- c->vbases[OSM_BASE] = parent->vbases[OSM_BASE];
+ c->vbase = parent->vbase;
p_hw = clk_hw_get_parent(p_hw);
if (!p_hw) {
@@ -999,10 +587,6 @@
}
policy->driver_data = c;
-
- clk_osm_enable(&parent->hw);
- udelay(300);
-
return 0;
err:
@@ -1036,704 +620,6 @@
.boost_enabled = true,
};
-static inline int clk_osm_count_ns(struct clk_osm *c, u64 nsec)
-{
- u64 temp;
-
- temp = (u64)c->osm_clk_rate * nsec;
- do_div(temp, 1000000000);
-
- return temp;
-}
-
-static void clk_osm_program_mem_acc_regs(struct clk_osm *c)
-{
- if (c->secure_init) {
- clk_osm_write_seq_reg(c,
- c->pbases[OSM_BASE] + MEMACC_CROSSOVER_VC,
- DATA_MEM(57));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[0], DATA_MEM(48));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[1], DATA_MEM(49));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[2], DATA_MEM(50));
- clk_osm_write_seq_reg(c, c->mem_acc_crossover_vc,
- DATA_MEM(78));
- clk_osm_write_seq_reg(c, c->mem_acc_level_vc[0], DATA_MEM(79));
- clk_osm_write_seq_reg(c, c->mem_acc_level_vc[1], DATA_MEM(80));
- /*
- * Note that DATA_MEM[81] -> DATA_MEM[89] values will be
- * confirmed post-si. Use a value of 1 for DATA_MEM[89] and
- * leave the rest of them as 0.
- */
- clk_osm_write_seq_reg(c, 1, DATA_MEM(89));
- } else {
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(78),
- c->mem_acc_crossover_vc);
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(79),
- c->mem_acc_level_vc[0]);
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(80),
- c->mem_acc_level_vc[1]);
- }
-}
-
-static void clk_osm_program_apm_regs(struct clk_osm *c)
-{
- if (c == &l3_clk || c == &pwrcl_clk)
- return;
-
- /*
- * Program address of the control register used to configure
- * the Array Power Mux controller
- */
- clk_osm_write_seq_reg(c, c->apm_mode_ctl, DATA_MEM(41));
-
- /* Program address of controller status register */
- clk_osm_write_seq_reg(c, c->apm_status_ctl, DATA_MEM(43));
-
- /* Program address of crossover register */
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + APM_CROSSOVER_VC,
- DATA_MEM(44));
-
- /* Program mode value to switch APM to VDD_APC */
- clk_osm_write_seq_reg(c, APM_APC_MODE, DATA_MEM(72));
-
- /* Program mode value to switch APM to VDD_MX */
- clk_osm_write_seq_reg(c, APM_MX_MODE, DATA_MEM(73));
-
- /* Program mask used to move into read_mask port */
- clk_osm_write_seq_reg(c, APM_READ_DATA_MASK, DATA_MEM(74));
-
- /* Value used to move into read_exp port */
- clk_osm_write_seq_reg(c, APM_APC_READ_VAL, DATA_MEM(75));
- clk_osm_write_seq_reg(c, APM_MX_READ_VAL, DATA_MEM(76));
-}
-
-static void clk_osm_do_additional_setup(struct clk_osm *c,
- struct platform_device *pdev)
-{
- if (!c->secure_init)
- return;
-
- dev_info(&pdev->dev, "Performing additional OSM setup due to lack of TZ for cluster=%d\n",
- c->cluster_num);
-
- /* PLL L_VAL & post-div programming */
- clk_osm_write_seq_reg(c, c->apcs_pll_min_freq, DATA_MEM(32));
- clk_osm_write_seq_reg(c, c->l_val_base, DATA_MEM(33));
- clk_osm_write_seq_reg(c, c->apcs_pll_user_ctl, DATA_MEM(34));
- clk_osm_write_seq_reg(c, PLL_POST_DIV1, DATA_MEM(35));
- clk_osm_write_seq_reg(c, PLL_POST_DIV2, DATA_MEM(36));
-
- /* APM Programming */
- clk_osm_program_apm_regs(c);
-
- /* GFMUX Programming */
- clk_osm_write_seq_reg(c, c->cfg_gfmux_addr, DATA_MEM(37));
- clk_osm_write_seq_reg(c, 0x1, DATA_MEM(65));
- clk_osm_write_seq_reg(c, 0x2, DATA_MEM(66));
- clk_osm_write_seq_reg(c, 0x3, DATA_MEM(67));
- clk_osm_write_seq_reg(c, 0x40000000, DATA_MEM(68));
- clk_osm_write_seq_reg(c, 0x20000000, DATA_MEM(69));
- clk_osm_write_seq_reg(c, 0x10000000, DATA_MEM(70));
- clk_osm_write_seq_reg(c, 0x70000000, DATA_MEM(71));
-
- /* Override programming */
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] +
- OVERRIDE_CLUSTER_IDLE_ACK, DATA_MEM(54));
- clk_osm_write_seq_reg(c, 0x3, DATA_MEM(55));
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + PDN_FSM_CTRL_REG,
- DATA_MEM(40));
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + REQ_GEN_FSM_STATUS,
- DATA_MEM(60));
- clk_osm_write_seq_reg(c, 0x10, DATA_MEM(61));
- clk_osm_write_seq_reg(c, 0x70, DATA_MEM(62));
- clk_osm_write_seq_reg(c, c->apcs_cbc_addr, DATA_MEM(112));
- clk_osm_write_seq_reg(c, 0x2, DATA_MEM(113));
-
- if (c == &perfcl_clk) {
- int rc;
- u32 isense_addr;
-
- /* Performance cluster isense programming */
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-isense-addr", &isense_addr);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,perfcl-isense-addr property, rc=%d\n",
- rc);
- return;
- }
- clk_osm_write_seq_reg(c, isense_addr, DATA_MEM(45));
- clk_osm_write_seq_reg(c, ISENSE_ON_DATA, DATA_MEM(46));
- clk_osm_write_seq_reg(c, ISENSE_OFF_DATA, DATA_MEM(47));
- }
-
- clk_osm_write_seq_reg(c, c->ramp_ctl_addr, DATA_MEM(105));
- clk_osm_write_seq_reg(c, CONSTANT_32, DATA_MEM(92));
-
- /* Enable/disable CPR ramp settings */
- clk_osm_write_seq_reg(c, 0x101C031, DATA_MEM(106));
- clk_osm_write_seq_reg(c, 0x1010031, DATA_MEM(107));
-}
-
-static void clk_osm_setup_fsms(struct clk_osm *c)
-{
- u32 val;
-
- /* Voltage Reduction FSM */
- if (c->red_fsm_en) {
- val = clk_osm_read_reg(c, VMIN_REDUCTION_ENABLE_REG) | BIT(0);
- val |= BVAL(6, 1, c->min_cpr_vc);
- clk_osm_write_reg(c, val, VMIN_REDUCTION_ENABLE_REG,
- OSM_BASE);
-
- clk_osm_write_reg(c, clk_osm_count_ns(c, 10000),
- VMIN_REDUCTION_TIMER_REG, OSM_BASE);
- }
-
- /* Boost FSM */
- if (c->boost_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- val |= DELTA_DEX_VAL | CC_BOOST_FSM_EN | IGNORE_PLL_LOCK;
- clk_osm_write_reg(c, val, PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG2, OSM_BASE);
- }
-
- /* Safe Freq FSM */
- if (c->safe_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | DCVS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
-
- }
-
- /* Pulse Swallowing FSM */
- if (c->ps_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | PS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
- }
-
- /* PLL signal timing control */
- if (c->boost_fsm_en || c->safe_fsm_en || c->ps_fsm_en)
- clk_osm_write_reg(c, 0x2, BOOST_PROG_SYNC_DELAY_REG, OSM_BASE);
-
- /* DCVS droop FSM - only if RCGwRC is not used for di/dt control */
- if (c->droop_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | DCVS_DROOP_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
- }
-
- if (c->ps_fsm_en || c->droop_fsm_en) {
- clk_osm_write_reg(c, 0x1, DROOP_PROG_SYNC_DELAY_REG, OSM_BASE);
- clk_osm_write_reg(c, clk_osm_count_ns(c, 100),
- DROOP_RELEASE_TIMER_CTRL, OSM_BASE);
- clk_osm_write_reg(c, clk_osm_count_ns(c, 150),
- DCVS_DROOP_TIMER_CTRL, OSM_BASE);
- /*
- * TODO: Check if DCVS_DROOP_CODE used is correct. Also check
- * if RESYNC_CTRL should be set for L3.
- */
- val = BIT(31) | BVAL(22, 16, 0x2) | BVAL(6, 0, 0x8);
- clk_osm_write_reg(c, val, DROOP_CTRL_REG, OSM_BASE);
- }
-}
-
-static int clk_osm_set_llm_volt_policy(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0, val, regval;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM up voltage request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-volt-up-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM voltage up timer value, rc=%d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM down voltage request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-volt-down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM Voltage down timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
- }
-
- /* Enable or disable honoring of LLM Voltage requests */
- rc = of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-llm-volt-vote");
- if (rc) {
- dev_dbg(&pdev->dev, "Honoring LLM Voltage requests\n");
- val = 0;
- } else
- val = 1;
-
- /* Enable or disable LLM VOLT DVCS */
- regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static int clk_osm_set_llm_freq_policy(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0, val, regval;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM up frequency request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-freq-up-timer", array,
- MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "Unable to get CC up timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM down frequency request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-freq-down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM Frequency down timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
- }
-
- /* Enable or disable honoring of LLM frequency requests */
- rc = of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-llm-freq-vote");
- if (rc) {
- dev_dbg(&pdev->dev, "Honoring LLM Frequency requests\n");
- val = 0;
- } else
- val = BIT(1);
-
- /* Enable or disable LLM FREQ DVCS */
- regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the write to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static int clk_osm_set_cc_policy(struct platform_device *pdev)
-{
- int rc = 0, val;
- u32 *array;
- struct device_node *of = pdev->dev.of_node;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, "qcom,up-timer", array,
- MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No up timer value, rc=%d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk,
- array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- rc = of_property_read_u32_array(of, "qcom,down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No down timer value, rc=%d\n", rc);
- } else {
- val = clk_osm_count_ns(&l3_clk,
- array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
-
- clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
- }
-
- /* OSM index override for cluster PC */
- rc = of_property_read_u32_array(of, "qcom,pc-override-index",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No PC override index value, rc=%d\n",
- rc);
- clk_osm_write_reg(&pwrcl_clk, 0, CC_ZERO_BEHAV_CTRL, OSM_BASE);
- clk_osm_write_reg(&perfcl_clk, 0, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- } else {
- val = BVAL(6, 1, array[pwrcl_clk.cluster_num])
- | ENABLE_OVERRIDE;
- clk_osm_write_reg(&pwrcl_clk, val, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- val = BVAL(6, 1, array[perfcl_clk.cluster_num])
- | ENABLE_OVERRIDE;
- clk_osm_write_reg(&perfcl_clk, val, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- }
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-c3-active");
- if (rc) {
- dev_dbg(&pdev->dev, "Treat cores in C3 as active\n");
-
- val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
- }
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-c2-active");
- if (rc) {
- dev_dbg(&pdev->dev, "Treat cores in C2 as active\n");
-
- val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
- }
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,disable-cc-dvcs");
- if (rc) {
- dev_dbg(&pdev->dev, "Disabling CC based DCVS\n");
- val = 1;
- } else
- val = 0;
-
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static void clk_osm_setup_cluster_pll(struct clk_osm *c)
-{
- writel_relaxed(0x0, c->vbases[PLL_BASE] + PLL_MODE);
- writel_relaxed(0x26, c->vbases[PLL_BASE] + PLL_L_VAL);
- writel_relaxed(0x8, c->vbases[PLL_BASE] +
- PLL_USER_CTRL);
- writel_relaxed(0x20000AA8, c->vbases[PLL_BASE] +
- PLL_CONFIG_CTL_LO);
- writel_relaxed(0x000003D2, c->vbases[PLL_BASE] +
- PLL_CONFIG_CTL_HI);
- writel_relaxed(0x2, c->vbases[PLL_BASE] +
- PLL_MODE);
-
- /* Ensure writes complete before delaying */
- clk_osm_mb(c, PLL_BASE);
-
- udelay(PLL_WAIT_LOCK_TIME_US);
-
- writel_relaxed(0x6, c->vbases[PLL_BASE] + PLL_MODE);
-
- /* Ensure write completes before delaying */
- clk_osm_mb(c, PLL_BASE);
-
- usleep_range(50, 75);
-
- writel_relaxed(0x7, c->vbases[PLL_BASE] + PLL_MODE);
-}
-
-static void clk_osm_misc_programming(struct clk_osm *c)
-{
- u32 lval = 0xFF, val;
- int i;
-
- clk_osm_write_reg(c, BVAL(23, 16, 0xF), SPM_CORE_COUNT_CTRL,
- OSM_BASE);
- clk_osm_write_reg(c, PLL_MIN_LVAL, PLL_MIN_FREQ_REG, OSM_BASE);
-
- /* Pattern to set/clear PLL lock in PDN_FSM_CTRL_REG */
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- if (c->secure_init) {
- val |= IGNORE_PLL_LOCK;
- clk_osm_write_seq_reg(c, val, DATA_MEM(108));
- val &= ~IGNORE_PLL_LOCK;
- clk_osm_write_seq_reg(c, val, DATA_MEM(109));
- clk_osm_write_seq_reg(c, MIN_VCO_VAL, DATA_MEM(110));
- } else {
- val |= IGNORE_PLL_LOCK;
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(108), val);
- val &= ~IGNORE_PLL_LOCK;
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(109), val);
- }
-
- /* Program LVAL corresponding to first turbo VC */
- for (i = 0; i < c->num_entries; i++) {
- if (c->osm_table[i].virtual_corner ==
- c->mem_acc_level_vc[1]) {
- lval = c->osm_table[i].freq_data & GENMASK(7, 0);
- break;
- }
- }
-
- if (c->secure_init)
- clk_osm_write_seq_reg(c, lval, DATA_MEM(114));
- else
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(114), lval);
-
-}
-
-static int clk_osm_setup_hw_table(struct clk_osm *c)
-{
- struct osm_entry *entry = c->osm_table;
- int i;
- u32 freq_val = 0, volt_val = 0, override_val = 0;
- u32 table_entry_offset, last_mem_acc_level, last_virtual_corner = 0;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- if (i < c->num_entries) {
- freq_val = entry[i].freq_data;
- volt_val = BVAL(27, 24, entry[i].mem_acc_level)
- | BVAL(21, 16, entry[i].virtual_corner)
- | BVAL(11, 0, entry[i].open_loop_volt);
- override_val = entry[i].override_data;
-
- if (last_virtual_corner && last_virtual_corner ==
- entry[i].virtual_corner && last_mem_acc_level !=
- entry[i].mem_acc_level) {
- pr_err("invalid LUT entry at row=%d virtual_corner=%d, mem_acc_level=%d\n",
- i, entry[i].virtual_corner,
- entry[i].mem_acc_level);
- return -EINVAL;
- }
- last_virtual_corner = entry[i].virtual_corner;
- last_mem_acc_level = entry[i].mem_acc_level;
- }
-
- table_entry_offset = i * OSM_REG_SIZE;
- clk_osm_write_reg(c, freq_val, FREQ_REG + table_entry_offset,
- OSM_BASE);
- clk_osm_write_reg(c, volt_val, VOLT_REG + table_entry_offset,
- OSM_BASE);
- clk_osm_write_reg(c, override_val, OVERRIDE_REG +
- table_entry_offset, OSM_BASE);
- }
-
- /* Make sure all writes go through */
- clk_osm_mb(c, OSM_BASE);
-
- return 0;
-}
-
-static void clk_osm_print_osm_table(struct clk_osm *c)
-{
- int i;
- struct osm_entry *table = c->osm_table;
- u32 pll_src, pll_div, lval, core_count;
-
- pr_debug("Index, Frequency, VC, OLV (mv), Core Count, PLL Src, PLL Div, L-Val, ACC Level\n");
- for (i = 0; i < c->num_entries; i++) {
- pll_src = (table[i].freq_data & GENMASK(31, 30)) >> 30;
- pll_div = (table[i].freq_data & GENMASK(29, 28)) >> 28;
- lval = table[i].freq_data & GENMASK(7, 0);
- core_count = (table[i].freq_data & GENMASK(18, 16)) >> 16;
-
- pr_debug("%3d, %11lu, %2u, %5u, %2u, %6u, %8u, %7u, %5u\n",
- i,
- table[i].frequency,
- table[i].virtual_corner,
- table[i].open_loop_volt,
- core_count,
- pll_src,
- pll_div,
- lval,
- table[i].mem_acc_level);
- }
- pr_debug("APM threshold corner=%d, crossover corner=%d\n",
- c->apm_threshold_vc, c->apm_crossover_vc);
- pr_debug("MEM-ACC threshold corner=%d, crossover corner=%d\n",
- c->mem_acc_threshold_vc, c->mem_acc_crossover_vc);
-}
-
static u32 find_voltage(struct clk_osm *c, unsigned long rate)
{
struct osm_entry *table = c->osm_table;
@@ -1890,196 +776,6 @@
return cycle_counter_ret;
}
-static void clk_osm_setup_cycle_counters(struct clk_osm *c)
-{
- u32 ratio = c->osm_clk_rate;
- u32 val = 0;
-
- /* Enable cycle counter */
- val = BIT(0);
- /* Setup OSM clock to XO ratio */
- do_div(ratio, c->xo_clk_rate);
- val |= BVAL(5, 1, ratio - 1) | OSM_CYCLE_COUNTER_USE_XO_EDGE_EN;
-
- clk_osm_write_reg(c, val, OSM_CYCLE_COUNTER_CTRL_REG, OSM_BASE);
- pr_debug("OSM to XO clock ratio: %d\n", ratio);
-}
-
-static int clk_osm_resolve_crossover_corners(struct clk_osm *c,
- struct platform_device *pdev)
-{
- struct regulator *regulator = c->vdd_reg;
- int count, vc, i, memacc_threshold, apm_threshold;
- int rc = 0;
- u32 corner_volt;
-
- if (c == &l3_clk || c == &pwrcl_clk)
- return rc;
-
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-apcs-apm-threshold-voltage",
- &apm_threshold);
- if (rc) {
- pr_err("qcom,perfcl-apcs-apm-threshold-voltage property not specified\n");
- return rc;
- }
-
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-apcs-mem-acc-threshold-voltage",
- &memacc_threshold);
- if (rc) {
- pr_err("qcom,perfcl-apcs-mem-acc-threshold-voltage property not specified\n");
- return rc;
- }
-
- /*
- * Initialize VC settings in case none of them go above the voltage
- * limits
- */
- c->apm_threshold_vc = c->apm_crossover_vc = c->mem_acc_crossover_vc =
- c->mem_acc_threshold_vc = MAX_VC;
-
- count = regulator_count_voltages(regulator);
- if (count < 0) {
- pr_err("Failed to get the number of virtual corners supported\n");
- return count;
- }
-
- c->apm_crossover_vc = count - 2;
- c->mem_acc_crossover_vc = count - 1;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- vc = c->osm_table[i].virtual_corner + 1;
- corner_volt = regulator_list_corner_voltage(regulator, vc);
-
- if (c->apm_threshold_vc == MAX_VC &&
- corner_volt >= apm_threshold)
- c->apm_threshold_vc = c->osm_table[i].virtual_corner;
-
- if (c->mem_acc_threshold_vc == MAX_VC &&
- corner_volt >= memacc_threshold)
- c->mem_acc_threshold_vc =
- c->osm_table[i].virtual_corner;
- }
-
- return rc;
-}
-
-static int clk_osm_resolve_open_loop_voltages(struct clk_osm *c)
-{
- struct regulator *regulator = c->vdd_reg;
- u32 vc, mv;
- int i;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- vc = c->osm_table[i].virtual_corner + 1;
- /* Voltage is in uv. Convert to mv */
- mv = regulator_list_corner_voltage(regulator, vc) / 1000;
- c->osm_table[i].open_loop_volt = mv;
- }
-
- return 0;
-}
-
-static int clk_osm_get_lut(struct platform_device *pdev,
- struct clk_osm *c, char *prop_name)
-{
- struct device_node *of = pdev->dev.of_node;
- int prop_len, total_elems, num_rows, i, j, k;
- int rc = 0;
- u32 *array;
- u32 *fmax_temp;
- u32 data;
- unsigned long abs_fmax = 0;
- bool last_entry = false;
-
- if (!of_find_property(of, prop_name, &prop_len)) {
- dev_err(&pdev->dev, "missing %s\n", prop_name);
- return -EINVAL;
- }
-
- total_elems = prop_len / sizeof(u32);
- if (total_elems % NUM_FIELDS) {
- dev_err(&pdev->dev, "bad length %d\n", prop_len);
- return -EINVAL;
- }
-
- num_rows = total_elems / NUM_FIELDS;
-
- fmax_temp = devm_kzalloc(&pdev->dev, num_rows * sizeof(unsigned long),
- GFP_KERNEL);
- if (!fmax_temp)
- return -ENOMEM;
-
- array = devm_kzalloc(&pdev->dev, prop_len, GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, prop_name, array, total_elems);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse OSM table, rc=%d\n", rc);
- goto exit;
- }
-
- pr_debug("%s: Entries in Table: %d\n", __func__, num_rows);
- c->num_entries = num_rows;
- if (c->num_entries > OSM_TABLE_SIZE) {
- pr_err("LUT entries %d exceed maximum size %d\n",
- c->num_entries, OSM_TABLE_SIZE);
- return -EINVAL;
- }
-
- for (i = 0, j = 0, k = 0; j < OSM_TABLE_SIZE; j++) {
- c->osm_table[j].frequency = array[i + FREQ];
- c->osm_table[j].freq_data = array[i + FREQ_DATA];
- c->osm_table[j].override_data = array[i + PLL_OVERRIDES];
- c->osm_table[j].mem_acc_level = array[i + MEM_ACC_LEVEL];
- /* Voltage corners are 0 based in the OSM LUT */
- c->osm_table[j].virtual_corner = array[i + VIRTUAL_CORNER] - 1;
- pr_debug("index=%d freq=%ld virtual_corner=%d freq_data=0x%x override_data=0x%x mem_acc_level=0x%x\n",
- j, c->osm_table[j].frequency,
- c->osm_table[j].virtual_corner,
- c->osm_table[j].freq_data,
- c->osm_table[j].override_data,
- c->osm_table[j].mem_acc_level);
-
- data = (array[i + FREQ_DATA] & GENMASK(29, 28)) >> 28;
- if (j && !c->min_cpr_vc && !data)
- c->min_cpr_vc = c->osm_table[j].virtual_corner;
-
- data = (array[i + FREQ_DATA] & GENMASK(18, 16)) >> 16;
- if (!last_entry && data == MAX_CORE_COUNT) {
- fmax_temp[k] = array[i];
- k++;
- }
-
- if (i < total_elems - NUM_FIELDS)
- i += NUM_FIELDS;
- else {
- abs_fmax = array[i];
- last_entry = true;
- }
- }
- fmax_temp[k++] = abs_fmax;
-
- osm_clks_init[c->cluster_num].rate_max = devm_kzalloc(&pdev->dev,
- k * sizeof(unsigned long),
- GFP_KERNEL);
- if (!osm_clks_init[c->cluster_num].rate_max) {
- rc = -ENOMEM;
- goto exit;
- }
-
- for (i = 0; i < k; i++)
- osm_clks_init[c->cluster_num].rate_max[i] = fmax_temp[i];
-
- osm_clks_init[c->cluster_num].num_rate_max = k;
-exit:
- devm_kfree(&pdev->dev, fmax_temp);
- devm_kfree(&pdev->dev, array);
- return rc;
-}
-
static int clk_osm_read_lut(struct platform_device *pdev, struct clk_osm *c)
{
u32 data, src, lval, i, j = OSM_TABLE_SIZE;
@@ -2123,494 +819,9 @@
return 0;
}
-static int clk_osm_parse_acd_dt_configs(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- l3_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_acd") != NULL ? true : false;
- pwrcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_acd") != NULL ? true : false;
- perfcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_acd") != NULL ? true : false;
-
- if (pwrcl_clk.acd_init || perfcl_clk.acd_init || l3_clk.acd_init) {
- rc = of_property_read_u32_array(of, "qcom,acdtd-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdtd-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_td = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_td = array[perfcl_clk.cluster_num];
- l3_clk.acd_td = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdcr-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdcr-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_cr = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_cr = array[perfcl_clk.cluster_num];
- l3_clk.acd_cr = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdsscr-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdsscr-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_sscr = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_sscr = array[perfcl_clk.cluster_num];
- l3_clk.acd_sscr = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdextint0-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdextint0-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_extint0_cfg = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_extint0_cfg = array[perfcl_clk.cluster_num];
- l3_clk.acd_extint0_cfg = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdextint1-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdextint1-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_extint1_cfg = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_extint1_cfg = array[perfcl_clk.cluster_num];
- l3_clk.acd_extint1_cfg = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdautoxfer-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdautoxfer-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_autoxfer_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_autoxfer_ctl = array[perfcl_clk.cluster_num];
- l3_clk.acd_autoxfer_ctl = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavg-init",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavg-init property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_init = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_init = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_init = array[l3_clk.cluster_num];
- }
-
- if (pwrcl_clk.acd_avg_init || perfcl_clk.acd_avg_init ||
- l3_clk.acd_avg_init) {
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg0-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg0-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg0 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg0 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg0 = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg1-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg1-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg1 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg1 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg1 = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg2-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg2-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg2 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg2 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg2 = array[l3_clk.cluster_num];
- }
-
- devm_kfree(&pdev->dev, array);
- return rc;
-}
-
-static int clk_osm_parse_dt_configs(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- char memacc_str[40];
- int rc = 0;
- struct resource *res;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, "qcom,l-val-base",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,l-val-base property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.l_val_base = array[l3_clk.cluster_num];
- pwrcl_clk.l_val_base = array[pwrcl_clk.cluster_num];
- perfcl_clk.l_val_base = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-pll-user-ctl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-pll-user-ctl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_pll_user_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_pll_user_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_pll_user_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-pll-min-freq",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-pll-min-freq property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_pll_min_freq = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_pll_min_freq = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_pll_min_freq = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apm-mode-ctl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apm-mode-ctl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apm_mode_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apm_mode_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apm_mode_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apm-status-ctrl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apm-status-ctrl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apm_status_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apm_status_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apm_status_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,cfg-gfmux-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,cfg-gfmux-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.cfg_gfmux_addr = array[l3_clk.cluster_num];
- pwrcl_clk.cfg_gfmux_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.cfg_gfmux_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-cbc-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-cbc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_cbc_addr = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_cbc_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_cbc_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-ramp-ctl-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-ramp-ctl-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.ramp_ctl_addr = array[l3_clk.cluster_num];
- pwrcl_clk.ramp_ctl_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.ramp_ctl_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32(of, "qcom,xo-clk-rate",
- &pwrcl_clk.xo_clk_rate);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,xo-clk-rate property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.xo_clk_rate = perfcl_clk.xo_clk_rate = pwrcl_clk.xo_clk_rate;
-
- rc = of_property_read_u32(of, "qcom,osm-clk-rate",
- &pwrcl_clk.osm_clk_rate);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,osm-clk-rate property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- l3_clk.osm_clk_rate = perfcl_clk.osm_clk_rate = pwrcl_clk.osm_clk_rate;
-
- rc = of_property_read_u32(of, "qcom,cc-reads",
- &pwrcl_clk.cycle_counter_reads);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,cc-reads property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- l3_clk.cycle_counter_reads = perfcl_clk.cycle_counter_reads =
- pwrcl_clk.cycle_counter_reads;
-
- rc = of_property_read_u32(of, "qcom,cc-delay",
- &pwrcl_clk.cycle_counter_delay);
- if (rc)
- dev_dbg(&pdev->dev, "no delays between cycle counter reads\n");
- else
- l3_clk.cycle_counter_delay = perfcl_clk.cycle_counter_delay =
- pwrcl_clk.cycle_counter_delay;
-
- rc = of_property_read_u32(of, "qcom,cc-factor",
- &pwrcl_clk.cycle_counter_factor);
- if (rc)
- dev_dbg(&pdev->dev, "no factor specified for cycle counter estimation\n");
- else
- l3_clk.cycle_counter_factor = perfcl_clk.cycle_counter_factor =
- pwrcl_clk.cycle_counter_factor;
-
- l3_clk.red_fsm_en = perfcl_clk.red_fsm_en = pwrcl_clk.red_fsm_en =
- of_property_read_bool(of, "qcom,red-fsm-en");
-
- l3_clk.boost_fsm_en = perfcl_clk.boost_fsm_en =
- pwrcl_clk.boost_fsm_en =
- of_property_read_bool(of, "qcom,boost-fsm-en");
-
- l3_clk.safe_fsm_en = perfcl_clk.safe_fsm_en = pwrcl_clk.safe_fsm_en =
- of_property_read_bool(of, "qcom,safe-fsm-en");
-
- l3_clk.ps_fsm_en = perfcl_clk.ps_fsm_en = pwrcl_clk.ps_fsm_en =
- of_property_read_bool(of, "qcom,ps-fsm-en");
-
- l3_clk.droop_fsm_en = perfcl_clk.droop_fsm_en =
- pwrcl_clk.droop_fsm_en =
- of_property_read_bool(of, "qcom,droop-fsm-en");
-
- devm_kfree(&pdev->dev, array);
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for l3_sequencer\n");
- return -ENOMEM;
- }
-
- l3_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- l3_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!l3_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map l3_sequencer base\n");
- return -ENOMEM;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for pwrcl_sequencer\n");
- return -ENOMEM;
- }
-
- pwrcl_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- pwrcl_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!pwrcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map pwrcl_sequencer base\n");
- return -ENOMEM;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for perfcl_sequencer\n");
- return -ENOMEM;
- }
-
- perfcl_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- perfcl_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!perfcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map perfcl_sequencer base\n");
- return -ENOMEM;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,l3-memacc-level-vc-bin%d", l3_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str, l3_clk.mem_acc_level_vc,
- MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,pwrcl-memacc-level-vc-bin%d", pwrcl_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str,
- pwrcl_clk.mem_acc_level_vc, MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,perfcl-memacc-level-vc-bin%d", pwrcl_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str,
- perfcl_clk.mem_acc_level_vc, MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- l3_clk.secure_init = perfcl_clk.secure_init = pwrcl_clk.secure_init =
- of_property_read_bool(pdev->dev.of_node, "qcom,osm-no-tz");
-
- if (!pwrcl_clk.secure_init)
- return rc;
-
- rc = of_property_read_u32_array(of, "qcom,l3-mem-acc-addr",
- l3_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,l3-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- rc = of_property_read_u32_array(of, "qcom,pwrcl-mem-acc-addr",
- pwrcl_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,pwrcl-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- rc = of_property_read_u32_array(of, "qcom,perfcl-mem-acc-addr",
- perfcl_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,perfcl-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- return rc;
-}
-
-static int clk_osm_acd_resources_init(struct platform_device *pdev)
-{
- struct resource *res;
- unsigned long pbase;
- void *vbase;
- int rc = 0;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_acd base\n");
- return -ENOMEM;
- }
- pwrcl_clk.pbases[ACD_BASE] = pbase;
- pwrcl_clk.vbases[ACD_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_acd base\n");
- return -ENOMEM;
- }
- perfcl_clk.pbases[ACD_BASE] = pbase;
- perfcl_clk.vbases[ACD_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map l3_acd base\n");
- return -ENOMEM;
- }
- l3_clk.pbases[ACD_BASE] = pbase;
- l3_clk.vbases[ACD_BASE] = vbase;
- }
- return rc;
-}
-
static int clk_osm_resources_init(struct platform_device *pdev)
{
- struct device_node *node;
struct resource *res;
- unsigned long pbase;
- int rc = 0;
- void *vbase;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"osm_l3_base");
@@ -2620,21 +831,14 @@
return -ENOMEM;
}
- l3_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- l3_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ l3_clk.pbase = (unsigned long)res->start;
+ l3_clk.vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!l3_clk.vbases[OSM_BASE]) {
+ if (!l3_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_l3_base base\n");
return -ENOMEM;
}
- /* Check if OSM has been enabled already by trustzone. */
- if (readl_relaxed(l3_clk.vbases[OSM_BASE] + ENABLE_REG) & ENABLE_OSM) {
- dev_info(&pdev->dev, "OSM has been initialized and enabled by TZ software\n");
- osm_tz_enabled = true;
- }
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"osm_pwrcl_base");
if (!res) {
@@ -2643,10 +847,10 @@
return -ENOMEM;
}
- pwrcl_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- pwrcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
+ pwrcl_clk.pbase = (unsigned long)res->start;
+ pwrcl_clk.vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (!pwrcl_clk.vbases[OSM_BASE]) {
+ if (!pwrcl_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_pwrcl_base base\n");
return -ENOMEM;
}
@@ -2659,394 +863,26 @@
return -ENOMEM;
}
- perfcl_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- perfcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
+ perfcl_clk.pbase = (unsigned long)res->start;
+ perfcl_clk.vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (!perfcl_clk.vbases[OSM_BASE]) {
+ if (!perfcl_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_perfcl_base base\n");
return -ENOMEM;
}
- if (osm_tz_enabled)
- return rc;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l3_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for l3_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map l3_pll base\n");
- return -ENOMEM;
- }
-
- l3_clk.pbases[PLL_BASE] = pbase;
- l3_clk.vbases[PLL_BASE] = vbase;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrcl_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for pwrcl_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_pll base\n");
- return -ENOMEM;
- }
-
- pwrcl_clk.pbases[PLL_BASE] = pbase;
- pwrcl_clk.vbases[PLL_BASE] = vbase;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "perfcl_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for perfcl_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_pll base\n");
- return -ENOMEM;
- }
-
- perfcl_clk.pbases[PLL_BASE] = pbase;
- perfcl_clk.vbases[PLL_BASE] = vbase;
-
- /* efuse speed bin fuses are optional */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map in l3_efuse base\n");
- return -ENOMEM;
- }
- l3_clk.pbases[EFUSE_BASE] = pbase;
- l3_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_efuse base\n");
- return -ENOMEM;
- }
- pwrcl_clk.pbases[EFUSE_BASE] = pbase;
- pwrcl_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_efuse base\n");
- return -ENOMEM;
- }
- perfcl_clk.pbases[EFUSE_BASE] = pbase;
- perfcl_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- vdd_l3 = devm_regulator_get(&pdev->dev, "vdd-l3");
- if (IS_ERR(vdd_l3)) {
- rc = PTR_ERR(vdd_l3);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the l3 vreg, rc=%d\n",
- rc);
- return rc;
- }
- l3_clk.vdd_reg = vdd_l3;
-
- vdd_pwrcl = devm_regulator_get(&pdev->dev, "vdd-pwrcl");
- if (IS_ERR(vdd_pwrcl)) {
- rc = PTR_ERR(vdd_pwrcl);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the pwrcl vreg, rc=%d\n",
- rc);
- return rc;
- }
- pwrcl_clk.vdd_reg = vdd_pwrcl;
-
- vdd_perfcl = devm_regulator_get(&pdev->dev, "vdd-perfcl");
- if (IS_ERR(vdd_perfcl)) {
- rc = PTR_ERR(vdd_perfcl);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the perfcl vreg, rc=%d\n",
- rc);
- return rc;
- }
- perfcl_clk.vdd_reg = vdd_perfcl;
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-l3-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-l3-supply\n");
- return -EINVAL;
- }
-
- l3_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!l3_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-l3-supply node\n");
- return -EINVAL;
- }
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-pwrcl-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-pwrcl-supply\n");
- return -EINVAL;
- }
-
- pwrcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!pwrcl_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-pwrcl-supply node\n");
- return -EINVAL;
- }
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-perfcl-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-perfcl-supply\n");
- return -EINVAL;
- }
-
- perfcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!perfcl_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-perfcl-supply\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int debugfs_get_debug_reg(void *data, u64 *val)
-{
- struct clk_osm *c = data;
-
- if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
- *val = readl_relaxed((char *)c->vbases[ACD_BASE] +
- c->acd_debugfs_addr);
- else
- *val = clk_osm_acd_local_read_reg(c, c->acd_debugfs_addr);
- return 0;
-}
-
-static int debugfs_set_debug_reg(void *data, u64 val)
-{
- struct clk_osm *c = data;
-
- if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
- clk_osm_write_reg(c, val, c->acd_debugfs_addr, ACD_BASE);
- else
- clk_osm_acd_master_write_through_reg(c, val,
- c->acd_debugfs_addr);
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_fops,
- debugfs_get_debug_reg,
- debugfs_set_debug_reg,
- "0x%llx\n");
-
-static int debugfs_get_debug_reg_addr(void *data, u64 *val)
-{
- struct clk_osm *c = data;
-
- *val = c->acd_debugfs_addr;
- return 0;
-}
-
-static int debugfs_set_debug_reg_addr(void *data, u64 val)
-{
- struct clk_osm *c = data;
-
- if (val > ACD_1P1_MAX_REG_OFFSET) {
- pr_err("invalid ACD register address offset, must be between 0-0x%x\n",
- ACD_1P1_MAX_REG_OFFSET);
- return 0;
- }
-
- c->acd_debugfs_addr = val;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_addr_fops,
- debugfs_get_debug_reg_addr,
- debugfs_set_debug_reg_addr,
- "%llu\n");
-
-static void populate_debugfs_dir(struct clk_osm *c)
-{
- struct dentry *temp;
-
- if (osm_debugfs_base == NULL) {
- osm_debugfs_base = debugfs_create_dir("osm", NULL);
- if (IS_ERR_OR_NULL(osm_debugfs_base)) {
- pr_err("osm debugfs base directory creation failed\n");
- osm_debugfs_base = NULL;
- return;
- }
- }
-
- c->debugfs = debugfs_create_dir(clk_hw_get_name(&c->hw),
- osm_debugfs_base);
- if (IS_ERR_OR_NULL(c->debugfs)) {
- pr_err("osm debugfs directory creation failed\n");
- return;
- }
-
- temp = debugfs_create_file("acd_debug_reg",
- 0644,
- c->debugfs, c,
- &debugfs_acd_debug_reg_fops);
- if (IS_ERR_OR_NULL(temp)) {
- pr_err("debugfs_acd_debug_reg_fops debugfs file creation failed\n");
- goto exit;
- }
-
- temp = debugfs_create_file("acd_debug_reg_addr",
- 0644,
- c->debugfs, c,
- &debugfs_acd_debug_reg_addr_fops);
- if (IS_ERR_OR_NULL(temp)) {
- pr_err("debugfs_acd_debug_reg_addr_fops debugfs file creation failed\n");
- goto exit;
- }
-
-exit:
- if (IS_ERR_OR_NULL(temp))
- debugfs_remove_recursive(c->debugfs);
-}
-
-static int clk_osm_acd_init(struct clk_osm *c)
-{
-
- int rc = 0;
- u32 auto_xfer_mask = 0;
-
- if (c->secure_init) {
- clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACDCR,
- DATA_MEM(115), OSM_BASE);
- clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACD_WRITE_CTL,
- DATA_MEM(116), OSM_BASE);
- }
-
- if (!c->acd_init)
- return 0;
-
- c->acd_debugfs_addr = ACD_HW_VERSION;
-
- /* Program ACD tunable-length delay register */
- clk_osm_write_reg(c, c->acd_td, ACDTD, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDTD);
-
- /* Program ACD control register */
- clk_osm_write_reg(c, c->acd_cr, ACDCR, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDCR);
-
- /* Program ACD soft start control register */
- clk_osm_write_reg(c, c->acd_sscr, ACDSSCR, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDSSCR);
-
- /* Program initial ACD external interface configuration register */
- clk_osm_write_reg(c, c->acd_extint0_cfg, ACD_EXTINT_CFG, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_EXTINT_CFG);
-
- /* Program ACD auto-register transfer control register */
- clk_osm_write_reg(c, c->acd_autoxfer_ctl, ACD_AUTOXFER_CTL, ACD_BASE);
-
- /* Ensure writes complete before transfers to local copy */
- clk_osm_acd_mb(c);
-
- /* Transfer master copies */
- rc = clk_osm_acd_auto_local_write_reg(c, auto_xfer_mask);
- if (rc)
- return rc;
-
- /* Switch CPUSS clock source to ACD clock */
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_GFMUX_CFG);
- rc = clk_osm_acd_master_write_through_reg(c, ACD_GFMUX_CFG_SELECT,
- ACD_GFMUX_CFG);
- if (rc)
- return rc;
-
- /* Program ACD_DCVS_SW */
- rc = clk_osm_acd_master_write_through_reg(c,
- ACD_DCVS_SW_DCVS_IN_PRGR_SET,
- ACD_DCVS_SW);
- if (rc)
- return rc;
-
- rc = clk_osm_acd_master_write_through_reg(c,
- ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR,
- ACD_DCVS_SW);
- if (rc)
- return rc;
-
- udelay(1);
-
- /* Program final ACD external interface configuration register */
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_extint1_cfg,
- ACD_EXTINT_CFG);
- if (rc)
- return rc;
-
- if (c->acd_avg_init) {
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_2);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg2,
- ACD_AVG_CFG_2);
- if (rc)
- return rc;
-
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_1);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg1,
- ACD_AVG_CFG_1);
- if (rc)
- return rc;
-
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_0);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg0,
- ACD_AVG_CFG_0);
- if (rc)
- return rc;
- }
-
- /*
- * ACDCR, ACDTD, ACDSSCR, ACD_EXTINT_CFG, ACD_GFMUX_CFG
- * must be copied from master to local copy on PC exit.
- * Also, ACD_AVG_CFG0, ACF_AVG_CFG1, and ACD_AVG_CFG2 when
- * AVG is enabled.
- */
- clk_osm_write_reg(c, auto_xfer_mask, ACD_AUTOXFER_CFG, ACD_BASE);
return 0;
}
static int clk_cpu_osm_driver_probe(struct platform_device *pdev)
{
int rc = 0, i;
- int pvs_ver = 0;
- u32 pte_efuse, val;
+ u32 val;
int num_clks = ARRAY_SIZE(osm_qcom_clk_hws);
struct clk *ext_xo_clk, *clk;
struct device *dev = &pdev->dev;
struct clk_onecell_data *clk_data;
- char l3speedbinstr[] = "qcom,l3-speedbin0-v0";
- char perfclspeedbinstr[] = "qcom,perfcl-speedbin0-v0";
- char pwrclspeedbinstr[] = "qcom,pwrcl-speedbin0-v0";
struct cpu_cycle_counter_cb cb = {
.get_cpu_cycle_counter = clk_osm_get_cpu_cycle_counter,
};
@@ -3085,282 +921,34 @@
return rc;
}
- if (!osm_tz_enabled) {
- if (l3_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse = readl_relaxed(l3_clk.vbases[EFUSE_BASE]);
- l3_clk.speedbin = ((pte_efuse >> L3_EFUSE_SHIFT) &
- L3_EFUSE_MASK);
- snprintf(l3speedbinstr, ARRAY_SIZE(l3speedbinstr),
- "qcom,l3-speedbin%d-v%d", l3_clk.speedbin, pvs_ver);
- }
+ /* Check if per-core DCVS is enabled/not */
+ val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
+ if (val && BIT(0))
+ pwrcl_clk.per_core_dcvs = true;
- dev_info(&pdev->dev, "using L3 speed bin %u and pvs_ver %d\n",
- l3_clk.speedbin, pvs_ver);
+ val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
+ if (val && BIT(0))
+ perfcl_clk.per_core_dcvs = true;
- rc = clk_osm_get_lut(pdev, &l3_clk, l3speedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for L3, rc=%d\n",
- rc);
- return rc;
- }
+ rc = clk_osm_read_lut(pdev, &l3_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for L3, rc=%d\n",
+ rc);
+ return rc;
+ }
- if (pwrcl_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse = readl_relaxed(pwrcl_clk.vbases[EFUSE_BASE]);
- pwrcl_clk.speedbin = ((pte_efuse >> PWRCL_EFUSE_SHIFT) &
- PWRCL_EFUSE_MASK);
- snprintf(pwrclspeedbinstr, ARRAY_SIZE(pwrclspeedbinstr),
- "qcom,pwrcl-speedbin%d-v%d", pwrcl_clk.speedbin,
- pvs_ver);
- }
+ rc = clk_osm_read_lut(pdev, &pwrcl_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for power cluster, rc=%d\n",
+ rc);
+ return rc;
+ }
- dev_info(&pdev->dev, "using pwrcl speed bin %u and pvs_ver %d\n",
- pwrcl_clk.speedbin, pvs_ver);
-
- rc = clk_osm_get_lut(pdev, &pwrcl_clk, pwrclspeedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for power cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- if (perfcl_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse =
- readl_relaxed(perfcl_clk.vbases[EFUSE_BASE]);
- perfcl_clk.speedbin = ((pte_efuse >> PERFCL_EFUSE_SHIFT)
- & PERFCL_EFUSE_MASK);
- snprintf(perfclspeedbinstr,
- ARRAY_SIZE(perfclspeedbinstr),
- "qcom,perfcl-speedbin%d-v%d",
- perfcl_clk.speedbin, pvs_ver);
- }
-
- dev_info(&pdev->dev, "using perfcl speed bin %u and pvs_ver %d\n",
- perfcl_clk.speedbin, pvs_ver);
-
- rc = clk_osm_get_lut(pdev, &perfcl_clk, perfclspeedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_parse_dt_configs(pdev);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse OSM device tree configurations\n");
- return rc;
- }
-
- rc = clk_osm_parse_acd_dt_configs(pdev);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse ACD device tree configurations\n");
- return rc;
- }
-
- rc = clk_osm_acd_resources_init(pdev);
- if (rc) {
- dev_err(&pdev->dev, "ACD resources init failed, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_resolve_open_loop_voltages(&l3_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for L3, rc=%d\n",
- rc);
- return rc;
- }
- rc = clk_osm_resolve_open_loop_voltages(&pwrcl_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for power cluster, rc=%d\n",
- rc);
- return rc;
- }
- rc = clk_osm_resolve_open_loop_voltages(&perfcl_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_resolve_crossover_corners(&l3_clk, pdev);
- if (rc)
- dev_info(&pdev->dev,
- "No APM crossover corner programmed for L3\n");
- rc = clk_osm_resolve_crossover_corners(&pwrcl_clk, pdev);
- if (rc)
- dev_info(&pdev->dev,
- "No APM crossover corner programmed for pwrcl_clk\n");
- rc = clk_osm_resolve_crossover_corners(&perfcl_clk, pdev);
- if (rc)
- dev_info(&pdev->dev, "No MEM-ACC crossover corner programmed\n");
-
- clk_osm_setup_cycle_counters(&l3_clk);
- clk_osm_setup_cycle_counters(&pwrcl_clk);
- clk_osm_setup_cycle_counters(&perfcl_clk);
-
- clk_osm_print_osm_table(&l3_clk);
- clk_osm_print_osm_table(&pwrcl_clk);
- clk_osm_print_osm_table(&perfcl_clk);
-
- rc = clk_osm_setup_hw_table(&l3_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup l3 hardware table\n");
- goto exit;
- }
- rc = clk_osm_setup_hw_table(&pwrcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup power cluster hardware table\n");
- goto exit;
- }
- rc = clk_osm_setup_hw_table(&perfcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup perf cluster hardware table\n");
- goto exit;
- }
-
- /* Policy tuning */
- rc = clk_osm_set_cc_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "cc policy setup failed");
- goto exit;
- }
-
- /* LLM Freq Policy Tuning */
- rc = clk_osm_set_llm_freq_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "LLM Frequency Policy setup failed");
- goto exit;
- }
-
- /* LLM Voltage Policy Tuning */
- rc = clk_osm_set_llm_volt_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "Failed to set LLM voltage Policy");
- goto exit;
- }
-
- clk_osm_setup_fsms(&l3_clk);
- clk_osm_setup_fsms(&pwrcl_clk);
- clk_osm_setup_fsms(&perfcl_clk);
-
- /*
- * Program the VC at which the array power supply
- * needs to be switched.
- */
- clk_osm_write_reg(&perfcl_clk, perfcl_clk.apm_threshold_vc,
- APM_CROSSOVER_VC, OSM_BASE);
- if (perfcl_clk.secure_init) {
- clk_osm_write_seq_reg(&perfcl_clk,
- perfcl_clk.apm_crossover_vc, DATA_MEM(77));
- clk_osm_write_seq_reg(&perfcl_clk,
- (0x39 | (perfcl_clk.apm_threshold_vc << 6)),
- DATA_MEM(111));
- } else {
- scm_io_write(perfcl_clk.pbases[SEQ_BASE] + DATA_MEM(77),
- perfcl_clk.apm_crossover_vc);
- scm_io_write(perfcl_clk.pbases[SEQ_BASE] +
- DATA_MEM(111),
- (0x39 | (perfcl_clk.apm_threshold_vc << 6)));
- }
-
- /*
- * Perform typical secure-world HW initialization
- * as necessary.
- */
- clk_osm_do_additional_setup(&l3_clk, pdev);
- clk_osm_do_additional_setup(&pwrcl_clk, pdev);
- clk_osm_do_additional_setup(&perfcl_clk, pdev);
-
- /* MEM-ACC Programming */
- clk_osm_program_mem_acc_regs(&l3_clk);
- clk_osm_program_mem_acc_regs(&pwrcl_clk);
- clk_osm_program_mem_acc_regs(&perfcl_clk);
-
- if (of_property_read_bool(pdev->dev.of_node,
- "qcom,osm-pll-setup")) {
- clk_osm_setup_cluster_pll(&l3_clk);
- clk_osm_setup_cluster_pll(&pwrcl_clk);
- clk_osm_setup_cluster_pll(&perfcl_clk);
- }
-
- /* Misc programming */
- clk_osm_misc_programming(&l3_clk);
- clk_osm_misc_programming(&pwrcl_clk);
- clk_osm_misc_programming(&perfcl_clk);
-
- rc = clk_osm_acd_init(&l3_clk);
- if (rc) {
- pr_err("failed to initialize ACD for L3, rc=%d\n", rc);
- goto exit;
- }
- rc = clk_osm_acd_init(&pwrcl_clk);
- if (rc) {
- pr_err("failed to initialize ACD for pwrcl, rc=%d\n",
- rc);
- goto exit;
- }
- rc = clk_osm_acd_init(&perfcl_clk);
- if (rc) {
- pr_err("failed to initialize ACD for perfcl, rc=%d\n",
- rc);
- goto exit;
- }
-
- pwrcl_clk.per_core_dcvs = perfcl_clk.per_core_dcvs =
- of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-per-core-dcvs");
- if (pwrcl_clk.per_core_dcvs) {
- val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
- val |= BIT(0);
- clk_osm_write_reg(&pwrcl_clk, val, CORE_DCVS_CTRL,
- OSM_BASE);
- val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
- val |= BIT(0);
- clk_osm_write_reg(&perfcl_clk, val, CORE_DCVS_CTRL,
- OSM_BASE);
- }
- } else {
- /* OSM has been enabled already by trustzone */
- rc = clk_osm_read_lut(pdev, &l3_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for L3, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_read_lut(pdev, &pwrcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for power cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_read_lut(pdev, &perfcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- /* Check if per-core DCVS is enabled/not */
- val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
- if (val && BIT(0))
- pwrcl_clk.per_core_dcvs = true;
-
- val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
- if (val && BIT(0))
- perfcl_clk.per_core_dcvs = true;
-
- clk_ops_l3_osm.enable = NULL;
+ rc = clk_osm_read_lut(pdev, &perfcl_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for perf cluster, rc=%d\n",
+ rc);
+ return rc;
}
spin_lock_init(&l3_clk.lock);
@@ -3387,34 +975,10 @@
get_online_cpus();
- if (!osm_tz_enabled) {
- populate_debugfs_dir(&l3_clk);
- populate_debugfs_dir(&pwrcl_clk);
- populate_debugfs_dir(&perfcl_clk);
-
- /* Configure default rate to lowest frequency */
- for (i = 0; i < MAX_CORE_COUNT; i++) {
- osm_set_index(&pwrcl_clk, 0, i);
- osm_set_index(&perfcl_clk, 0, i);
- }
- }
- /*
- * Set the L3 clock to run off GPLL0 and enable OSM for the domain.
- * In the case that trustzone has already enabled OSM, bring the L3
- * clock rate to a safe level until the devfreq driver comes up and
- * votes for its desired frequency.
- */
- rc = clk_set_rate(l3_clk.hw.clk, OSM_INIT_RATE);
- if (rc) {
- dev_err(&pdev->dev, "Unable to set init rate on L3 cluster, rc=%d\n",
- rc);
- goto provider_err;
- }
WARN(clk_prepare_enable(l3_cluster0_vote_clk.hw.clk),
"clk: Failed to enable cluster0 clock for L3\n");
WARN(clk_prepare_enable(l3_cluster1_vote_clk.hw.clk),
"clk: Failed to enable cluster1 clock for L3\n");
- udelay(300);
populate_opp_table(pdev);
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
index e9ffb96..2c5b7ea 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.c
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -52,6 +52,10 @@
static void dspp_hsic_install_property(struct drm_crtc *crtc);
+static void dspp_memcolor_install_property(struct drm_crtc *crtc);
+
+static void dspp_sixzone_install_property(struct drm_crtc *crtc);
+
static void dspp_ad_install_property(struct drm_crtc *crtc);
static void dspp_vlut_install_property(struct drm_crtc *crtc);
@@ -85,6 +89,8 @@
do { \
func[SDE_DSPP_PCC] = dspp_pcc_install_property; \
func[SDE_DSPP_HSIC] = dspp_hsic_install_property; \
+ func[SDE_DSPP_MEMCOLOR] = dspp_memcolor_install_property; \
+ func[SDE_DSPP_SIXZONE] = dspp_sixzone_install_property; \
func[SDE_DSPP_AD] = dspp_ad_install_property; \
func[SDE_DSPP_VLUT] = dspp_vlut_install_property; \
func[SDE_DSPP_GAMUT] = dspp_gamut_install_property; \
@@ -108,11 +114,11 @@
SDE_CP_CRTC_DSPP_IGC,
SDE_CP_CRTC_DSPP_PCC,
SDE_CP_CRTC_DSPP_GC,
- SDE_CP_CRTC_DSPP_HUE,
- SDE_CP_CRTC_DSPP_SAT,
- SDE_CP_CRTC_DSPP_VAL,
- SDE_CP_CRTC_DSPP_CONT,
- SDE_CP_CRTC_DSPP_MEMCOLOR,
+ SDE_CP_CRTC_DSPP_HSIC,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKIN,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKY,
+ SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,
+ SDE_CP_CRTC_DSPP_MEMCOL_PROT,
SDE_CP_CRTC_DSPP_SIXZONE,
SDE_CP_CRTC_DSPP_GAMUT,
SDE_CP_CRTC_DSPP_DITHER,
@@ -667,40 +673,40 @@
}
hw_dspp->ops.setup_gc(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_HUE:
- if (!hw_dspp || !hw_dspp->ops.setup_hue) {
+ case SDE_CP_CRTC_DSPP_HSIC:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_hsic) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_hue(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_hsic(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_SAT:
- if (!hw_dspp || !hw_dspp->ops.setup_sat) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_SKIN:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_skin) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_sat(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_skin(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_VAL:
- if (!hw_dspp || !hw_dspp->ops.setup_val) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_SKY:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_sky) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_val(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_sky(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_CONT:
- if (!hw_dspp || !hw_dspp->ops.setup_cont) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_foliage) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_cont(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_foliage(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_MEMCOLOR:
- if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_PROT:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_prot) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_pa_memcolor(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_prot(hw_dspp, &hw_cfg);
break;
case SDE_CP_CRTC_DSPP_SIXZONE:
if (!hw_dspp || !hw_dspp->ops.setup_sixzone) {
@@ -1214,9 +1220,72 @@
switch (version) {
case 1:
snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "SDE_DSPP_HUE_V", version);
- sde_cp_crtc_install_range_property(crtc, feature_name,
- SDE_CP_CRTC_DSPP_HUE, 0, U32_MAX, 0);
+ "SDE_DSPP_PA_HSIC_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_HSIC, sizeof(struct drm_msm_pa_hsic));
+ break;
+ default:
+ DRM_ERROR("version %d not supported\n", version);
+ break;
+ }
+}
+
+static void dspp_memcolor_install_property(struct drm_crtc *crtc)
+{
+ char feature_name[256];
+ struct sde_kms *kms = NULL;
+ struct sde_mdss_cfg *catalog = NULL;
+ u32 version;
+
+ kms = get_kms(crtc);
+ catalog = kms->catalog;
+ version = catalog->dspp[0].sblk->memcolor.version >> 16;
+ switch (version) {
+ case 1:
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_SKIN_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKIN,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_SKY_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKY,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_FOLIAGE_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_PROT_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_PROT,
+ sizeof(struct drm_msm_memcol));
+ break;
+ default:
+ DRM_ERROR("version %d not supported\n", version);
+ break;
+ }
+}
+
+static void dspp_sixzone_install_property(struct drm_crtc *crtc)
+{
+ char feature_name[256];
+ struct sde_kms *kms = NULL;
+ struct sde_mdss_cfg *catalog = NULL;
+ u32 version;
+
+ kms = get_kms(crtc);
+ catalog = kms->catalog;
+ version = catalog->dspp[0].sblk->sixzone.version >> 16;
+ switch (version) {
+ case 1:
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_SIXZONE_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_SIXZONE,
+ sizeof(struct drm_msm_sixzone));
break;
default:
DRM_ERROR("version %d not supported\n", version);
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h
index aff07ef..7eb1738 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.h
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h
@@ -26,7 +26,8 @@
enum sde_memcolor_type {
MEMCOLOR_SKIN = 0,
MEMCOLOR_SKY,
- MEMCOLOR_FOLIAGE
+ MEMCOLOR_FOLIAGE,
+ MEMCOLOR_MAX
};
/*
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h b/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
index 6896ba7..3d2c0a5 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
@@ -66,4 +66,42 @@
#define PCC_GG_OFF 0x70
#define PCC_BB_OFF 0x7c
+#define PA_EN BIT(20)
+#define PA_HUE_EN BIT(25)
+#define PA_SAT_EN BIT(26)
+#define PA_VAL_EN BIT(27)
+#define PA_CONT_EN BIT(28)
+
+#define PA_SIXZONE_HUE_EN BIT(29)
+#define PA_SIXZONE_SAT_EN BIT(30)
+#define PA_SIXZONE_VAL_EN BIT(31)
+
+#define PA_HIST_EN BIT(16)
+
+#define PA_SKIN_EN BIT(7)
+#define PA_FOL_EN BIT(6)
+#define PA_SKY_EN BIT(5)
+
+#define PA_HUE_MASK (BIT(12) - 1)
+#define PA_SAT_MASK (BIT(16) - 1)
+#define PA_VAL_MASK (BIT(8) - 1)
+#define PA_CONT_MASK (BIT(8) - 1)
+
+#define PA_HUE_OFF 0x1c
+#define PA_SAT_OFF 0x20
+#define PA_VAL_OFF 0x24
+#define PA_CONT_OFF 0x28
+#define PA_PWL_HOLD_OFF 0x40
+
+#define PA_DISABLE_REQUIRED(x) \
+ !((x) & (PA_SKIN_EN | PA_SKY_EN | \
+ PA_FOL_EN | PA_HUE_EN | \
+ PA_SAT_EN | PA_VAL_EN | \
+ PA_CONT_EN | PA_HIST_EN | \
+ PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN | \
+ PA_SIXZONE_VAL_EN))
+
+#define SIXZONE_ADJ_CURVE_P1_OFF 0x4
+#define SIXZONE_THRESHOLDS_OFF 0x8
+
#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
index 8e54a2a..d32459a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
@@ -14,15 +14,17 @@
#include "sde_hw_color_processing_v1_7.h"
#include "sde_hw_ctl.h"
+#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
+
#define PA_HUE_VIG_OFF 0x110
#define PA_SAT_VIG_OFF 0x114
#define PA_VAL_VIG_OFF 0x118
#define PA_CONT_VIG_OFF 0x11C
-#define PA_HUE_DSPP_OFF 0x238
-#define PA_SAT_DSPP_OFF 0x23C
-#define PA_VAL_DSPP_OFF 0x240
-#define PA_CONT_DSPP_OFF 0x244
+#define PA_HUE_DSPP_OFF 0x1c
+#define PA_SAT_DSPP_OFF 0x20
+#define PA_VAL_DSPP_OFF 0x24
+#define PA_CONT_DSPP_OFF 0x28
#define PA_HIST_CTRL_DSPP_OFF 0x4
#define PA_HIST_DATA_DSPP_OFF 0x400
@@ -78,18 +80,44 @@
#define DSPP_OP_PA_FOL_EN BIT(6)
#define DSPP_OP_PA_SKY_EN BIT(7)
+#define DSPP_SZ_ADJ_CURVE_P1_OFF 0x4
+#define DSPP_SZ_THRESHOLDS_OFF 0x8
+#define DSPP_PA_PWL_HOLD_OFF 0x40
+
+#define DSPP_MEMCOL_SIZE0 0x14
+#define DSPP_MEMCOL_SIZE1 0x8
+#define DSPP_MEMCOL_PWL0_OFF 0x0
+#define DSPP_MEMCOL_PWL2_OFF 0x3C
+#define DSPP_MEMCOL_HOLD_SIZE 0x4
+
+#define DSPP_MEMCOL_PROT_VAL_EN BIT(24)
+#define DSPP_MEMCOL_PROT_SAT_EN BIT(23)
+#define DSPP_MEMCOL_PROT_HUE_EN BIT(22)
+#define DSPP_MEMCOL_PROT_CONT_EN BIT(18)
+#define DSPP_MEMCOL_PROT_SIXZONE_EN BIT(17)
+#define DSPP_MEMCOL_PROT_BLEND_EN BIT(3)
+
+#define DSPP_MEMCOL_MASK \
+ (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | DSPP_OP_PA_FOL_EN)
+
+#define DSPP_MEMCOL_PROT_MASK \
+ (DSPP_MEMCOL_PROT_HUE_EN | DSPP_MEMCOL_PROT_SAT_EN | \
+ DSPP_MEMCOL_PROT_VAL_EN | DSPP_MEMCOL_PROT_CONT_EN | \
+ DSPP_MEMCOL_PROT_SIXZONE_EN | DSPP_MEMCOL_PROT_BLEND_EN)
+
#define PA_VIG_DISABLE_REQUIRED(x) \
!((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
VIG_OP_PA_CONT_EN))
-
#define PA_DSPP_DISABLE_REQUIRED(x) \
!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \
DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \
DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \
- DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))
+ DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN | \
+ DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN | \
+ DSPP_OP_SZ_VAL_EN))
#define DSPP_OP_PCC_ENABLE BIT(0)
#define PCC_OP_MODE_OFF 0
@@ -116,30 +144,27 @@
static void __setup_pa_hue(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t hue,
- int location)
+ const struct sde_pp_blk *blk, u32 hue, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
- u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :
- VIG_OP_PA_HUE_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
+ u32 op_hue_en = (loc == DSPP) ? DSPP_OP_PA_HUE_EN : VIG_OP_PA_HUE_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
if (!hue) {
opmode &= ~op_hue_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_hue_en | op_pa_en;
+ opmode |= (op_hue_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -152,38 +177,28 @@
__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);
}
-void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg)
-{
- uint32_t hue = *((uint32_t *)cfg);
-
- __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
-}
-
static void __setup_pa_sat(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t sat,
- int location)
+ const struct sde_pp_blk *blk, u32 sat, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
- u32 op_sat_en = (location == DSPP) ?
- DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
+ u32 op_sat_en = (loc == DSPP) ? DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
if (!sat) {
opmode &= ~op_sat_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_sat_en | op_pa_en;
+ opmode |= (op_sat_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -197,30 +212,27 @@
}
static void __setup_pa_val(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t value,
- int location)
+ const struct sde_pp_blk *blk, u32 value, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
- u32 op_val_en = (location == DSPP) ?
- DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
+ u32 op_val_en = (loc == DSPP) ? DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
if (!value) {
opmode &= ~op_val_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_val_en | op_pa_en;
+ opmode |= (op_val_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -234,30 +246,28 @@
}
static void __setup_pa_cont(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t contrast,
- int location)
+ const struct sde_pp_blk *blk, u32 contrast, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
- u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :
- VIG_OP_PA_CONT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
+ u32 op_cont_en = (loc == DSPP) ?
+ DSPP_OP_PA_CONT_EN : VIG_OP_PA_CONT_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
if (!contrast) {
opmode &= ~op_cont_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_cont_en | op_pa_en;
+ opmode |= (op_cont_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -270,6 +280,120 @@
__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);
}
+void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_pa_hsic *hsic_cfg;
+ u32 hue = 0;
+ u32 sat = 0;
+ u32 val = 0;
+ u32 cont = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ if (hw_cfg->payload &&
+ (hw_cfg->len != sizeof(struct drm_msm_pa_hsic))) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_pa_hsic));
+ return;
+ }
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable pa hsic feature\n");
+ } else {
+ hsic_cfg = hw_cfg->payload;
+ if (hsic_cfg->flags & PA_HSIC_HUE_ENABLE)
+ hue = hsic_cfg->hue;
+ if (hsic_cfg->flags & PA_HSIC_SAT_ENABLE)
+ sat = hsic_cfg->saturation;
+ if (hsic_cfg->flags & PA_HSIC_VAL_ENABLE)
+ val = hsic_cfg->value;
+ if (hsic_cfg->flags & PA_HSIC_CONT_ENABLE)
+ cont = hsic_cfg->contrast;
+ }
+
+ __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
+ __setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic, sat, DSPP);
+ __setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic, val, DSPP);
+ __setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic, cont, DSPP);
+}
+
+void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_sixzone *sixzone;
+ u32 opcode = 0, local_opcode = 0;
+ u32 reg = 0, hold = 0, local_hold = 0;
+ u32 addr = 0;
+ int i = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable sixzone feature\n");
+ opcode &= ~(DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN |
+ DSPP_OP_SZ_VAL_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_sixzone));
+ return;
+ }
+
+ sixzone = hw_cfg->payload;
+
+ reg = BIT(26);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->sixzone.base, reg);
+
+ addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_ADJ_CURVE_P1_OFF;
+ for (i = 0; i < SIXZONE_LUT_SIZE; i++) {
+ SDE_REG_WRITE(&ctx->hw, addr, sixzone->curve[i].p1);
+ SDE_REG_WRITE(&ctx->hw, (addr - 4), sixzone->curve[i].p0);
+ }
+
+ addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_THRESHOLDS_OFF;
+ SDE_REG_WRITE(&ctx->hw, addr, sixzone->threshold);
+ SDE_REG_WRITE(&ctx->hw, (addr + 4), sixzone->adjust_p0);
+ SDE_REG_WRITE(&ctx->hw, (addr + 8), sixzone->adjust_p1);
+
+ hold = SDE_REG_READ(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF));
+ local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);
+ local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);
+ hold &= ~REG_MASK_SHIFT(4, 12);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF),
+ hold);
+
+ if (sixzone->flags & SIXZONE_HUE_ENABLE)
+ local_opcode |= DSPP_OP_SZ_HUE_EN;
+ if (sixzone->flags & SIXZONE_SAT_ENABLE)
+ local_opcode |= DSPP_OP_SZ_SAT_EN;
+ if (sixzone->flags & SIXZONE_VAL_ENABLE)
+ local_opcode |= DSPP_OP_SZ_VAL_EN;
+
+ if (local_opcode)
+ local_opcode |= DSPP_OP_PA_EN;
+
+ opcode &= ~REG_MASK_SHIFT(3, 29);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,
enum sde_memcolor_type type,
void *cfg)
@@ -333,6 +457,220 @@
SDE_REG_WRITE(&ctx->hw, base, op);
}
+static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,
+ enum sde_memcolor_type type,
+ struct drm_msm_memcol *memcolor)
+{
+ u32 addr = 0, offset = 0, idx = 0;
+ u32 hold = 0, local_hold = 0, hold_shift = 0;
+
+ switch (type) {
+ case MEMCOLOR_SKIN:
+ idx = 0;
+ break;
+ case MEMCOLOR_SKY:
+ idx = 1;
+ break;
+ case MEMCOLOR_FOLIAGE:
+ idx = 2;
+ break;
+ default:
+ DRM_ERROR("Invalid memory color type %d\n", type);
+ return;
+ }
+
+ offset = DSPP_MEMCOL_PWL0_OFF + (idx * DSPP_MEMCOL_SIZE0);
+ addr = ctx->cap->sblk->memcolor.base + offset;
+ hold_shift = idx * DSPP_MEMCOL_HOLD_SIZE;
+
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p0);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p1);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->hue_region);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->sat_region);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->val_region);
+
+ offset = DSPP_MEMCOL_PWL2_OFF + (idx * DSPP_MEMCOL_SIZE1);
+ addr = ctx->cap->sblk->memcolor.base + offset;
+
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p2);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->blend_gain);
+
+ addr = ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF;
+ hold = SDE_REG_READ(&ctx->hw, addr);
+ local_hold = ((memcolor->sat_hold & REG_MASK(2)) << hold_shift);
+ local_hold |=
+ ((memcolor->val_hold & REG_MASK(2)) << (hold_shift + 2));
+ hold &= ~REG_MASK_SHIFT(4, hold_shift);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw, addr, hold);
+}
+
+void sde_setup_dspp_memcol_skin_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor skin feature\n");
+ opcode &= ~(DSPP_OP_PA_SKIN_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_SKIN, memcolor);
+
+ opcode |= (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_sky_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor sky feature\n");
+ opcode &= ~(DSPP_OP_PA_SKY_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_SKY, memcolor);
+
+ opcode |= (DSPP_OP_PA_SKY_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_foliage_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor foliage feature\n");
+ opcode &= ~(DSPP_OP_PA_FOL_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_FOLIAGE, memcolor);
+
+ opcode |= (DSPP_OP_PA_FOL_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_prot_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0, local_opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor prot feature\n");
+ opcode &= ~(DSPP_MEMCOL_PROT_MASK);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ if (memcolor->prot_flags) {
+ if (memcolor->prot_flags & MEMCOL_PROT_HUE)
+ local_opcode |= DSPP_MEMCOL_PROT_HUE_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_SAT)
+ local_opcode |= DSPP_MEMCOL_PROT_SAT_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_VAL)
+ local_opcode |= DSPP_MEMCOL_PROT_VAL_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_CONT)
+ local_opcode |= DSPP_MEMCOL_PROT_CONT_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_SIXZONE)
+ local_opcode |= DSPP_MEMCOL_PROT_SIXZONE_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_BLEND)
+ local_opcode |= DSPP_MEMCOL_PROT_BLEND_EN;
+ }
+
+ if (local_opcode) {
+ local_opcode |= DSPP_OP_PA_EN;
+ opcode &= ~(DSPP_MEMCOL_PROT_MASK);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ }
+}
+
void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg)
{
struct sde_hw_cp_cfg *hw_cfg = cfg;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
index 74018a3..3c783ee 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
@@ -62,11 +62,46 @@
void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg);
/**
- * sde_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware
+ * sde_setup_dspp_pa_hsic_v17 - setup DSPP hsic feature in v1.7 hardware
* @ctx: Pointer to DSPP context
- * @cfg: Pointer to hue data
+ * @cfg: Pointer to hsic data
*/
-void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_skin_v17 - setup DSPP memcol skin in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_skin_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_sky_v17 - setup DSPP memcol sky in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_sky_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_foliage_v17 - setup DSPP memcol fol in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_foliage_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_prot_v17 - setup DSPP memcol prot in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_prot_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_sixzone_v17 - setup DSPP sixzone feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to sixzone data
+ */
+void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg);
/**
* sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index 36e30b7..b268e8f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -71,8 +71,28 @@
break;
case SDE_DSPP_HSIC:
if (c->cap->sblk->hsic.version ==
- (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_hue = sde_setup_dspp_pa_hue_v1_7;
+ SDE_COLOR_PROCESS_VER(0x1, 0x7))
+ c->ops.setup_pa_hsic =
+ sde_setup_dspp_pa_hsic_v17;
+ break;
+ case SDE_DSPP_MEMCOLOR:
+ if (c->cap->sblk->memcolor.version ==
+ SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
+ c->ops.setup_pa_memcol_skin =
+ sde_setup_dspp_memcol_skin_v17;
+ c->ops.setup_pa_memcol_sky =
+ sde_setup_dspp_memcol_sky_v17;
+ c->ops.setup_pa_memcol_foliage =
+ sde_setup_dspp_memcol_foliage_v17;
+ c->ops.setup_pa_memcol_prot =
+ sde_setup_dspp_memcol_prot_v17;
+ }
+ break;
+ case SDE_DSPP_SIXZONE:
+ if (c->cap->sblk->sixzone.version ==
+ SDE_COLOR_PROCESS_VER(0x1, 0x7))
+ c->ops.setup_sixzone =
+ sde_setup_dspp_sixzone_v17;
break;
case SDE_DSPP_VLUT:
if (c->cap->sblk->vlut.version ==
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
index 4878fc6..2b64165 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
@@ -52,11 +52,11 @@
void (*setup_igc)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_pa - setup dspp pa
+ * setup_pa_hsic - setup dspp pa hsic
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
*/
- void (*setup_pa)(struct sde_hw_dspp *dspp, void *cfg);
+ void (*setup_pa_hsic)(struct sde_hw_dspp *dspp, void *cfg);
/**
* setup_pcc - setup dspp pcc
@@ -73,11 +73,32 @@
void (*setup_sharpening)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_pa_memcolor - setup dspp memcolor
+ * setup_pa_memcol_skin - setup dspp memcolor skin
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
*/
- void (*setup_pa_memcolor)(struct sde_hw_dspp *ctx, void *cfg);
+ void (*setup_pa_memcol_skin)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_sky - setup dspp memcolor sky
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_sky)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_foliage - setup dspp memcolor foliage
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_foliage)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_prot - setup dspp memcolor protection
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_prot)(struct sde_hw_dspp *ctx, void *cfg);
/**
* setup_sixzone - setup dspp six zone
@@ -101,34 +122,6 @@
void (*setup_dither)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_hue - setup dspp PA hue
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_hue)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_sat - setup dspp PA saturation
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_sat)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_val - setup dspp PA value
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_val)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_cont - setup dspp PA contrast
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_cont)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
* setup_vlut - setup dspp PA VLUT
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index b59dd16..0dc3fed 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -39,7 +39,14 @@
#define PCC_MEM_SIZE (PCC_LEN + \
REG_DMA_HEADERS_BUFFER_SZ)
+#define HSIC_MEM_SIZE ((sizeof(struct drm_msm_pa_hsic)) + \
+ REG_DMA_HEADERS_BUFFER_SZ)
+
+#define SIXZONE_MEM_SIZE ((sizeof(struct drm_msm_sixzone)) + \
+ REG_DMA_HEADERS_BUFFER_SZ)
+
#define REG_MASK(n) ((BIT(n)) - 1)
+#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
static struct sde_reg_dma_buffer *dspp_buf[REG_DMA_FEATURES_MAX][DSPP_MAX];
@@ -49,9 +56,9 @@
[SDE_DSPP_IGC] = IGC,
[SDE_DSPP_PCC] = PCC,
[SDE_DSPP_GC] = GC,
- [SDE_DSPP_HSIC] = REG_DMA_FEATURES_MAX,
+ [SDE_DSPP_HSIC] = HSIC,
[SDE_DSPP_MEMCOLOR] = REG_DMA_FEATURES_MAX,
- [SDE_DSPP_SIXZONE] = REG_DMA_FEATURES_MAX,
+ [SDE_DSPP_SIXZONE] = SIX_ZONE,
[SDE_DSPP_DITHER] = REG_DMA_FEATURES_MAX,
[SDE_DSPP_HIST] = REG_DMA_FEATURES_MAX,
[SDE_DSPP_AD] = REG_DMA_FEATURES_MAX,
@@ -63,6 +70,8 @@
[SDE_DSPP_GC] = GC_LUT_MEM_SIZE,
[SDE_DSPP_IGC] = IGC_LUT_MEM_SIZE,
[SDE_DSPP_PCC] = PCC_MEM_SIZE,
+ [SDE_DSPP_HSIC] = HSIC_MEM_SIZE,
+ [SDE_DSPP_SIXZONE] = SIXZONE_MEM_SIZE,
};
static u32 dspp_mapping[DSPP_MAX] = {
@@ -295,8 +304,8 @@
if (!hw_cfg->payload) {
DRM_DEBUG_DRIVER("Disable vlut feature\n");
SDE_REG_WRITE(&ctx->hw, PA_LUTV_OPMODE_OFF, 0);
- if (op_mode & (~(BIT(20))))
- op_mode = 0;
+ if (PA_DISABLE_REQUIRED(op_mode))
+ op_mode &= ~PA_EN;
SDE_REG_WRITE(&ctx->hw, PA_OP_MODE_OFF, op_mode);
return;
}
@@ -919,6 +928,233 @@
kfree(data);
}
+void reg_dmav1_setup_dspp_pa_hsicv18(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_reg_dma_ops *dma_ops;
+ struct sde_reg_dma_kickoff_cfg kick_off;
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
+ struct drm_msm_pa_hsic *hsic_cfg;
+ u32 reg = 0, opcode = 0, local_opcode = 0;
+ int rc;
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ rc = reg_dma_dspp_check(ctx, cfg, HSIC);
+ if (rc)
+ return;
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable pa hsic feature\n");
+ opcode &= ~(PA_HUE_EN | PA_SAT_EN | PA_VAL_EN | PA_CONT_EN);
+ if (PA_DISABLE_REQUIRED(opcode))
+ opcode &= ~PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_pa_hsic)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_pa_hsic));
+ return;
+ }
+
+ hsic_cfg = hw_cfg->payload;
+
+ dma_ops = sde_reg_dma_get_ops();
+ dma_ops->reset_reg_dma_buf(dspp_buf[HSIC][ctx->idx]);
+
+ REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
+ HSIC, dspp_buf[HSIC][ctx->idx]);
+
+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write decode select failed ret %d\n", rc);
+ return;
+ }
+
+ if (hsic_cfg->flags & PA_HSIC_HUE_ENABLE) {
+ reg = hsic_cfg->hue & PA_HUE_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_HUE_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic hue write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_HUE_EN;
+ } else if (opcode & PA_HUE_EN)
+ opcode &= ~PA_HUE_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_SAT_ENABLE) {
+ reg = hsic_cfg->saturation & PA_SAT_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_SAT_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic saturation write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_SAT_EN;
+ } else if (opcode & PA_SAT_EN)
+ opcode &= ~PA_SAT_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_VAL_ENABLE) {
+ reg = hsic_cfg->value & PA_VAL_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_VAL_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic value write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_VAL_EN;
+ } else if (opcode & PA_VAL_EN)
+ opcode &= ~PA_VAL_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_CONT_ENABLE) {
+ reg = hsic_cfg->contrast & PA_CONT_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_CONT_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic contrast write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_CONT_EN;
+ } else if (opcode & PA_CONT_EN)
+ opcode &= ~PA_CONT_EN;
+
+ if (local_opcode)
+ opcode |= (local_opcode | PA_EN);
+ else {
+ DRM_ERROR("Invalid hsic config\n");
+ return;
+ }
+
+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[HSIC][ctx->idx],
+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
+ rc = dma_ops->kick_off(&kick_off);
+ if (rc)
+ DRM_ERROR("failed to kick off ret %d\n", rc);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void reg_dmav1_setup_dspp_sixzonev18(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_reg_dma_ops *dma_ops;
+ struct sde_reg_dma_kickoff_cfg kick_off;
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
+ struct drm_msm_sixzone *sixzone;
+ u32 reg = 0, hold = 0, local_hold = 0;
+ u32 opcode = 0, local_opcode = 0;
+ int rc;
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ rc = reg_dma_dspp_check(ctx, cfg, SIX_ZONE);
+ if (rc)
+ return;
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable sixzone feature\n");
+ opcode &= ~(PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN |
+ PA_SIXZONE_VAL_EN);
+ if (PA_DISABLE_REQUIRED(opcode))
+ opcode &= ~PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_sixzone));
+ return;
+ }
+
+ sixzone = hw_cfg->payload;
+
+ dma_ops = sde_reg_dma_get_ops();
+ dma_ops->reset_reg_dma_buf(dspp_buf[SIX_ZONE][ctx->idx]);
+
+ REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
+ SIX_ZONE, dspp_buf[SIX_ZONE][ctx->idx]);
+
+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write decode select failed ret %d\n", rc);
+ return;
+ }
+
+ reg = BIT(26);
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->sixzone.base,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("setting lut index failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ (ctx->cap->sblk->sixzone.base + SIXZONE_ADJ_CURVE_P1_OFF),
+ &sixzone->curve[0].p1, (SIXZONE_LUT_SIZE * sizeof(u32) * 2),
+ REG_BLK_WRITE_MULTIPLE, 2, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write sixzone lut failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->sixzone.base + SIXZONE_THRESHOLDS_OFF,
+ &sixzone->threshold, 3 * sizeof(u32),
+ REG_BLK_WRITE_SINGLE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write sixzone threshold failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
+ dspp_buf[SIX_ZONE][ctx->idx],
+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
+ rc = dma_ops->kick_off(&kick_off);
+ if (rc)
+ DRM_ERROR("failed to kick off ret %d\n", rc);
+
+ hold = SDE_REG_READ(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + PA_PWL_HOLD_OFF));
+ local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);
+ local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);
+ hold &= ~REG_MASK_SHIFT(4, 12);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + PA_PWL_HOLD_OFF), hold);
+
+ if (sixzone->flags & SIXZONE_HUE_ENABLE)
+ local_opcode |= PA_SIXZONE_HUE_EN;
+ if (sixzone->flags & SIXZONE_SAT_ENABLE)
+ local_opcode |= PA_SIXZONE_SAT_EN;
+ if (sixzone->flags & SIXZONE_VAL_ENABLE)
+ local_opcode |= PA_SIXZONE_VAL_EN;
+
+ if (local_opcode)
+ local_opcode |= PA_EN;
+
+ opcode &= ~REG_MASK_SHIFT(3, 29);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)
{
int i;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
index bb72c8f..a8115d6 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
@@ -67,6 +67,20 @@
void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg);
/**
+ * reg_dmav1_setup_dspp_pa_hsicv18() - pa hsic v18 impl using reg dma v1.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_dspp_pa_hsicv18(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * reg_dmav1_setup_dspp_sixzonev18() - sixzone v18 impl using reg dma v1.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_dspp_sixzonev18(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
* reg_dmav1_deinit_dspp_ops() - deinitialize the dspp feature op for sde v4
* which were initialized.
* @idx: dspp idx
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index e865f20..4357518 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -1481,6 +1481,7 @@
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+ unsigned int val;
if (!kgsl_gmu_isenabled(device))
return;
@@ -1488,10 +1489,16 @@
adreno_snapshot_registers(device, snapshot, a6xx_gmu_registers,
ARRAY_SIZE(a6xx_gmu_registers) / 2);
- if (gpudev->gx_is_on(adreno_dev))
+ if (gpudev->gx_is_on(adreno_dev)) {
+ /* Set fence to ALLOW mode so registers can be read */
+ kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
+ kgsl_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &val);
+
+ KGSL_DRV_ERR(device, "set FENCE to ALLOW mode:%x\n", val);
adreno_snapshot_registers(device, snapshot,
a6xx_gmu_gx_registers,
ARRAY_SIZE(a6xx_gmu_gx_registers) / 2);
+ }
}
/* a6xx_snapshot_sqe() - Dump SQE data in snapshot */
@@ -1579,9 +1586,6 @@
bool sptprac_on;
unsigned int i;
- /* Make sure the fence is in ALLOW mode so registers can be read */
- kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
-
/* GMU TCM data dumped through AHB */
a6xx_snapshot_gmu(adreno_dev, snapshot);
diff --git a/drivers/gpu/msm/kgsl_gmu.c b/drivers/gpu/msm/kgsl_gmu.c
index 98b5ea7..9446f70 100644
--- a/drivers/gpu/msm/kgsl_gmu.c
+++ b/drivers/gpu/msm/kgsl_gmu.c
@@ -807,6 +807,15 @@
if (status & GMU_INT_HOST_AHB_BUS_ERR)
dev_err_ratelimited(&gmu->pdev->dev,
"AHB bus error interrupt received\n");
+ if (status & GMU_INT_FENCE_ERR) {
+ unsigned int fence_status;
+
+ adreno_read_gmureg(ADRENO_DEVICE(device),
+ ADRENO_REG_GMU_AHB_FENCE_STATUS, &fence_status);
+ dev_err_ratelimited(&gmu->pdev->dev,
+ "FENCE error interrupt received %x\n", fence_status);
+ }
+
if (status & ~GMU_AO_INT_MASK)
dev_err_ratelimited(&gmu->pdev->dev,
"Unhandled GMU interrupts 0x%lx\n",
diff --git a/drivers/gpu/msm/kgsl_gmu.h b/drivers/gpu/msm/kgsl_gmu.h
index adabbc2..e0c857f 100644
--- a/drivers/gpu/msm/kgsl_gmu.h
+++ b/drivers/gpu/msm/kgsl_gmu.h
@@ -22,11 +22,13 @@
#define GMU_INT_WDOG_BITE BIT(0)
#define GMU_INT_RSCC_COMP BIT(1)
+#define GMU_INT_FENCE_ERR BIT(3)
#define GMU_INT_DBD_WAKEUP BIT(4)
#define GMU_INT_HOST_AHB_BUS_ERR BIT(5)
#define GMU_AO_INT_MASK \
(GMU_INT_WDOG_BITE | \
- GMU_INT_HOST_AHB_BUS_ERR)
+ GMU_INT_HOST_AHB_BUS_ERR | \
+ GMU_INT_FENCE_ERR)
#define MAX_GMUFW_SIZE 0x2000 /* in dwords */
#define FENCE_RANGE_MASK ((0x1 << 31) | (0x0A << 18) | (0x8A0))
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index db948a9..a8ab720 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -2485,6 +2485,9 @@
static void kgsl_pwrctrl_disable(struct kgsl_device *device)
{
if (kgsl_gmu_isenabled(device)) {
+ struct kgsl_pwrctrl *pwr = &device->pwrctrl;
+
+ pwr->active_pwrlevel = pwr->num_pwrlevels - 1;
kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_OFF);
return gmu_stop(device);
}
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 2460ba7..793cbb5 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -881,9 +881,17 @@
return ret;
if (gi2c->se_mode == UNINITIALIZED) {
- u32 se_mode = readl_relaxed(gi2c->base +
- GENI_IF_FIFO_DISABLE_RO);
+ int proto = get_se_proto(gi2c->base);
+ u32 se_mode;
+ if (unlikely(proto != I2C)) {
+ dev_err(gi2c->dev, "Invalid proto %d\n", proto);
+ se_geni_resources_off(&gi2c->i2c_rsc);
+ return -ENXIO;
+ }
+
+ se_mode = readl_relaxed(gi2c->base +
+ GENI_IF_FIFO_DISABLE_RO);
if (se_mode) {
gi2c->se_mode = GSI_ONLY;
geni_se_select_mode(gi2c->base, GSI_DMA);
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a0e1f59..58d5030 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -101,6 +101,9 @@
#define sCR0_VMID16EN (1 << 31)
#define sCR0_BSU_SHIFT 14
#define sCR0_BSU_MASK 0x3
+#define sCR0_SHCFG_SHIFT 22
+#define sCR0_SHCFG_MASK 0x3
+#define sCR0_SHCFG_NSH 3
/* Auxiliary Configuration register */
#define ARM_SMMU_GR0_sACR 0x10
@@ -177,6 +180,9 @@
#define S2CR_CBNDX_MASK 0xff
#define S2CR_TYPE_SHIFT 16
#define S2CR_TYPE_MASK 0x3
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK 0x3
+#define S2CR_SHCFG_NSH 0x3
enum arm_smmu_s2cr_type {
S2CR_TYPE_TRANS,
S2CR_TYPE_BYPASS,
@@ -251,6 +257,9 @@
#define ARM_SMMU_CB_ATS1PR 0x800
#define ARM_SMMU_CB_ATSR 0x8f0
+#define SCTLR_SHCFG_SHIFT 22
+#define SCTLR_SHCFG_MASK 0x3
+#define SCTLR_SHCFG_NSH 0x3
#define SCTLR_S1_ASIDPNE (1 << 12)
#define SCTLR_CFCFG (1 << 7)
#define SCTLR_HUPCF (1 << 8)
@@ -1526,6 +1535,9 @@
/* SCTLR */
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE;
+ /* Ensure bypass transactions are Non-shareable */
+ reg |= SCTLR_SHCFG_NSH << SCTLR_SHCFG_SHIFT;
+
if (smmu_domain->attributes & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)) {
reg &= ~SCTLR_CFCFG;
reg |= SCTLR_HUPCF;
@@ -1929,7 +1941,8 @@
struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
u32 reg = (s2cr->type & S2CR_TYPE_MASK) << S2CR_TYPE_SHIFT |
(s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
- (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT;
+ (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT |
+ S2CR_SHCFG_NSH << S2CR_SHCFG_SHIFT;
writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
}
@@ -2392,10 +2405,6 @@
if (!ops)
return -ENODEV;
- ret = arm_smmu_domain_power_on(domain, smmu_domain->smmu);
- if (ret)
- return ret;
-
arm_smmu_secure_domain_lock(smmu_domain);
__saved_iova_start = iova;
@@ -2436,7 +2445,6 @@
iova = __saved_iova_start;
}
arm_smmu_secure_domain_unlock(smmu_domain);
- arm_smmu_domain_power_off(domain, smmu_domain->smmu);
return iova - __saved_iova_start;
}
@@ -3430,6 +3438,10 @@
if (smmu->features & ARM_SMMU_FEAT_VMID16)
reg |= sCR0_VMID16EN;
+ /* Force bypass transaction to be Non-Shareable & not io-coherent */
+ reg &= ~(sCR0_SHCFG_MASK << sCR0_SHCFG_SHIFT);
+ reg |= sCR0_SHCFG_NSH;
+
/* Push the button */
__arm_smmu_tlb_sync(smmu);
writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
diff --git a/drivers/irqchip/qcom/pdc-sdm845.c b/drivers/irqchip/qcom/pdc-sdm845.c
index 178cf1f0..9fb8897 100644
--- a/drivers/irqchip/qcom/pdc-sdm845.c
+++ b/drivers/irqchip/qcom/pdc-sdm845.c
@@ -123,10 +123,10 @@
{119, 666}, /* core_bi_px_to_mpm[2] */
{120, 667}, /* core_bi_px_to_mpm[3] */
{121, 668}, /* core_bi_px_to_mpm[4] */
- {122, 669}, /* core_bi_px_gpio_41 */
- {123, 670}, /* core_bi_px_gpio_89 */
- {124, 671}, /* core_bi_px_gpio_31 */
- {125, 672}, /* core_bi_px_gpio_49 */
+ {122, 662}, /* core_bi_px_gpio_41 */
+ {123, 663}, /* core_bi_px_gpio_89 */
+ {124, 664}, /* core_bi_px_gpio_31 */
+ {125, 665}, /* core_bi_px_gpio_49 */
{-1}
};
diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c
index 5c9c75c..7068212 100644
--- a/drivers/leds/leds-qpnp-wled.c
+++ b/drivers/leds/leds-qpnp-wled.c
@@ -2442,7 +2442,7 @@
wled->pmic_rev_id->pmic_subtype, wled->pmic_rev_id->rev4);
prop = of_get_address_by_name(pdev->dev.of_node, QPNP_WLED_SINK_BASE,
- 0, 0);
+ NULL, NULL);
if (!prop) {
dev_err(&pdev->dev, "Couldnt find sink's addr rc %d\n", rc);
return rc;
@@ -2450,7 +2450,7 @@
wled->sink_base = be32_to_cpu(*prop);
prop = of_get_address_by_name(pdev->dev.of_node, QPNP_WLED_CTRL_BASE,
- 0, 0);
+ NULL, NULL);
if (!prop) {
dev_err(&pdev->dev, "Couldnt find ctrl's addr rc = %d\n", rc);
return rc;
diff --git a/drivers/md/dm-req-crypt.c b/drivers/md/dm-req-crypt.c
index 3ffe7e5..b4bdbc0 100644
--- a/drivers/md/dm-req-crypt.c
+++ b/drivers/md/dm-req-crypt.c
@@ -217,6 +217,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
} else {
DMERR("%s io is NULL\n", __func__);
@@ -225,6 +226,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
atomic_dec(&io->pending);
@@ -253,6 +255,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
} else {
DMERR("%s io is NULL\n",
@@ -262,6 +265,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
/* Should never get here if io or Clone is NULL */
@@ -445,6 +449,7 @@
if (!io || !io->cloned_request) {
DMERR("%s io is invalid\n", __func__);
WARN_ON(1); /* should not happen */
+ return;
}
clone = io->cloned_request;
@@ -696,6 +701,7 @@
if (!io || !io->cloned_request) {
DMERR("%s io is invalid\n", __func__);
WARN_ON(1); /* should not happen */
+ return;
}
clone = io->cloned_request;
@@ -740,6 +746,7 @@
err = DM_REQ_CRYPT_ERROR;
/* If io is not populated this should not be called */
WARN_ON(1);
+ return;
}
req = skcipher_request_alloc(tfm, GFP_KERNEL);
if (!req) {
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
index e3d46df..4b0cc74 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
@@ -372,6 +372,8 @@
&camnoc_info->specific[i].safe_lut);
cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
&camnoc_info->specific[i].ubwc_ctl);
+ cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
+ &camnoc_info->specific[i].flag_out_set0_low);
}
}
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
index d5bb363..e3639a6 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
@@ -110,6 +110,7 @@
struct cam_cpas_reg danger_lut;
struct cam_cpas_reg safe_lut;
struct cam_cpas_reg ubwc_ctl;
+ struct cam_cpas_reg flag_out_set0_low;
};
/**
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
index 918258d..55cb07b 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
@@ -494,8 +494,15 @@
},
{
.port_type = CAM_CAMNOC_ICP,
- .enable = false,
- }
+ .enable = true,
+ .flag_out_set0_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_WRITE,
+ .masked_value = 0,
+ .offset = 0x2088,
+ .value = 0x100000,
+ },
+ },
};
static uint32_t cam_cpas110_slave_error_logger[] = {
diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
index b8a5685..d9be53d 100644
--- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
+++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
@@ -112,6 +112,9 @@
/* Before triggering reset to HW, clear the reset complete */
reinit_completion(&fd_core->reset_complete);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_CORE,
+ hw_static_info->core_regs.control, 0x1);
+
if (hw_static_info->enable_errata_wa.single_irq_only) {
cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
hw_static_info->wrapper_regs.irq_mask,
@@ -126,9 +129,6 @@
if (time_left <= 0)
CAM_WARN(CAM_FD, "HW reset timeout time_left=%d", time_left);
- cam_fd_soc_register_write(soc_info, CAM_FD_REG_CORE,
- hw_static_info->core_regs.control, 0x1);
-
CAM_DBG(CAM_FD, "FD Wrapper SW Sync Reset complete");
return 0;
@@ -424,9 +424,10 @@
struct cam_fd_hw_req_private *req_private;
uint32_t base, face_cnt;
uint32_t *buffer;
+ unsigned long flags;
int i;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if ((fd_core->core_state != CAM_FD_CORE_STATE_IDLE) ||
(fd_core->results_valid == false) ||
!fd_core->hw_req_private) {
@@ -434,12 +435,12 @@
"Invalid state for results state=%d, results=%d %pK",
fd_core->core_state, fd_core->results_valid,
fd_core->hw_req_private);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->core_state = CAM_FD_CORE_STATE_READING_RESULTS;
req_private = fd_core->hw_req_private;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
/*
* Copy the register value as is into output buffers.
@@ -511,10 +512,10 @@
}
}
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->hw_req_private = NULL;
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return 0;
}
@@ -776,6 +777,9 @@
{
struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv;
struct cam_fd_core *fd_core;
+ struct cam_fd_hw_static_info *hw_static_info;
+ struct cam_hw_soc_info *soc_info;
+ unsigned long flags;
int rc;
if (!fd_hw) {
@@ -784,18 +788,23 @@
}
fd_core = (struct cam_fd_core *)fd_hw->core_info;
+ hw_static_info = fd_core->hw_static_info;
+ soc_info = &fd_hw->soc_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if (fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS) {
CAM_ERR(CAM_FD, "Reset not allowed in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->results_valid = false;
fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
+
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x1);
rc = cam_fd_hw_util_fdwrapper_halt(fd_hw);
if (rc) {
@@ -809,9 +818,12 @@
return rc;
}
- spin_lock(&fd_core->spin_lock);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x0);
+
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
@@ -824,6 +836,7 @@
struct cam_fd_hw_cmd_start_args *start_args =
(struct cam_fd_hw_cmd_start_args *)hw_start_args;
struct cam_fd_ctx_hw_private *ctx_hw_private;
+ unsigned long flags;
int rc;
if (!hw_priv || !start_args) {
@@ -841,11 +854,11 @@
fd_core = (struct cam_fd_core *)fd_hw->core_info;
hw_static_info = fd_core->hw_static_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if (fd_core->core_state != CAM_FD_CORE_STATE_IDLE) {
CAM_ERR(CAM_FD, "Cannot start in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
@@ -858,7 +871,7 @@
fd_core->hw_req_private = start_args->hw_req_private;
fd_core->core_state = CAM_FD_CORE_STATE_PROCESSING;
fd_core->results_valid = false;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
ctx_hw_private = start_args->ctx_hw_private;
@@ -903,9 +916,9 @@
return 0;
error:
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
@@ -914,6 +927,9 @@
{
struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv;
struct cam_fd_core *fd_core;
+ struct cam_fd_hw_static_info *hw_static_info;
+ struct cam_hw_soc_info *soc_info;
+ unsigned long flags;
int rc;
if (!fd_hw) {
@@ -922,19 +938,24 @@
}
fd_core = (struct cam_fd_core *)fd_hw->core_info;
+ hw_static_info = fd_core->hw_static_info;
+ soc_info = &fd_hw->soc_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if ((fd_core->core_state == CAM_FD_CORE_STATE_POWERDOWN) ||
(fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS)) {
CAM_ERR(CAM_FD, "Reset not allowed in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->results_valid = false;
fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
+
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x1);
rc = cam_fd_hw_util_fdwrapper_halt(fd_hw);
if (rc) {
@@ -949,9 +970,12 @@
return rc;
}
- spin_lock(&fd_core->spin_lock);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x0);
+
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
index bdd72af..3d9c5f0 100644
--- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
+++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
@@ -30,7 +30,7 @@
#define CAM_FD_IRQ_TO_MASK(irq) (1 << (irq))
#define CAM_FD_MASK_TO_IRQ(mask, irq) ((mask) >> (irq))
-#define CAM_FD_HW_HALT_RESET_TIMEOUT 100
+#define CAM_FD_HW_HALT_RESET_TIMEOUT 750
/**
* enum cam_fd_core_state - FD Core internal states
diff --git a/drivers/media/platform/msm/camera/cam_icp/hfi.c b/drivers/media/platform/msm/camera/cam_icp/hfi.c
index a315268..cdb0cfa 100644
--- a/drivers/media/platform/msm/camera/cam_icp/hfi.c
+++ b/drivers/media/platform/msm/camera/cam_icp/hfi.c
@@ -385,10 +385,15 @@
ICP_FLAG_CSR_WAKE_UP_EN | ICP_CSR_EN_CLKGATE_WFI),
icp_base + HFI_REG_A5_CSR_A5_CONTROL);
} else {
+ /* Due to hardware bug in V1 ICP clock gating has to be
+ * disabled, this is supposed to be fixed in V-2. But enabling
+ * the clock gating is causing the firmware hang, hence
+ * disabling the clock gating on both V1 and V2 until the
+ * hardware team root causes this
+ */
cam_io_w((uint32_t)ICP_FLAG_CSR_A5_EN |
ICP_FLAG_CSR_WAKE_UP_EN |
- ((soc_version == SOC_VERSION_HW1) ?
- (ICP_CSR_EN_CLKGATE_WFI) : (0x0)),
+ ICP_CSR_EN_CLKGATE_WFI,
icp_base + HFI_REG_A5_CSR_A5_CONTROL);
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
index 6060278..8489780 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
@@ -778,10 +778,11 @@
uint32_t cid_res_id)
{
int rc = -1;
- int i, j;
+ int i;
struct cam_ife_hw_mgr *ife_hw_mgr;
struct cam_ife_hw_mgr_res *csid_res;
+ struct cam_ife_hw_mgr_res *cid_res;
struct cam_hw_intf *hw_intf;
struct cam_csid_hw_reserve_resource_args csid_acquire;
@@ -800,69 +801,64 @@
csid_acquire.in_port = in_port;
csid_acquire.out_port = in_port->data;
- if (in_port->usage_type)
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER;
- else
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE;
-
-
-
- for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {
- if (!ife_hw_mgr->csid_devices[i])
- continue;
-
- hw_intf = ife_hw_mgr->csid_devices[i];
- rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &csid_acquire,
- sizeof(csid_acquire));
- if (rc)
- continue;
- else
- break;
- }
-
- if (i == CAM_IFE_CSID_HW_NUM_MAX) {
- CAM_ERR(CAM_ISP, "Can not acquire ife csid ipp resource");
- goto err;
- }
-
- CAM_DBG(CAM_ISP, "acquired csid(%d) left ipp resource successfully",
- i);
-
csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
csid_res->res_id = CAM_IFE_PIX_PATH_RES_IPP;
csid_res->is_dual_vfe = in_port->usage_type;
- csid_res->hw_res[0] = csid_acquire.node_res;
- csid_res->hw_res[1] = NULL;
- if (csid_res->is_dual_vfe) {
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE;
- csid_acquire.master_idx = csid_res->hw_res[0]->hw_intf->hw_idx;
+ if (in_port->usage_type)
+ csid_res->is_dual_vfe = 1;
+ else {
+ csid_res->is_dual_vfe = 0;
+ csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER;
+ }
- for (j = i + 1; j < CAM_IFE_CSID_HW_NUM_MAX; j++) {
- if (!ife_hw_mgr->csid_devices[j])
+ list_for_each_entry(cid_res, &ife_ctx->res_list_ife_cid,
+ list) {
+ if (cid_res->res_id != cid_res_id)
+ continue;
+
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!cid_res->hw_res[i])
continue;
- hw_intf = ife_hw_mgr->csid_devices[j];
+ csid_acquire.node_res = NULL;
+ if (csid_res->is_dual_vfe) {
+ if (i == CAM_ISP_HW_SPLIT_LEFT)
+ csid_acquire.sync_mode =
+ CAM_ISP_HW_SYNC_MASTER;
+ else
+ csid_acquire.sync_mode =
+ CAM_ISP_HW_SYNC_SLAVE;
+ }
+
+ hw_intf = ife_hw_mgr->csid_devices[
+ cid_res->hw_res[i]->hw_intf->hw_idx];
rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
&csid_acquire, sizeof(csid_acquire));
- if (rc)
- continue;
- else
- break;
+ if (rc) {
+ CAM_ERR(CAM_ISP,
+ "Cannot acquire ife csid ipp resource");
+ goto err;
+ }
+
+ csid_res->hw_res[i] = csid_acquire.node_res;
+ CAM_DBG(CAM_ISP,
+ "acquired csid(%s)=%d ipp rsrc successfully",
+ (i == 0) ? "left" : "right",
+ hw_intf->hw_idx);
+
}
- if (j == CAM_IFE_CSID_HW_NUM_MAX) {
+ if (i == CAM_IFE_CSID_HW_NUM_MAX) {
CAM_ERR(CAM_ISP,
- "Can not acquire ife csid rdi resrouce");
+ "Can not acquire ife csid ipp resource");
goto err;
}
- csid_res->hw_res[1] = csid_acquire.node_res;
- CAM_DBG(CAM_ISP,
- "acquired csid(%d)right ipp resrouce successfully", j);
-
+ csid_res->parent = cid_res;
+ cid_res->child[cid_res->num_children++] = csid_res;
}
- csid_res->parent = &ife_ctx->res_list_ife_in;
+
CAM_DBG(CAM_ISP, "acquire res %d", csid_acquire.res_id);
return 0;
@@ -909,7 +905,8 @@
struct cam_ife_hw_mgr *ife_hw_mgr;
struct cam_ife_hw_mgr_res *csid_res;
- struct cam_hw_intf *hw_intf;
+ struct cam_ife_hw_mgr_res *cid_res;
+ struct cam_hw_intf *hw_intf;
struct cam_isp_out_port_info *out_port;
struct cam_csid_hw_reserve_resource_args csid_acquire;
@@ -934,6 +931,7 @@
* between the csid rdi type and out port rdi type
*/
+ memset(&csid_acquire, 0, sizeof(csid_acquire));
csid_acquire.res_id =
cam_ife_hw_mgr_get_ife_csid_rdi_res_type(
out_port->res_type);
@@ -944,37 +942,58 @@
csid_acquire.out_port = out_port;
csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE;
- for (j = 0; j < CAM_IFE_CSID_HW_NUM_MAX; j++) {
- if (!ife_hw_mgr->csid_devices[j])
+ list_for_each_entry(cid_res, &ife_ctx->res_list_ife_cid,
+ list) {
+ if (cid_res->res_id != cid_res_id)
continue;
- hw_intf = ife_hw_mgr->csid_devices[j];
- rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
- &csid_acquire, sizeof(csid_acquire));
- if (rc)
- continue;
- else
+ for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) {
+ if (!cid_res->hw_res[j])
+ continue;
+
+ csid_acquire.node_res = NULL;
+
+ hw_intf = ife_hw_mgr->csid_devices[
+ cid_res->hw_res[j]->hw_intf->hw_idx];
+ rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
+ &csid_acquire, sizeof(csid_acquire));
+ if (rc) {
+ CAM_DBG(CAM_ISP,
+ "CSID Path reserve failed hw=%d rc=%d",
+ hw_intf->hw_idx, rc);
+ continue;
+ }
+
+ /* RDI does not need Dual ISP. Break */
break;
- }
+ }
- if (j == CAM_IFE_CSID_HW_NUM_MAX) {
- CAM_ERR(CAM_ISP,
- "Can not acquire ife csid rdi resource");
- goto err;
- }
+ if (j == CAM_ISP_HW_SPLIT_MAX &&
+ csid_acquire.node_res == NULL) {
+ CAM_ERR(CAM_ISP,
+ "acquire csid rdi rsrc failed, cid %d",
+ cid_res_id);
+ goto err;
+ }
- csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
- csid_res->res_id = csid_acquire.res_id;
- csid_res->is_dual_vfe = 0;
- csid_res->hw_res[0] = csid_acquire.node_res;
- csid_res->hw_res[1] = NULL;
- CAM_DBG(CAM_ISP, "acquire res %d", csid_acquire.res_id);
- csid_res->parent = &ife_ctx->res_list_ife_in;
+ csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
+ csid_res->res_id = csid_acquire.res_id;
+ csid_res->is_dual_vfe = 0;
+ csid_res->hw_res[0] = csid_acquire.node_res;
+ csid_res->hw_res[1] = NULL;
+ CAM_DBG(CAM_ISP, "acquire res %d",
+ csid_acquire.res_id);
+ csid_res->parent = cid_res;
+ cid_res->child[cid_res->num_children++] =
+ csid_res;
+
+ /* Done with cid_res_id. Break */
+ break;
+ }
}
return 0;
err:
- /* resource resources at entry funciton */
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
index dcbea8d..c6d5601 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
@@ -613,7 +613,6 @@
i, j, need_th_processing[j]);
}
}
- read_unlock(&controller->rw_lock);
CAM_DBG(CAM_ISP, "unlocked controller %pK name %s rw_lock %pK",
controller, controller->name, &controller->rw_lock);
@@ -632,6 +631,7 @@
&controller->th_list_head[i]);
}
}
+ read_unlock(&controller->rw_lock);
return IRQ_HANDLED;
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
index 7d6e758..c5dd6ff 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
@@ -627,6 +627,12 @@
goto end;
}
+ if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 &&
+ csid_hw->hw_intf->hw_idx != 2) {
+ rc = -EINVAL;
+ goto end;
+ }
+
if (csid_hw->csi2_reserve_cnt) {
/* current configure res type should match requested res type */
if (csid_hw->res_type != cid_reserv->in_port->res_type) {
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
index 77b830c..e4381d6 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
@@ -507,8 +507,6 @@
core_info->vfe_top->top_priv, isp_res,
sizeof(struct cam_isp_resource_node));
} else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) {
- cam_irq_controller_unsubscribe_irq(
- core_info->vfe_irq_controller, isp_res->irq_handle);
rc = core_info->vfe_bus->hw_ops.stop(isp_res, NULL, 0);
} else {
CAM_ERR(CAM_ISP, "Invalid res type:%d", isp_res->res_type);
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
index 77e4eb3..39a5603 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
@@ -11,4 +11,4 @@
ccflags-y += -Idrivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus
ccflags-y += -Idrivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw
-obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe170.o
+obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe170.o cam_vfe_lite170.o
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
index e3a6f7b..5773bbe 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
@@ -222,11 +222,12 @@
.comp_error_status = 0x0000206C,
.comp_ovrwr_status = 0x00002070,
.dual_comp_error_status = 0x00002074,
- .dual_comp_error_status = 0x00002078,
+ .dual_comp_ovrwr_status = 0x00002078,
.addr_sync_cfg = 0x0000207C,
.addr_sync_frame_hdr = 0x00002080,
.addr_sync_no_sync = 0x00002084,
},
+ .num_client = 20,
.bus_client_reg = {
/* BUS Client 0 */
{
@@ -707,8 +708,24 @@
.addr_sync_mask = 0x0000209C,
},
},
+ .num_out = 18,
.vfe_out_hw_info = {
{
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL,
.max_width = 4096,
.max_height = 4096,
@@ -739,21 +756,6 @@
.max_height = -1,
},
{
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
- .max_width = -1,
- .max_height = -1,
- },
- {
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
- .max_width = -1,
- .max_height = -1,
- },
- {
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
- .max_width = -1,
- .max_height = -1,
- },
- {
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,
.max_width = -1,
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c
new file mode 100644
index 0000000..3c8abbf
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c
@@ -0,0 +1,51 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include "cam_vfe_lite170.h"
+#include "cam_vfe_hw_intf.h"
+#include "cam_vfe_core.h"
+#include "cam_vfe_dev.h"
+
+static const struct of_device_id cam_vfe170_dt_match[] = {
+ {
+ .compatible = "qcom,vfe-lite170",
+ .data = &cam_vfe_lite170_hw_info,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cam_vfe170_dt_match);
+
+static struct platform_driver cam_vfe170_driver = {
+ .probe = cam_vfe_probe,
+ .remove = cam_vfe_remove,
+ .driver = {
+ .name = "cam_vfe_lite170",
+ .owner = THIS_MODULE,
+ .of_match_table = cam_vfe170_dt_match,
+ },
+};
+
+static int __init cam_vfe170_init_module(void)
+{
+ return platform_driver_register(&cam_vfe170_driver);
+}
+
+static void __exit cam_vfe170_exit_module(void)
+{
+ platform_driver_unregister(&cam_vfe170_driver);
+}
+
+module_init(cam_vfe170_init_module);
+module_exit(cam_vfe170_exit_module);
+MODULE_DESCRIPTION("CAM VFE170 driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h
new file mode 100644
index 0000000..2f95feb
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h
@@ -0,0 +1,336 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_VFE_LITE170_H_
+#define _CAM_VFE_LITE170_H_
+
+#include "cam_vfe_bus_ver2.h"
+#include "cam_irq_controller.h"
+#include "cam_vfe_top_ver2.h"
+#include "cam_vfe_core.h"
+
+static struct cam_irq_register_set vfe170_top_irq_reg_set[2] = {
+ {
+ .mask_reg_offset = 0x0000005C,
+ .clear_reg_offset = 0x00000064,
+ .status_reg_offset = 0x0000006C,
+ },
+ {
+ .mask_reg_offset = 0x00000060,
+ .clear_reg_offset = 0x00000068,
+ .status_reg_offset = 0x00000070,
+ },
+};
+
+static struct cam_irq_controller_reg_info vfe170_top_irq_reg_info = {
+ .num_registers = 2,
+ .irq_reg_set = vfe170_top_irq_reg_set,
+ .global_clear_offset = 0x00000058,
+ .global_clear_bitmask = 0x00000001,
+};
+
+static struct cam_vfe_top_ver2_reg_offset_common vfe170_top_common_reg = {
+ .hw_version = 0x00000000,
+ .hw_capability = 0x00000004,
+ .lens_feature = 0x00000008,
+ .stats_feature = 0x0000000C,
+ .color_feature = 0x00000010,
+ .zoom_feature = 0x00000014,
+ .global_reset_cmd = 0x00000018,
+ .module_ctrl = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ },
+ .bus_cgc_ovd = 0x0000003C,
+ .core_cfg = 0x00000000,
+ .three_D_cfg = 0x00000000,
+ .violation_status = 0x0000007C,
+ .reg_update_cmd = 0x000004AC,
+};
+
+static struct cam_vfe_rdi_ver2_reg vfe170_rdi_reg = {
+ .reg_update_cmd = 0x000004AC,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_0_data = {
+ .reg_update_cmd_data = 0x2,
+ .sof_irq_mask = 0x8000000,
+ .reg_update_irq_mask = 0x20,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_1_data = {
+ .reg_update_cmd_data = 0x4,
+ .sof_irq_mask = 0x10000000,
+ .reg_update_irq_mask = 0x40,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_2_data = {
+ .reg_update_cmd_data = 0x8,
+ .sof_irq_mask = 0x20000000,
+ .reg_update_irq_mask = 0x80,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_3_data = {
+ .reg_update_cmd_data = 0x10,
+ .sof_irq_mask = 0x40000000,
+ .reg_update_irq_mask = 0x100,
+};
+
+static struct cam_vfe_top_ver2_hw_info vfe170_top_hw_info = {
+ .common_reg = &vfe170_top_common_reg,
+ .camif_hw_info = {
+ .common_reg = NULL,
+ .camif_reg = NULL,
+ .reg_data = NULL,
+ },
+ .rdi_hw_info = {
+ .common_reg = &vfe170_top_common_reg,
+ .rdi_reg = &vfe170_rdi_reg,
+ .reg_data = {
+ &vfe170_rdi_0_data,
+ &vfe170_rdi_1_data,
+ &vfe170_rdi_2_data,
+ &vfe170_rdi_3_data,
+ },
+ },
+ .mux_type = {
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ },
+};
+
+static struct cam_irq_register_set vfe170_bus_irq_reg[3] = {
+ {
+ .mask_reg_offset = 0x00002044,
+ .clear_reg_offset = 0x00002050,
+ .status_reg_offset = 0x0000205C,
+ },
+ {
+ .mask_reg_offset = 0x00002048,
+ .clear_reg_offset = 0x00002054,
+ .status_reg_offset = 0x00002060,
+ },
+ {
+ .mask_reg_offset = 0x0000204C,
+ .clear_reg_offset = 0x00002058,
+ .status_reg_offset = 0x00002064,
+ },
+};
+
+static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = {
+ .common_reg = {
+ .hw_version = 0x00002000,
+ .hw_capability = 0x00002004,
+ .sw_reset = 0x00002008,
+ .cgc_ovd = 0x0000200C,
+ .pwr_iso_cfg = 0x000020CC,
+ .dual_master_comp_cfg = 0x00002028,
+ .irq_reg_info = {
+ .num_registers = 3,
+ .irq_reg_set = vfe170_bus_irq_reg,
+ .global_clear_offset = 0x00002068,
+ .global_clear_bitmask = 0x00000001,
+ },
+ .comp_error_status = 0x0000206C,
+ .comp_ovrwr_status = 0x00002070,
+ .dual_comp_error_status = 0x00002074,
+ .dual_comp_ovrwr_status = 0x00002078,
+ .addr_sync_cfg = 0x0000207C,
+ .addr_sync_frame_hdr = 0x00002080,
+ .addr_sync_no_sync = 0x00002084,
+ },
+ .num_client = 4,
+ .bus_client_reg = {
+ /* BUS Client 0 */
+ {
+ .status0 = 0x00002200,
+ .status1 = 0x00002204,
+ .cfg = 0x00002208,
+ .header_addr = 0x0000220C,
+ .header_cfg = 0x00002210,
+ .image_addr = 0x00002214,
+ .image_addr_offset = 0x00002218,
+ .buffer_width_cfg = 0x0000221C,
+ .buffer_height_cfg = 0x00002220,
+ .packer_cfg = 0x00002224,
+ .stride = 0x00002228,
+ .irq_subsample_period = 0x00002248,
+ .irq_subsample_pattern = 0x0000224C,
+ .framedrop_period = 0x00002250,
+ .framedrop_pattern = 0x00002254,
+ .frame_inc = 0x00002258,
+ .burst_limit = 0x0000225C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 1 */
+ {
+ .status0 = 0x00002300,
+ .status1 = 0x00002304,
+ .cfg = 0x00002308,
+ .header_addr = 0x0000230C,
+ .header_cfg = 0x00002310,
+ .image_addr = 0x00002314,
+ .image_addr_offset = 0x00002318,
+ .buffer_width_cfg = 0x0000231C,
+ .buffer_height_cfg = 0x00002320,
+ .packer_cfg = 0x00002324,
+ .stride = 0x00002328,
+ .irq_subsample_period = 0x00002348,
+ .irq_subsample_pattern = 0x0000234C,
+ .framedrop_period = 0x00002350,
+ .framedrop_pattern = 0x00002354,
+ .frame_inc = 0x00002358,
+ .burst_limit = 0x0000235C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 2 */
+ {
+ .status0 = 0x00002400,
+ .status1 = 0x00002404,
+ .cfg = 0x00002408,
+ .header_addr = 0x0000240C,
+ .header_cfg = 0x00002410,
+ .image_addr = 0x00002414,
+ .image_addr_offset = 0x00002418,
+ .buffer_width_cfg = 0x0000241C,
+ .buffer_height_cfg = 0x00002420,
+ .packer_cfg = 0x00002424,
+ .stride = 0x00002428,
+ .irq_subsample_period = 0x00002448,
+ .irq_subsample_pattern = 0x0000244C,
+ .framedrop_period = 0x00002450,
+ .framedrop_pattern = 0x00002454,
+ .frame_inc = 0x00002458,
+ .burst_limit = 0x0000245C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 3 */
+ {
+ .status0 = 0x00002500,
+ .status1 = 0x00002504,
+ .cfg = 0x00002508,
+ .header_addr = 0x0000250C,
+ .header_cfg = 0x00002510,
+ .image_addr = 0x00002514,
+ .image_addr_offset = 0x00002518,
+ .buffer_width_cfg = 0x0000251C,
+ .buffer_height_cfg = 0x00002520,
+ .packer_cfg = 0x00002524,
+ .stride = 0x00002528,
+ .irq_subsample_period = 0x00002548,
+ .irq_subsample_pattern = 0x0000254C,
+ .framedrop_period = 0x00002550,
+ .framedrop_pattern = 0x00002554,
+ .frame_inc = 0x00002558,
+ .burst_limit = 0x0000255C,
+ .ubwc_regs = NULL,
+ },
+ },
+ .comp_grp_reg = {
+ /* CAM_VFE_BUS_VER2_COMP_GRP_0 */
+ {
+ .comp_mask = 0x00002010,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_1 */
+ {
+ .comp_mask = 0x00002014,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_2 */
+ {
+ .comp_mask = 0x00002018,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_3 */
+ {
+ .comp_mask = 0x0000201C,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_4 */
+ {
+ .comp_mask = 0x00002020,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_5 */
+ {
+ .comp_mask = 0x00002024,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */
+ {
+ .comp_mask = 0x0000202C,
+ .addr_sync_mask = 0x00002088,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */
+ {
+ .comp_mask = 0x00002030,
+ .addr_sync_mask = 0x0000208C,
+
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */
+ {
+ .comp_mask = 0x00002034,
+ .addr_sync_mask = 0x00002090,
+
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */
+ {
+ .comp_mask = 0x00002038,
+ .addr_sync_mask = 0x00002094,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */
+ {
+ .comp_mask = 0x0000203C,
+ .addr_sync_mask = 0x00002098,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */
+ {
+ .comp_mask = 0x00002040,
+ .addr_sync_mask = 0x0000209C,
+ },
+ },
+ .num_out = 4,
+ .vfe_out_hw_info = {
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI3,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ },
+};
+
+static struct cam_vfe_hw_info cam_vfe_lite170_hw_info = {
+ .irq_reg_info = &vfe170_top_irq_reg_info,
+
+ .bus_version = CAM_VFE_BUS_VER_2_0,
+ .bus_hw_info = &vfe170_bus_hw_info,
+
+ .top_version = CAM_VFE_TOP_VER_2_0,
+ .top_hw_info = &vfe170_top_hw_info,
+
+};
+
+#endif /* _CAM_VFE_LITE170_H_ */
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
index 005d7e0..cb5c0a7 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
@@ -184,6 +184,8 @@
struct cam_vfe_bus_ver2_priv {
struct cam_vfe_bus_ver2_common_data common_data;
+ uint32_t num_client;
+ uint32_t num_out;
struct cam_isp_resource_node bus_client[CAM_VFE_BUS_VER2_MAX_CLIENTS];
struct cam_isp_resource_node comp_grp[CAM_VFE_BUS_VER2_COMP_GRP_MAX];
@@ -394,6 +396,8 @@
return CAM_VFE_BUS_VER2_VFE_OUT_RDI1;
case CAM_ISP_IFE_OUT_RES_RDI_2:
return CAM_VFE_BUS_VER2_VFE_OUT_RDI2;
+ case CAM_ISP_IFE_OUT_RES_RDI_3:
+ return CAM_VFE_BUS_VER2_VFE_OUT_RDI3;
case CAM_ISP_IFE_OUT_RES_STATS_HDR_BE:
return CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE;
case CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST:
@@ -425,6 +429,7 @@
case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI3:
switch (format) {
case CAM_FORMAT_MIPI_RAW_8:
case CAM_FORMAT_MIPI_RAW_10:
@@ -551,6 +556,42 @@
int wm_idx = -1;
switch (vfe_out_res_id) {
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 0;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 2;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI3:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 3;
+ break;
+ default:
+ break;
+ }
+ break;
case CAM_VFE_BUS_VER2_VFE_OUT_FULL:
switch (plane) {
case PLANE_Y:
@@ -611,33 +652,6 @@
break;
}
break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 0;
- break;
- default:
- break;
- }
- break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 1;
- break;
- default:
- break;
- }
- break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 2;
- break;
- default:
- break;
- }
- break;
case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE:
switch (plane) {
case PLANE_Y:
@@ -792,7 +806,7 @@
/* No need to allocate for BUS VER2. VFE OUT to WM is fixed. */
wm_idx = cam_vfe_bus_get_wm_idx(vfe_out_res_id, plane);
- if (wm_idx < 0 || wm_idx >= CAM_VFE_BUS_VER2_MAX_CLIENTS) {
+ if (wm_idx < 0 || wm_idx >= ver2_bus_priv->num_client) {
CAM_ERR(CAM_ISP, "Unsupported VFE out %d plane %d",
vfe_out_res_id, plane);
return -EINVAL;
@@ -2168,7 +2182,8 @@
vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE;
INIT_LIST_HEAD(&vfe_out->list);
- rsrc_data->out_type = index;
+ rsrc_data->out_type =
+ ver2_hw_info->vfe_out_hw_info[index].vfe_out_type;
rsrc_data->common_data = &ver2_bus_priv->common_data;
rsrc_data->max_width =
ver2_hw_info->vfe_out_hw_info[index].max_width;
@@ -2783,6 +2798,8 @@
}
vfe_bus_local->bus_priv = bus_priv;
+ bus_priv->num_client = ver2_hw_info->num_client;
+ bus_priv->num_out = ver2_hw_info->num_out;
bus_priv->common_data.num_sec_out = 0;
bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE;
bus_priv->common_data.core_index = soc_info->index;
@@ -2808,7 +2825,7 @@
INIT_LIST_HEAD(&bus_priv->free_dual_comp_grp);
INIT_LIST_HEAD(&bus_priv->used_comp_grp);
- for (i = 0; i < CAM_VFE_BUS_VER2_MAX_CLIENTS; i++) {
+ for (i = 0; i < bus_priv->num_client; i++) {
rc = cam_vfe_bus_init_wm_resource(i, bus_priv, bus_hw_info,
&bus_priv->bus_client[i]);
if (rc < 0) {
@@ -2826,7 +2843,7 @@
}
}
- for (i = 0; i < CAM_VFE_BUS_VER2_VFE_OUT_MAX; i++) {
+ for (i = 0; i < bus_priv->num_out; i++) {
rc = cam_vfe_bus_init_vfe_out_resource(i, bus_priv, bus_hw_info,
&bus_priv->vfe_out[i]);
if (rc < 0) {
@@ -2859,7 +2876,7 @@
deinit_vfe_out:
if (i < 0)
- i = CAM_VFE_BUS_VER2_VFE_OUT_MAX;
+ i = bus_priv->num_out;
for (--i; i >= 0; i--)
cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]);
@@ -2871,7 +2888,7 @@
deinit_wm:
if (i < 0)
- i = CAM_VFE_BUS_VER2_MAX_CLIENTS;
+ i = bus_priv->num_client;
for (--i; i >= 0; i--)
cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]);
@@ -2909,7 +2926,7 @@
for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++)
INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list);
- for (i = 0; i < CAM_VFE_BUS_VER2_MAX_CLIENTS; i++) {
+ for (i = 0; i < bus_priv->num_client; i++) {
rc = cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]);
if (rc < 0)
CAM_ERR(CAM_ISP,
@@ -2923,7 +2940,7 @@
"Deinit Comp Grp failed rc=%d", rc);
}
- for (i = 0; i < CAM_VFE_BUS_VER2_VFE_OUT_MAX; i++) {
+ for (i = 0; i < bus_priv->num_out; i++) {
rc = cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]);
if (rc < 0)
CAM_ERR(CAM_ISP,
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
index c90d4ce..8b55309 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
@@ -42,15 +42,16 @@
};
enum cam_vfe_bus_ver2_vfe_out_type {
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI3,
CAM_VFE_BUS_VER2_VFE_OUT_FULL,
CAM_VFE_BUS_VER2_VFE_OUT_DS4,
CAM_VFE_BUS_VER2_VFE_OUT_DS16,
CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP,
CAM_VFE_BUS_VER2_VFE_OUT_FD,
CAM_VFE_BUS_VER2_VFE_OUT_PDAF,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG,
@@ -160,11 +161,13 @@
* @vfe_out_hw_info: VFE output capability
*/
struct cam_vfe_bus_ver2_hw_info {
- struct cam_vfe_bus_ver2_reg_offset_common common_reg;
+ struct cam_vfe_bus_ver2_reg_offset_common common_reg;
+ uint32_t num_client;
struct cam_vfe_bus_ver2_reg_offset_bus_client
bus_client_reg[CAM_VFE_BUS_VER2_MAX_CLIENTS];
struct cam_vfe_bus_ver2_reg_offset_comp_grp
comp_grp_reg[CAM_VFE_BUS_VER2_COMP_GRP_MAX];
+ uint32_t num_out;
struct cam_vfe_bus_ver2_vfe_out_hw_info
vfe_out_hw_info[CAM_VFE_BUS_VER2_VFE_OUT_MAX];
};
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
index c089911..0763bca 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
@@ -17,8 +17,8 @@
#include "cam_hw_intf.h"
#include "cam_isp_hw.h"
-#define CAM_VFE_BUS_VER_1_0 0x1000
-#define CAM_VFE_BUS_VER_2_0 0x2000
+#define CAM_VFE_BUS_VER_1_0 0x1000
+#define CAM_VFE_BUS_VER_2_0 0x2000
enum cam_vfe_bus_plane_type {
PLANE_Y,
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
index 2cd6b04..35c2717 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
@@ -28,8 +28,6 @@
#include "cam_hw_mgr_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_jpeg_hw_mgr.h"
-#include "cam_enc_hw_intf.h"
-#include "cam_dma_hw_intf.h"
#include "cam_smmu_api.h"
#include "cam_mem_mgr.h"
#include "cam_req_mgr_workq.h"
@@ -38,6 +36,9 @@
#include "cam_debug_util.h"
#define CAM_JPEG_HW_ENTRIES_MAX 20
+#define CAM_JPEG_CHBASE 0
+#define CAM_JPEG_CFG 1
+#define CAM_JPEG_PARAM 2
static struct cam_jpeg_hw_mgr g_jpeg_hw_mgr;
@@ -88,13 +89,20 @@
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(
hw_mgr->devices[dev_type][0]->hw_priv,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_SET_IRQ_CB,
&irq_cb, sizeof(irq_cb));
if (rc) {
CAM_ERR(CAM_JPEG, "CMD_SET_IRQ_CB failed %d", rc);
return rc;
}
+ if (hw_mgr->devices[dev_type][0]->hw_ops.deinit) {
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.deinit(
+ hw_mgr->devices[dev_type][0]->hw_priv, NULL, 0);
+ if (rc)
+ CAM_ERR(CAM_JPEG, "Failed to Deinit %d HW", dev_type);
+ }
+
mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex);
hw_mgr->device_in_use[dev_type][0] = false;
p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0];
@@ -126,7 +134,8 @@
}
rc = cam_mem_get_cpu_buf(
- p_cfg_req->hw_cfg_args.hw_update_entries[1].handle,
+ p_cfg_req->hw_cfg_args.
+ hw_update_entries[CAM_JPEG_PARAM].handle,
(uint64_t *)&kaddr, &cmd_buf_len);
if (rc) {
CAM_ERR(CAM_JPEG, "unable to get info for cmd buf: %x %d",
@@ -137,8 +146,8 @@
cmd_buf_kaddr = (uint32_t *)kaddr;
cmd_buf_kaddr =
- (cmd_buf_kaddr +
- (p_cfg_req->hw_cfg_args.hw_update_entries[1].offset/4));
+ (cmd_buf_kaddr + (p_cfg_req->hw_cfg_args.
+ hw_update_entries[CAM_JPEG_PARAM].offset / sizeof(uint32_t)));
p_params = (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr;
@@ -234,6 +243,59 @@
return 0;
}
+static int cam_jpeg_insert_cdm_change_base(
+ struct cam_hw_config_args *config_args,
+ struct cam_jpeg_hw_ctx_data *ctx_data,
+ struct cam_jpeg_hw_mgr *hw_mgr)
+{
+ int rc;
+ uint32_t dev_type;
+ struct cam_cdm_bl_request *cdm_cmd;
+ uint32_t size;
+ uint32_t mem_cam_base;
+ uint64_t iova_addr;
+ uint32_t *ch_base_iova_addr;
+ size_t ch_base_len;
+
+ rc = cam_mem_get_cpu_buf(config_args->
+ hw_update_entries[CAM_JPEG_CHBASE].handle,
+ &iova_addr, &ch_base_len);
+ if (rc) {
+ CAM_ERR(CAM_JPEG,
+ "unable to get src buf info for cmd buf: %d", rc);
+ return rc;
+ }
+ CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d",
+ (void *)iova_addr, ch_base_len,
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].offset);
+ ch_base_iova_addr = (uint32_t *)iova_addr;
+ ch_base_iova_addr = (ch_base_iova_addr +
+ (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset /
+ sizeof(uint32_t)));
+
+ dev_type = ctx_data->jpeg_dev_acquire_info.dev_type;
+ mem_cam_base = hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base;
+ size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_required_size_changebase();
+ hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_write_changebase(ch_base_iova_addr, mem_cam_base);
+
+ cdm_cmd = ctx_data->cdm_cmd;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].bl_addr.mem_handle =
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].handle;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset =
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].offset;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = size * sizeof(uint32_t);
+ cdm_cmd->cmd_arrary_count++;
+
+ ch_base_iova_addr += size;
+ *ch_base_iova_addr = 0;
+ ch_base_iova_addr += size;
+ *ch_base_iova_addr = 0;
+
+ return rc;
+}
+
static int cam_jpeg_mgr_process_cmd(void *priv, void *data)
{
int rc;
@@ -249,11 +311,10 @@
uint32_t dev_type;
struct cam_jpeg_set_irq_cb irq_cb;
struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL;
+ struct cam_hw_done_event_data buf_data;
uint32_t size = 0;
uint32_t mem_cam_base = 0;
- struct cam_hw_done_event_data buf_data;
- CAM_DBG(CAM_JPEG, "in cam_jpeg_mgr_process_cmd");
if (!hw_mgr || !task_data) {
CAM_ERR(CAM_JPEG, "Invalid arguments %pK %pK",
hw_mgr, task_data);
@@ -296,7 +357,8 @@
if (!config_args->num_hw_update_entries) {
CAM_ERR(CAM_JPEG, "No hw update enteries are available");
- return -EINVAL;
+ rc = -EINVAL;
+ goto end_unusedev;
}
mutex_lock(&hw_mgr->hw_mgr_mutex);
@@ -304,7 +366,8 @@
if (!ctx_data->in_use) {
CAM_ERR(CAM_JPEG, "ctx is not in use");
mutex_unlock(&hw_mgr->hw_mgr_mutex);
- return -EINVAL;
+ rc = -EINVAL;
+ goto end_unusedev;
}
mutex_unlock(&hw_mgr->hw_mgr_mutex);
@@ -313,99 +376,123 @@
if (dev_type != p_cfg_req->dev_type)
CAM_WARN(CAM_JPEG, "dev types not same something wrong");
+ if (!hw_mgr->devices[dev_type][0]->hw_ops.init) {
+ CAM_ERR(CAM_JPEG, "hw op init null ");
+ rc = -EFAULT;
+ goto end;
+ }
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.init(
+ hw_mgr->devices[dev_type][0]->hw_priv,
+ ctx_data,
+ sizeof(ctx_data));
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
+ goto end;
+ }
+
irq_cb.jpeg_hw_mgr_cb = cam_jpeg_hw_mgr_cb;
irq_cb.data = (void *)ctx_data;
irq_cb.b_set_cb = true;
if (!hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) {
CAM_ERR(CAM_JPEG, "op process_cmd null ");
- return -EINVAL;
+ rc = -EFAULT;
+ goto end_callcb;
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(
hw_mgr->devices[dev_type][0]->hw_priv,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_SET_IRQ_CB,
&irq_cb, sizeof(irq_cb));
if (rc) {
CAM_ERR(CAM_JPEG, "SET_IRQ_CB failed %d", rc);
- return -EINVAL;
+ goto end_callcb;
}
if (!hw_mgr->devices[dev_type][0]->hw_ops.reset) {
CAM_ERR(CAM_JPEG, "op reset null ");
- return -EINVAL;
+ rc = -EFAULT;
+ goto end_callcb;
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.reset(
hw_mgr->devices[dev_type][0]->hw_priv,
NULL, 0);
if (rc) {
CAM_ERR(CAM_JPEG, "jpeg hw reset failed %d", rc);
- return -EINVAL;
+ goto end_callcb;
}
- mem_cam_base = (uint64_t)hw_mgr->cdm_reg_map[dev_type][0]->
- mem_cam_base;
- size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
- cdm_required_size_changebase();
- hw_mgr->cdm_info[dev_type][0].cdm_ops->
- cdm_write_changebase(ctx_data->cmd_chbase_buf_addr,
- (uint64_t)hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base);
- ctx_data->cdm_cmd_chbase->cmd_arrary_count = 1;
- ctx_data->cdm_cmd_chbase->type = CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA;
- ctx_data->cdm_cmd_chbase->flag = false;
- ctx_data->cdm_cmd_chbase->userdata = NULL;
- ctx_data->cdm_cmd_chbase->cookie = 0;
- ctx_data->cdm_cmd_chbase->cmd[0].bl_addr.kernel_iova =
- ctx_data->cmd_chbase_buf_addr;
- ctx_data->cdm_cmd_chbase->cmd[0].offset = 0;
- ctx_data->cdm_cmd_chbase->cmd[0].len = size;
- rc = cam_cdm_submit_bls(hw_mgr->cdm_info[dev_type][0].cdm_handle,
- ctx_data->cdm_cmd_chbase);
- if (rc)
- CAM_ERR(CAM_JPEG, "failed cdm cmd %d", rc);
+ cdm_cmd = ctx_data->cdm_cmd;
+ cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE;
+ cdm_cmd->flag = false;
+ cdm_cmd->userdata = NULL;
+ cdm_cmd->cookie = 0;
+ cdm_cmd->cmd_arrary_count = 0;
- CAM_DBG(CAM_JPEG, "cfg e %pK num %d",
- config_args->hw_update_entries,
- config_args->num_hw_update_entries);
-
- if (config_args->num_hw_update_entries > 0) {
- cdm_cmd = ctx_data->cdm_cmd;
- cdm_cmd->cmd_arrary_count =
- config_args->num_hw_update_entries - 1;
- cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE;
- cdm_cmd->flag = false;
- cdm_cmd->userdata = NULL;
- cdm_cmd->cookie = 0;
-
- for (i = 0; i <= cdm_cmd->cmd_arrary_count; i++) {
- cmd = (config_args->hw_update_entries + i);
- cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle;
- cdm_cmd->cmd[i].offset = cmd->offset;
- cdm_cmd->cmd[i].len = cmd->len;
- }
-
- rc = cam_cdm_submit_bls(
- hw_mgr->cdm_info[dev_type][0].cdm_handle,
- cdm_cmd);
+ /* if for backward compat */
+ if (config_args->hw_update_entries[CAM_JPEG_CHBASE].handle) {
+ rc = cam_jpeg_insert_cdm_change_base(config_args,
+ ctx_data, hw_mgr);
if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
- rc);
- goto end_callcb;
- }
-
- if (!hw_mgr->devices[dev_type][0]->hw_ops.start) {
- CAM_ERR(CAM_JPEG, "op start null ");
- rc = -EINVAL;
- goto end_callcb;
- }
- rc = hw_mgr->devices[dev_type][0]->hw_ops.start(
- hw_mgr->devices[dev_type][0]->hw_priv,
- NULL, 0);
- if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
- rc);
+ CAM_ERR(CAM_JPEG, "insert change base failed %d", rc);
goto end_callcb;
}
} else {
- CAM_ERR(CAM_JPEG, "No commands to config");
+ mem_cam_base = hw_mgr->cdm_reg_map[dev_type][0]->
+ mem_cam_base;
+ size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_required_size_changebase();
+ hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_write_changebase(ctx_data->cmd_chbase_buf_addr,
+ hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base);
+ ctx_data->cdm_cmd_chbase->cmd_arrary_count = 1;
+ ctx_data->cdm_cmd_chbase->type =
+ CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA;
+ ctx_data->cdm_cmd_chbase->flag = false;
+ ctx_data->cdm_cmd_chbase->userdata = NULL;
+ ctx_data->cdm_cmd_chbase->cookie = 0;
+ ctx_data->cdm_cmd_chbase->cmd[0].bl_addr.kernel_iova =
+ ctx_data->cmd_chbase_buf_addr;
+ ctx_data->cdm_cmd_chbase->cmd[0].offset = 0;
+ ctx_data->cdm_cmd_chbase->cmd[0].len = size;
+ cam_cdm_submit_bls(hw_mgr->cdm_info[dev_type][0].
+ cdm_handle,
+ ctx_data->cdm_cmd_chbase);
+ }
+
+ CAM_DBG(CAM_JPEG, "num hw up %d", config_args->num_hw_update_entries);
+ for (i = CAM_JPEG_CFG; i < (config_args->num_hw_update_entries - 1);
+ i++) {
+ cmd = (config_args->hw_update_entries + i);
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].
+ bl_addr.mem_handle = cmd->handle;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset =
+ cmd->offset;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len =
+ cmd->len;
+ CAM_DBG(CAM_JPEG, "i %d entry h %d o %d l %d",
+ i, cmd->handle, cmd->offset, cmd->len);
+ cdm_cmd->cmd_arrary_count++;
+ }
+
+ rc = cam_cdm_submit_bls(
+ hw_mgr->cdm_info[dev_type][0].cdm_handle,
+ cdm_cmd);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to apply the configs %d", rc);
+ goto end_callcb;
+ }
+
+ if (!hw_mgr->devices[dev_type][0]->hw_ops.start) {
+ CAM_ERR(CAM_JPEG, "op start null ");
+ rc = -EINVAL;
+ goto end_callcb;
+ }
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.start(
+ hw_mgr->devices[dev_type][0]->hw_priv,
+ NULL, 0);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
+ rc);
+ goto end_callcb;
}
return rc;
@@ -423,6 +510,12 @@
(uint64_t)p_cfg_req->hw_cfg_args.priv;
ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data);
}
+end_unusedev:
+ mutex_lock(&hw_mgr->hw_mgr_mutex);
+ hw_mgr->device_in_use[p_cfg_req->dev_type][0] = false;
+ hw_mgr->dev_hw_cfg_args[p_cfg_req->dev_type][0] = NULL;
+ mutex_unlock(&hw_mgr->hw_mgr_mutex);
+
end:
return rc;
@@ -535,6 +628,7 @@
struct cam_packet *packet = NULL;
struct cam_cmd_buf_desc *cmd_desc = NULL;
struct cam_buf_io_cfg *io_cfg_ptr = NULL;
+ struct cam_kmd_buf_info kmd_buf;
if (!prepare_args || !hw_mgr) {
CAM_ERR(CAM_JPEG, "Invalid args %pK %pK",
@@ -564,7 +658,17 @@
packet->header.op_code & 0xff);
return -EINVAL;
}
- if ((packet->num_cmd_buf > 2) || !packet->num_patches ||
+
+ /* if for backward compat */
+ if (packet->kmd_cmd_buf_index != -1) {
+ rc = cam_packet_util_validate_packet(packet);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "invalid packet %d", rc);
+ return rc;
+ }
+ }
+
+ if ((packet->num_cmd_buf > 5) || !packet->num_patches ||
!packet->num_io_configs) {
CAM_ERR(CAM_JPEG, "wrong number of cmd/patch info: %u %u",
packet->num_cmd_buf,
@@ -611,16 +715,35 @@
i, io_cfg_ptr[i].direction, io_cfg_ptr[i].fence);
}
- for (i = 0; i < packet->num_cmd_buf; i++) {
- prepare_args->hw_update_entries[i].len =
- (uint32_t)cmd_desc[i].length;
- prepare_args->hw_update_entries[i].handle =
- (uint32_t)cmd_desc[i].mem_handle;
- prepare_args->hw_update_entries[i].offset =
- (uint32_t)cmd_desc[i].offset;
- prepare_args->num_hw_update_entries++;
+ j = prepare_args->num_hw_update_entries;
+ /* if-else for backward compat */
+ if (packet->kmd_cmd_buf_index != -1) {
+ rc = cam_packet_util_get_kmd_buffer(packet, &kmd_buf);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "get kmd buf failed %d", rc);
+ return rc;
+ }
+ } else {
+ memset(&kmd_buf, 0x0, sizeof(kmd_buf));
}
+ /* fill kmd buf info into 1st hw update entry */
+ prepare_args->hw_update_entries[j].len =
+ (uint32_t)kmd_buf.used_bytes;
+ prepare_args->hw_update_entries[j].handle =
+ (uint32_t)kmd_buf.handle;
+ prepare_args->hw_update_entries[j].offset =
+ (uint32_t)kmd_buf.offset;
+ j++;
+ for (i = 0; i < packet->num_cmd_buf; i++, j++) {
+ prepare_args->hw_update_entries[j].len =
+ (uint32_t)cmd_desc[i].length;
+ prepare_args->hw_update_entries[j].handle =
+ (uint32_t)cmd_desc[i].mem_handle;
+ prepare_args->hw_update_entries[j].offset =
+ (uint32_t)cmd_desc[i].offset;
+ }
+ prepare_args->num_hw_update_entries = j;
prepare_args->priv = (void *)packet->header.request_id;
CAM_DBG(CAM_JPEG, "will wait on input sync sync_id %d",
@@ -651,6 +774,11 @@
dev_type = ctx_data->jpeg_dev_acquire_info.dev_type;
mutex_lock(&hw_mgr->hw_mgr_mutex);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 0) {
+ mutex_unlock(&hw_mgr->hw_mgr_mutex);
+ CAM_ERR(CAM_JPEG, "Error Unbalanced deinit");
+ return -EFAULT;
+ }
hw_mgr->cdm_info[dev_type][0].ref_cnt--;
if (!(hw_mgr->cdm_info[dev_type][0].ref_cnt)) {
@@ -663,12 +791,6 @@
cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
}
- if (g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.deinit) {
- rc = g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.deinit(
- g_jpeg_hw_mgr.devices[dev_type][0]->hw_priv, NULL, 0);
- if (rc)
- CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
- }
mutex_unlock(&hw_mgr->hw_mgr_mutex);
rc = cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data);
@@ -787,20 +909,6 @@
goto start_cdm_hdl_failed;
}
- if (!g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.init) {
- CAM_ERR(CAM_JPEG, "hw op init null ");
- rc = -EINVAL;
- goto start_cdm_hdl_failed;
- }
- rc = g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.init(
- g_jpeg_hw_mgr.devices[dev_type][0]->hw_priv,
- ctx_data,
- sizeof(ctx_data));
- if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
- goto start_cdm_hdl_failed;
- }
-
if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
if (cam_cdm_stream_on(
hw_mgr->cdm_info[dev_type][0].cdm_handle)) {
@@ -833,9 +941,12 @@
return rc;
copy_to_user_failed:
- cam_cdm_stream_off(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
+ cam_cdm_stream_off(hw_mgr->cdm_info[dev_type][0].cdm_handle);
start_cdm_hdl_failed:
- cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
+ cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ hw_mgr->cdm_info[dev_type][0].ref_cnt--;
acq_cdm_hdl_failed:
kfree(ctx_data->cdm_cmd);
cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data);
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h
deleted file mode 100644
index f0b4e00..0000000
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef CAM_JPEG_ENC_HW_INTF_H
-#define CAM_JPEG_ENC_HW_INTF_H
-
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_enc_cmd_type {
- CAM_JPEG_ENC_CMD_CDM_CFG,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
- CAM_JPEG_ENC_CMD_MAX,
-};
-
-#endif /* CAM_JPEG_ENC_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
index 3204388..44b134a 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
@@ -13,14 +13,32 @@
#ifndef CAM_JPEG_HW_INTF_H
#define CAM_JPEG_HW_INTF_H
+#include "cam_cpas_api.h"
+
#define CAM_JPEG_CTX_MAX 8
#define CAM_JPEG_DEV_PER_TYPE_MAX 1
#define CAM_JPEG_CMD_BUF_MAX_SIZE 128
#define CAM_JPEG_MSG_BUF_MAX_SIZE CAM_JPEG_CMD_BUF_MAX_SIZE
+#define JPEG_VOTE 640000000
+
enum cam_jpeg_hw_type {
CAM_JPEG_DEV_ENC,
CAM_JPEG_DEV_DMA,
};
+
+struct cam_jpeg_set_irq_cb {
+ int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
+ int32_t result_size, void *data);
+ void *data;
+ uint32_t b_set_cb;
+};
+
+enum cam_jpeg_cmd_type {
+ CAM_JPEG_CMD_CDM_CFG,
+ CAM_JPEG_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_MAX,
+};
+
#endif
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
index d5c8c9d..5fb4e3ad 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
@@ -17,34 +17,8 @@
#include <uapi/media/cam_defs.h>
#include <linux/of.h>
-#include "cam_cpas_api.h"
-
-#define JPEG_TURBO_VOTE 640000000
int cam_jpeg_hw_mgr_init(struct device_node *of_node,
uint64_t *hw_mgr_hdl);
-/**
- * struct cam_jpeg_cpas_vote
- * @ahb_vote: AHB vote info
- * @axi_vote: AXI vote info
- * @ahb_vote_valid: Flag for ahb vote data
- * @axi_vote_valid: Flag for axi vote data
- */
-struct cam_jpeg_cpas_vote {
- struct cam_ahb_vote ahb_vote;
- struct cam_axi_vote axi_vote;
- uint32_t ahb_vote_valid;
- uint32_t axi_vote_valid;
-};
-
-struct cam_jpeg_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(
- uint32_t irq_status,
- int32_t result_size,
- void *data);
- void *data;
- uint32_t b_set_cb;
-};
-
#endif /* CAM_JPEG_HW_MGR_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
index 0a15f71..2d343dd 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
@@ -26,7 +26,6 @@
#include "jpeg_dma_soc.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
-#include "cam_dma_hw_intf.h"
#include "cam_jpeg_hw_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
@@ -38,7 +37,8 @@
struct cam_hw_info *jpeg_dma_dev = device_priv;
struct cam_hw_soc_info *soc_info = NULL;
struct cam_jpeg_dma_device_core_info *core_info = NULL;
- struct cam_jpeg_cpas_vote cpas_vote;
+ struct cam_ahb_vote ahb_vote;
+ struct cam_axi_vote axi_vote;
int rc;
if (!device_priv) {
@@ -57,20 +57,19 @@
return -EINVAL;
}
-
mutex_lock(&core_info->core_mutex);
if (++core_info->ref_count > 1) {
mutex_unlock(&core_info->core_mutex);
return 0;
}
- cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;
- cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;
- cpas_vote.axi_vote.compressed_bw = JPEG_TURBO_VOTE;
- cpas_vote.axi_vote.uncompressed_bw = JPEG_TURBO_VOTE;
+ ahb_vote.type = CAM_VOTE_ABSOLUTE;
+ ahb_vote.vote.level = CAM_SVS_VOTE;
+ axi_vote.compressed_bw = JPEG_VOTE;
+ axi_vote.uncompressed_bw = JPEG_VOTE;
rc = cam_cpas_start(core_info->cpas_handle,
- &cpas_vote.ahb_vote, &cpas_vote.axi_vote);
+ &ahb_vote, &axi_vote);
if (rc) {
CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc);
goto cpas_failed;
@@ -91,6 +90,7 @@
cpas_failed:
--core_info->ref_count;
mutex_unlock(&core_info->core_mutex);
+
return rc;
}
@@ -154,7 +154,7 @@
return -EINVAL;
}
- if (cmd_type >= CAM_JPEG_DMA_CMD_MAX) {
+ if (cmd_type >= CAM_JPEG_CMD_MAX) {
CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type);
return -EINVAL;
}
@@ -164,7 +164,7 @@
core_info;
switch (cmd_type) {
- case CAM_JPEG_DMA_CMD_SET_IRQ_CB:
+ case CAM_JPEG_CMD_SET_IRQ_CB:
{
struct cam_jpeg_set_irq_cb *irq_cb = cmd_args;
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
index 1e0c2e2..a4d5d89 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
@@ -19,16 +19,12 @@
#include <linux/platform_device.h>
#include <linux/dma-buf.h>
+#include "cam_jpeg_hw_intf.h"
+
struct cam_jpeg_dma_device_hw_info {
uint32_t reserved;
};
-struct cam_jpeg_dma_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
- int32_t result_size, void *data);
- void *data;
-};
-
enum cam_jpeg_dma_core_state {
CAM_JPEG_DMA_CORE_NOT_READY,
CAM_JPEG_DMA_CORE_READY,
@@ -40,7 +36,7 @@
enum cam_jpeg_dma_core_state core_state;
struct cam_jpeg_dma_device_hw_info *jpeg_dma_hw_info;
uint32_t cpas_handle;
- struct cam_jpeg_dma_set_irq_cb irq_cb;
+ struct cam_jpeg_set_irq_cb irq_cb;
int32_t ref_count;
struct mutex core_mutex;
};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h
new file mode 100644
index 0000000..725af47
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CAM_JPEG_ENC_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+ CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+ CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+ (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+ CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = {
+ .reg_offset = {
+ .hw_version = 0x0,
+ .int_clr = 0x1c,
+ .int_status = 0x20,
+ .int_mask = 0x18,
+ .hw_cmd = 0x10,
+ .reset_cmd = 0x8,
+ .encode_size = 0x180,
+ },
+ .reg_val = {
+ .int_clr_clearall = 0xFFFFFFFF,
+ .int_mask_disable_all = 0x00000000,
+ .int_mask_enable_all = 0xFFFFFFFF,
+ .hw_cmd_start = 0x00000001,
+ .reset_cmd = 0x00032093,
+ },
+ .int_status = {
+ .framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+ .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+ .iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+ }
+};
+
+#endif /* CAM_JPEG_ENC_HW_INFO_TITAN170_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
index 06ad260..a7c4e06 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
@@ -26,52 +26,17 @@
#include "jpeg_enc_soc.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
-#include "cam_enc_hw_intf.h"
#include "cam_jpeg_hw_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
#include "cam_debug_util.h"
-#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
-#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
-
-#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
-#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
-
-#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
-#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
-
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26)
-#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29)
-
-#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
- CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
-#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
- CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
-#define CAM_JPEG_HW_MASK_COMP_ERR \
- (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
- CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
-
-#define CAM_JPEG_HW_IRQ_IS_FRAME_DONE(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_FRAMEDONE)
-#define CAM_JPEG_HW_IRQ_IS_RESET_ACK(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_RESET_ACK)
-#define CAM_JPEG_HW_IRQ_IS_ERR(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_ERR)
+#define CAM_JPEG_HW_IRQ_IS_FRAME_DONE(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.framedone)
+#define CAM_JPEG_HW_IRQ_IS_RESET_ACK(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.resetdone)
+#define CAM_JPEG_HW_IRQ_IS_ERR(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.iserror)
#define CAM_JPEG_ENC_RESET_TIMEOUT msecs_to_jiffies(500)
@@ -81,7 +46,8 @@
struct cam_hw_info *jpeg_enc_dev = device_priv;
struct cam_hw_soc_info *soc_info = NULL;
struct cam_jpeg_enc_device_core_info *core_info = NULL;
- struct cam_jpeg_cpas_vote cpas_vote;
+ struct cam_ahb_vote ahb_vote;
+ struct cam_axi_vote axi_vote;
int rc;
if (!device_priv) {
@@ -100,20 +66,19 @@
return -EINVAL;
}
-
mutex_lock(&core_info->core_mutex);
if (++core_info->ref_count > 1) {
mutex_unlock(&core_info->core_mutex);
return 0;
}
- cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;
- cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;
- cpas_vote.axi_vote.compressed_bw = JPEG_TURBO_VOTE;
- cpas_vote.axi_vote.uncompressed_bw = JPEG_TURBO_VOTE;
+ ahb_vote.type = CAM_VOTE_ABSOLUTE;
+ ahb_vote.vote.level = CAM_SVS_VOTE;
+ axi_vote.compressed_bw = JPEG_VOTE;
+ axi_vote.uncompressed_bw = JPEG_VOTE;
rc = cam_cpas_start(core_info->cpas_handle,
- &cpas_vote.ahb_vote, &cpas_vote.axi_vote);
+ &ahb_vote, &axi_vote);
if (rc) {
CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc);
goto cpas_failed;
@@ -134,6 +99,7 @@
cpas_failed:
--core_info->ref_count;
mutex_unlock(&core_info->core_mutex);
+
return rc;
}
@@ -174,7 +140,7 @@
rc = cam_jpeg_enc_disable_soc_resources(soc_info);
if (rc)
- CAM_ERR(CAM_JPEG, "soc enable failed %d", rc);
+ CAM_ERR(CAM_JPEG, "soc disable failed %d", rc);
rc = cam_cpas_stop(core_info->cpas_handle);
if (rc)
@@ -207,17 +173,19 @@
mem_base = soc_info->reg_map[0].mem_base;
irq_status = cam_io_r_mb(mem_base +
- core_info->jpeg_enc_hw_info->int_status);
+ core_info->jpeg_enc_hw_info->reg_offset.int_status);
cam_io_w_mb(irq_status,
soc_info->reg_map[0].mem_base +
- core_info->jpeg_enc_hw_info->int_clr);
+ core_info->jpeg_enc_hw_info->reg_offset.int_clr);
CAM_DBG(CAM_JPEG, "irq_num %d irq_status = %x , core_state %d",
irq_num, irq_status, core_info->core_state);
- if (CAM_JPEG_HW_IRQ_IS_FRAME_DONE(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_FRAME_DONE(irq_status, hw_info)) {
if (core_info->core_state == CAM_JPEG_ENC_CORE_READY) {
- encoded_size = cam_io_r_mb(mem_base + 0x180);
+ encoded_size = cam_io_r_mb(mem_base +
+ core_info->jpeg_enc_hw_info->reg_offset.
+ encode_size);
if (core_info->irq_cb.jpeg_hw_mgr_cb) {
core_info->irq_cb.jpeg_hw_mgr_cb(irq_status,
encoded_size,
@@ -229,7 +197,7 @@
core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY;
}
- if (CAM_JPEG_HW_IRQ_IS_RESET_ACK(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_RESET_ACK(irq_status, hw_info)) {
if (core_info->core_state == CAM_JPEG_ENC_CORE_RESETTING) {
core_info->core_state = CAM_JPEG_ENC_CORE_READY;
complete(&jpeg_enc_dev->hw_complete);
@@ -238,7 +206,7 @@
}
}
/* Unexpected/unintended HW interrupt */
- if (CAM_JPEG_HW_IRQ_IS_ERR(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_ERR(irq_status, hw_info)) {
core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY;
CAM_ERR_RATE_LIMIT(CAM_JPEG,
"error irq_num %d irq_status = %x , core_state %d",
@@ -285,10 +253,14 @@
core_info->core_state = CAM_JPEG_ENC_CORE_RESETTING;
- cam_io_w_mb(0x00000000, mem_base + hw_info->int_mask);
- cam_io_w_mb(0xFFFFFFFF, mem_base + hw_info->int_clr);
- cam_io_w_mb(0xFFFFFFFF, mem_base + hw_info->int_mask);
- cam_io_w_mb(0x00032093, mem_base + hw_info->reset_cmd);
+ cam_io_w_mb(hw_info->reg_val.int_mask_disable_all,
+ mem_base + hw_info->reg_offset.int_mask);
+ cam_io_w_mb(hw_info->reg_val.int_clr_clearall,
+ mem_base + hw_info->reg_offset.int_clr);
+ cam_io_w_mb(hw_info->reg_val.int_mask_enable_all,
+ mem_base + hw_info->reg_offset.int_mask);
+ cam_io_w_mb(hw_info->reg_val.reset_cmd,
+ mem_base + hw_info->reg_offset.reset_cmd);
rem_jiffies = wait_for_completion_timeout(&jpeg_enc_dev->hw_complete,
CAM_JPEG_ENC_RESET_TIMEOUT);
@@ -325,7 +297,8 @@
return -EINVAL;
}
- cam_io_w_mb(0x00000001, mem_base + 0x00000010);
+ cam_io_w_mb(hw_info->reg_val.hw_cmd_start,
+ mem_base + hw_info->reg_offset.hw_cmd);
return 0;
}
@@ -342,7 +315,7 @@
return -EINVAL;
}
- if (cmd_type >= CAM_JPEG_ENC_CMD_MAX) {
+ if (cmd_type >= CAM_JPEG_CMD_MAX) {
CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type);
return -EINVAL;
}
@@ -352,7 +325,7 @@
core_info;
switch (cmd_type) {
- case CAM_JPEG_ENC_CMD_SET_IRQ_CB:
+ case CAM_JPEG_CMD_SET_IRQ_CB:
{
struct cam_jpeg_set_irq_cb *irq_cb = cmd_args;
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
index eb5caef..4f5d625 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
@@ -19,18 +19,36 @@
#include <linux/platform_device.h>
#include <linux/dma-buf.h>
-struct cam_jpeg_enc_device_hw_info {
+#include "cam_jpeg_hw_intf.h"
+
+struct cam_jpeg_enc_reg_offsets {
uint32_t hw_version;
uint32_t int_status;
uint32_t int_clr;
uint32_t int_mask;
+ uint32_t hw_cmd;
+ uint32_t reset_cmd;
+ uint32_t encode_size;
+};
+
+struct cam_jpeg_enc_regval {
+ uint32_t int_clr_clearall;
+ uint32_t int_mask_disable_all;
+ uint32_t int_mask_enable_all;
+ uint32_t hw_cmd_start;
uint32_t reset_cmd;
};
-struct cam_jpeg_enc_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
- int32_t result_size, void *data);
- void *data;
+struct cam_jpeg_enc_int_status {
+ uint32_t framedone;
+ uint32_t resetdone;
+ uint32_t iserror;
+};
+
+struct cam_jpeg_enc_device_hw_info {
+ struct cam_jpeg_enc_reg_offsets reg_offset;
+ struct cam_jpeg_enc_regval reg_val;
+ struct cam_jpeg_enc_int_status int_status;
};
enum cam_jpeg_enc_core_state {
@@ -44,7 +62,7 @@
enum cam_jpeg_enc_core_state core_state;
struct cam_jpeg_enc_device_hw_info *jpeg_enc_hw_info;
uint32_t cpas_handle;
- struct cam_jpeg_enc_set_irq_cb irq_cb;
+ struct cam_jpeg_set_irq_cb irq_cb;
int32_t ref_count;
struct mutex core_mutex;
};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
index 570d9f9..735bd21 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
@@ -25,15 +25,7 @@
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
#include "cam_debug_util.h"
-
-static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = {
- .int_clr = 0x1c,
- .int_status = 0x20,
- .int_mask = 0x18,
- .reset_cmd = 0x8,
- .hw_version = 0x0,
-};
-EXPORT_SYMBOL(cam_jpeg_enc_hw_info);
+#include "cam_jpeg_enc_hw_info_ver_4_2_0.h"
static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info,
struct cam_jpeg_enc_device_core_info *core_info,
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
index c3475b6..ff0d32c 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
@@ -317,7 +317,7 @@
cmd_buf += (sizeof(struct cam_cmd_i2c_info)/sizeof(uint32_t));
i2c_data->init_settings.request_id = 0;
i2c_reg_settings->is_settings_valid = 1;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[1], 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -338,7 +338,7 @@
offset = (uint32_t *)&csl_packet->payload;
offset += csl_packet->cmd_buf_offset / sizeof(uint32_t);
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -358,7 +358,7 @@
offset = (uint32_t *)&csl_packet->payload;
offset += csl_packet->cmd_buf_offset / sizeof(uint32_t);
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -401,12 +401,16 @@
return -EINVAL;
}
- if (config)
+ if (config) {
+ rc = cam_soc_util_request_platform_resource(soc_info,
+ NULL, NULL);
rc = cam_soc_util_enable_platform_resource(soc_info, false, 0,
false);
- else
+ } else {
rc = cam_soc_util_disable_platform_resource(soc_info, false,
false);
+ rc = cam_soc_util_release_platform_resource(soc_info);
+ }
return rc;
}
@@ -429,15 +433,6 @@
if (soc_info->gpio_data &&
gpio_num_info &&
gpio_num_info->valid[SENSOR_VAF] == 1) {
- rc = cam_soc_util_request_platform_resource(&a_ctrl->soc_info,
- NULL, NULL);
- rc = cam_soc_util_enable_platform_resource(&a_ctrl->soc_info,
- false, 0, false);
- if (rc < 0) {
- CAM_ERR(CAM_ACTUATOR, "Failed in req gpio: %d", rc);
- return rc;
- }
-
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
1);
@@ -456,12 +451,6 @@
&a_ctrl->soc_info;
struct msm_camera_gpio_num_info *gpio_num_info = NULL;
- rc = cam_actuator_vreg_control(a_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_ACTUATOR, "Failed %d");
- return rc;
- }
-
gpio_num_info = a_ctrl->gpio_num_info;
if (soc_info->gpio_data &&
@@ -471,15 +460,12 @@
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
GPIOF_OUT_INIT_LOW);
-
- rc = cam_soc_util_release_platform_resource(&a_ctrl->soc_info);
- rc |= cam_soc_util_disable_platform_resource(&a_ctrl->soc_info,
- 0, 0);
- if (rc < 0)
- CAM_ERR(CAM_ACTUATOR,
- "Failed to disable platform resources: %d", rc);
}
+ rc = cam_actuator_vreg_control(a_ctrl, 0);
+ if (rc < 0)
+ CAM_ERR(CAM_ACTUATOR, "Disable Regulator Failed: %d", rc);
+
return rc;
}
@@ -594,6 +580,9 @@
}
break;
case CAM_STOP_DEV: {
+ struct i2c_settings_array *i2c_set = NULL;
+ int i;
+
rc = camera_io_release(&a_ctrl->io_master_info);
if (rc < 0)
CAM_ERR(CAM_ACTUATOR, "Failed in releasing CCI");
@@ -602,6 +591,17 @@
CAM_ERR(CAM_ACTUATOR, "Actuator Power down failed");
goto release_mutex;
}
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(a_ctrl->i2c_data.per_frame[i]);
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_SENSOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+ }
+ }
}
break;
case CAM_CONFIG_DEV: {
@@ -642,3 +642,50 @@
return rc;
}
+
+int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req)
+{
+ int32_t rc = 0, i;
+ uint32_t cancel_req_id_found = 0;
+ struct cam_actuator_ctrl_t *a_ctrl = NULL;
+ struct i2c_settings_array *i2c_set = NULL;
+
+ if (!flush_req)
+ return -EINVAL;
+
+ a_ctrl = (struct cam_actuator_ctrl_t *)
+ cam_get_device_priv(flush_req->dev_hdl);
+ if (!a_ctrl) {
+ CAM_ERR(CAM_ACTUATOR, "Device data is NULL");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(a_ctrl->i2c_data.per_frame[i]);
+
+ if ((flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ)
+ && (i2c_set->request_id != flush_req->req_id))
+ continue;
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_ACTUATOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+
+ if (flush_req->type ==
+ CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) {
+ cancel_req_id_found = 1;
+ break;
+ }
+ }
+ }
+
+ if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ &&
+ !cancel_req_id_found)
+ CAM_DBG(CAM_ACTUATOR,
+ "Flush request id:%lld not found in the pending list",
+ flush_req->req_id);
+ return rc;
+}
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
index d2cb96d..e5676e6 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
@@ -30,6 +30,14 @@
int32_t cam_actuator_publish_dev_info(struct cam_req_mgr_device_info *info);
/**
+ * @flush: Req mgr structure for flushing request
+ *
+ * This API flushes the request that is mentioned
+ */
+int cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush);
+
+
+/**
* @link: Link setup info
*
* This API establishes link actuator subdevice with req mgr
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
index 45dbba1..1559145 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
@@ -307,6 +307,8 @@
cam_actuator_establish_link;
a_ctrl->bridge_intf.ops.apply_req =
cam_actuator_apply_request;
+ a_ctrl->bridge_intf.ops.flush_req =
+ cam_actuator_flush_request;
platform_set_drvdata(pdev, a_ctrl);
v4l2_set_subdevdata(&a_ctrl->v4l2_dev_str.sd, a_ctrl);
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
index a173954..8a631ae 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
@@ -668,7 +668,7 @@
case CAM_EEPROM_PACKET_OPCODE_INIT:
if (e_ctrl->userspace_probe == false) {
rc = cam_eeprom_parse_read_memory_map(
- e_ctrl->pdev->dev.of_node, e_ctrl);
+ e_ctrl->soc_info.dev->of_node, e_ctrl);
if (rc < 0) {
CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc);
return rc;
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
index 0a283ab..7971b79 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
@@ -77,12 +77,16 @@
return -EINVAL;
}
- if (config)
+ if (config) {
+ rc = cam_soc_util_request_platform_resource(soc_info,
+ NULL, NULL);
rc = cam_soc_util_enable_platform_resource(soc_info, false, 0,
false);
- else
+ } else {
rc = cam_soc_util_disable_platform_resource(soc_info, false,
false);
+ rc = cam_soc_util_release_platform_resource(soc_info);
+ }
return rc;
}
@@ -105,15 +109,6 @@
if (soc_info->gpio_data &&
gpio_num_info &&
gpio_num_info->valid[SENSOR_VAF] == 1) {
- rc = cam_soc_util_request_platform_resource(&o_ctrl->soc_info,
- NULL, NULL);
- rc = cam_soc_util_enable_platform_resource(&o_ctrl->soc_info,
- false, 0, false);
- if (rc < 0) {
- CAM_ERR(CAM_OIS, "Failed in req gpio: %d", rc);
- return rc;
- }
-
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
1);
@@ -132,12 +127,6 @@
&o_ctrl->soc_info;
struct msm_camera_gpio_num_info *gpio_num_info = NULL;
- rc = cam_ois_vreg_control(o_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_OIS, "Failed %d");
- return rc;
- }
-
gpio_num_info = o_ctrl->gpio_num_info;
if (soc_info->gpio_data &&
@@ -147,15 +136,12 @@
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
GPIOF_OUT_INIT_LOW);
-
- rc = cam_soc_util_release_platform_resource(&o_ctrl->soc_info);
- rc |= cam_soc_util_disable_platform_resource(&o_ctrl->soc_info,
- 0, 0);
- if (rc < 0)
- CAM_ERR(CAM_OIS,
- "Failed to disable platform resources: %d", rc);
}
+ rc = cam_ois_vreg_control(o_ctrl, 0);
+ if (rc < 0)
+ CAM_ERR(CAM_OIS, "Disable regualtor Failed %d", rc);
+
return rc;
}
@@ -430,7 +416,7 @@
i2c_reg_settings = &(o_ctrl->i2c_init_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[1], 1);
if (rc < 0) {
CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d",
@@ -442,7 +428,7 @@
i2c_reg_settings = &(o_ctrl->i2c_calib_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[2], 1);
if (rc < 0) {
CAM_ERR(CAM_OIS,
@@ -458,7 +444,7 @@
i2c_reg_settings = &(o_ctrl->i2c_mode_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc);
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
index cd96129..856dbeb 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
@@ -17,6 +17,27 @@
#include "cam_soc_util.h"
#include "cam_trace.h"
+
+static void cam_sensor_update_req_mgr(
+ struct cam_sensor_ctrl_t *s_ctrl,
+ struct cam_packet *csl_packet)
+{
+ struct cam_req_mgr_add_request add_req;
+
+ add_req.link_hdl = s_ctrl->bridge_intf.link_hdl;
+ add_req.req_id = csl_packet->header.request_id;
+ CAM_DBG(CAM_SENSOR, " Rxed Req Id: %lld",
+ csl_packet->header.request_id);
+ add_req.dev_hdl = s_ctrl->bridge_intf.device_hdl;
+ add_req.skip_before_applying = 0;
+ if (s_ctrl->bridge_intf.crm_cb &&
+ s_ctrl->bridge_intf.crm_cb->add_req)
+ s_ctrl->bridge_intf.crm_cb->add_req(&add_req);
+
+ CAM_DBG(CAM_SENSOR, " add req to req mgr: %lld",
+ add_req.req_id);
+}
+
static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl,
void *arg)
{
@@ -30,7 +51,6 @@
uint32_t *offset = NULL;
struct cam_config_dev_cmd config;
struct i2c_data_settings *i2c_data = NULL;
- struct cam_req_mgr_add_request add_req;
ioctl_ctrl = (struct cam_control *)arg;
@@ -63,13 +83,32 @@
i2c_data = &(s_ctrl->i2c_data);
CAM_DBG(CAM_SENSOR, "Header OpCode: %d", csl_packet->header.op_code);
- if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG) {
+ switch (csl_packet->header.op_code & 0xFFFFFF) {
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: {
i2c_reg_settings = &i2c_data->init_settings;
i2c_reg_settings->request_id = 0;
i2c_reg_settings->is_settings_valid = 1;
- } else if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE) {
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG: {
+ i2c_reg_settings = &i2c_data->res_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: {
+ i2c_reg_settings = &i2c_data->streamon_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: {
+ i2c_reg_settings = &i2c_data->streamoff_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE: {
i2c_reg_settings =
&i2c_data->
per_frame[csl_packet->header.request_id %
@@ -91,10 +130,14 @@
i2c_reg_settings->request_id =
csl_packet->header.request_id;
i2c_reg_settings->is_settings_valid = 1;
- } else if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_PKT_NOP_OPCODE) {
- goto update_req_mgr;
- } else {
+ cam_sensor_update_req_mgr(s_ctrl, csl_packet);
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP: {
+ cam_sensor_update_req_mgr(s_ctrl, csl_packet);
+ return rc;
+ }
+ default:
CAM_ERR(CAM_SENSOR, "Invalid Packet Header");
return -EINVAL;
}
@@ -103,28 +146,11 @@
offset += csl_packet->cmd_buf_offset / 4;
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings, cmd_desc, 1);
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings, cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "Fail parsing I2C Pkt: %d", rc);
return rc;
}
-
-update_req_mgr:
- if (((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_PKT_NOP_OPCODE) || (csl_packet->header.op_code ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE)) {
- add_req.link_hdl = s_ctrl->bridge_intf.link_hdl;
- add_req.req_id = csl_packet->header.request_id;
- CAM_DBG(CAM_SENSOR, " Rxed Req Id: %lld",
- csl_packet->header.request_id);
- add_req.dev_hdl = s_ctrl->bridge_intf.device_hdl;
- add_req.skip_before_applying = 0;
- if (s_ctrl->bridge_intf.crm_cb &&
- s_ctrl->bridge_intf.crm_cb->add_req)
- s_ctrl->bridge_intf.crm_cb->add_req(&add_req);
- CAM_DBG(CAM_SENSOR, " add req to req mgr: %lld",
- add_req.req_id);
- }
return rc;
}
@@ -511,8 +537,12 @@
goto release_mutex;
}
- CAM_DBG(CAM_SENSOR, "Probe Succeeded on the slot: %d",
- s_ctrl->soc_info.index);
+ CAM_INFO(CAM_SENSOR,
+ "Probe Succees, slot:%d slave_addr: 0x%x, slave_id: %d",
+ s_ctrl->soc_info.index,
+ s_ctrl->sensordata->slave_info.sensor_slave_addr,
+ s_ctrl->sensordata->slave_info.sensor_id);
+
rc = cam_sensor_power_down(s_ctrl);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "fail in Sensor Power Down");
@@ -595,31 +625,67 @@
break;
}
case CAM_START_DEV: {
- rc = cam_sensor_power_up(s_ctrl);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR, "Sensor Power up failed");
- goto release_mutex;
- }
- rc = cam_sensor_apply_settings(s_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR, "cannot apply settings");
- goto release_mutex;
- }
- rc = delete_request(&s_ctrl->i2c_data.init_settings);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR,
- "Fail in deleting the Init settings");
- rc = -EINVAL;
- goto release_mutex;
+ if (s_ctrl->i2c_data.streamon_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.streamon_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply streamon settings");
+ goto release_mutex;
+ }
+ rc = delete_request(
+ &s_ctrl->i2c_data.streamon_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the streamon settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.streamon_settings.request_id = -1;
}
}
break;
case CAM_STOP_DEV: {
+ struct i2c_settings_array *i2c_set = NULL;
+ int i;
+
+ if (s_ctrl->i2c_data.streamoff_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.streamoff_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply streamoff settings");
+ goto release_mutex;
+ }
+ rc = delete_request(
+ &s_ctrl->i2c_data.streamoff_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the Streaomoff settings");
+ rc = -EINVAL;
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.streamoff_settings.request_id = -1;
+ }
rc = cam_sensor_power_down(s_ctrl);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "Sensor Power Down failed");
goto release_mutex;
}
+
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(s_ctrl->i2c_data.per_frame[i]);
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_SENSOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+ }
+ }
+
}
break;
case CAM_CONFIG_DEV: {
@@ -628,6 +694,46 @@
CAM_ERR(CAM_SENSOR, "Failed CCI Config: %d", rc);
goto release_mutex;
}
+ if (s_ctrl->i2c_data.init_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.init_settings.request_id == 0)) {
+ rc = cam_sensor_power_up(s_ctrl);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR, "Sensor Power up failed");
+ goto release_mutex;
+ }
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply init settings");
+ goto release_mutex;
+ }
+ rc = delete_request(&s_ctrl->i2c_data.init_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the Init settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.init_settings.request_id = -1;
+ }
+
+ if (s_ctrl->i2c_data.res_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.res_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply res settings");
+ goto release_mutex;
+ }
+ rc = delete_request(&s_ctrl->i2c_data.res_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the res settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.res_settings.request_id = -1;
+ }
}
break;
case CAM_SD_SHUTDOWN:
@@ -769,14 +875,35 @@
}
int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl,
- int64_t req_id)
+ int64_t req_id, enum cam_sensor_packet_opcodes opcode)
{
int rc = 0, offset, del_req_id;
struct i2c_settings_array *i2c_set = NULL;
struct i2c_settings_list *i2c_list;
if (req_id == 0) {
- i2c_set = &s_ctrl->i2c_data.init_settings;
+ switch (opcode) {
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: {
+ i2c_set = &s_ctrl->i2c_data.streamon_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: {
+ i2c_set = &s_ctrl->i2c_data.init_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG: {
+ i2c_set = &s_ctrl->i2c_data.res_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: {
+ i2c_set = &s_ctrl->i2c_data.streamoff_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE:
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE:
+ default:
+ return 0;
+ }
if (i2c_set->is_settings_valid == 1) {
list_for_each_entry(i2c_list,
&(i2c_set->list_head), list) {
@@ -790,12 +917,7 @@
return rc;
}
}
- rc = delete_request(&(s_ctrl->i2c_data.init_settings));
i2c_set->is_settings_valid = 0;
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR,
- "Failed in deleting the Init request: %d", rc);
- }
}
} else {
offset = req_id % MAX_PER_FRAME_ARRAY;
@@ -836,6 +958,7 @@
del_req_id, rc);
}
}
+
return rc;
}
@@ -855,7 +978,8 @@
}
CAM_DBG(CAM_SENSOR, " Req Id: %lld", apply->request_id);
trace_cam_apply_req("Sensor", apply->request_id);
- rc = cam_sensor_apply_settings(s_ctrl, apply->request_id);
+ rc = cam_sensor_apply_settings(s_ctrl, apply->request_id,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE);
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
index c8158fa..adc2e37 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
@@ -40,10 +40,12 @@
/**
* @s_ctrl: Sensor ctrl structure
* @req_id: Request id
+ * @opcode: opcode for settings
*
* This API applies the req_id settings to sensor
*/
-int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, int64_t req_id);
+int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, int64_t req_id,
+ enum cam_sensor_packet_opcodes opcode);
/**
* @apply: Req mgr structure for applying request
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
index 122aa3e..74d8212 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
@@ -163,6 +163,9 @@
}
INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.res_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head));
for (i = 0; i < MAX_PER_FRAME_ARRAY; i++)
INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head));
@@ -269,6 +272,9 @@
}
INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.res_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head));
for (i = 0; i < MAX_PER_FRAME_ARRAY; i++)
INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head));
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
index 97b4c01..ac1e23b 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
@@ -153,7 +153,10 @@
CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON,
CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE,
CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG,
- CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127
};
enum cam_actuator_packet_opcodes {
@@ -279,6 +282,9 @@
struct i2c_data_settings {
struct i2c_settings_array init_settings;
+ struct i2c_settings_array res_settings;
+ struct i2c_settings_array streamon_settings;
+ struct i2c_settings_array streamoff_settings;
struct i2c_settings_array *per_frame;
};
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
index bcdaf6d..85d7b74 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
@@ -250,7 +250,7 @@
}
/**
- * Name : cam_sensor_i2c_pkt_parser
+ * Name : cam_sensor_i2c_command_parser
* Description : Parse CSL CCI packet and apply register settings
* Parameters : s_ctrl input/output sub_device
* arg input cam_control
@@ -260,7 +260,7 @@
* WAIT + n x RND_WR with num_cmd_buf = 1. Do not exepect RD/WR
* with different cmd_type and op_code in one command buffer.
*/
-int cam_sensor_i2c_pkt_parser(struct i2c_settings_array *i2c_reg_settings,
+int cam_sensor_i2c_command_parser(struct i2c_settings_array *i2c_reg_settings,
struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers)
{
int16_t rc = 0, i = 0;
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
index 8a26369..d2079b0 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
@@ -34,7 +34,7 @@
int msm_camera_pinctrl_init
(struct msm_pinctrl_info *sensor_pctrl, struct device *dev);
-int cam_sensor_i2c_pkt_parser(struct i2c_settings_array *i2c_reg_settings,
+int cam_sensor_i2c_command_parser(struct i2c_settings_array *i2c_reg_settings,
struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers);
int32_t delete_request(struct i2c_settings_array *i2c_array);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index 68611b6..c042007 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -846,7 +846,8 @@
/* For decoder No need to sanity till LOAD_RESOURCES */
if (inst->session_type == MSM_VIDC_DECODER &&
- inst->state < MSM_VIDC_LOAD_RESOURCES_DONE) {
+ (inst->state < MSM_VIDC_LOAD_RESOURCES_DONE ||
+ inst->state >= MSM_VIDC_RELEASE_RESOURCES_DONE)) {
dprintk(VIDC_DBG,
"No need to verify buffer counts : %pK\n", inst);
return 0;
@@ -1499,6 +1500,16 @@
HAL_BUFFER_INPUT);
return -EINVAL;
}
+
+ if (inst->session_type == MSM_VIDC_DECODER &&
+ !(inst->flags & VIDC_THUMBNAIL) &&
+ inst->fmts[OUTPUT_PORT].fourcc ==
+ V4L2_PIX_FMT_VP9 &&
+ bufreq->buffer_count_min_host <
+ MIN_NUM_OUTPUT_BUFFERS_VP9)
+ bufreq->buffer_count_min_host =
+ MIN_NUM_OUTPUT_BUFFERS_VP9;
+
ctrl->val = bufreq->buffer_count_min_host;
break;
case V4L2_CID_MPEG_VIDC_VIDEO_TME_PAYLOAD_VERSION:
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
index f2f6d58..5183ddd 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
@@ -22,6 +22,19 @@
#define MSM_VIDC_MIN_UBWC_COMPRESSION_RATIO (1 << 16)
#define MSM_VIDC_MAX_UBWC_COMPRESSION_RATIO (5 << 16)
+static inline void msm_dcvs_print_dcvs_stats(struct clock_data *dcvs)
+{
+ dprintk(VIDC_PROF,
+ "DCVS: Load_Low %d, Load Norm %d, Load High %d\n",
+ dcvs->load_low,
+ dcvs->load_norm,
+ dcvs->load_high);
+
+ dprintk(VIDC_PROF,
+ "DCVS: min_threshold %d, max_threshold %d\n",
+ dcvs->min_threshold, dcvs->max_threshold);
+}
+
static inline unsigned long int get_ubwc_compression_ratio(
struct ubwc_cr_stats_info_type ubwc_stats_info)
{
@@ -509,6 +522,14 @@
unsigned long vpp_cycles = 0, vsp_cycles = 0;
u32 vpp_cycles_per_mb;
u32 mbs_per_second;
+ struct msm_vidc_core *core = NULL;
+ int i = 0;
+ struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
+ u64 rate = 0;
+ struct clock_data *dcvs = NULL;
+
+ core = inst->core;
+ dcvs = &inst->clk_data;
mbs_per_second = msm_comm_get_inst_load_per_core(inst,
LOAD_CALC_NO_QUIRKS);
@@ -544,6 +565,22 @@
freq = max(vpp_cycles, vsp_cycles);
+ dprintk(VIDC_DBG, "Update DCVS Load\n");
+ allowed_clks_tbl = core->resources.allowed_clks_tbl;
+ for (i = core->resources.allowed_clks_tbl_size - 1; i >= 0; i--) {
+ rate = allowed_clks_tbl[i].clock_rate;
+ if (rate >= freq)
+ break;
+ }
+
+ dcvs->load_norm = rate;
+ dcvs->load_low = i < (core->resources.allowed_clks_tbl_size - 1) ?
+ allowed_clks_tbl[i+1].clock_rate : dcvs->load_norm;
+ dcvs->load_high = i > 0 ? allowed_clks_tbl[i-1].clock_rate :
+ dcvs->load_norm;
+
+ msm_dcvs_print_dcvs_stats(dcvs);
+
dprintk(VIDC_PROF, "%s Inst %pK : Filled Len = %d Freq = %lu\n",
__func__, inst, filled_len, freq);
@@ -652,7 +689,9 @@
operating_rate = operating_rate >> 16;
- if ((curr_operating_rate + ops_left) >= operating_rate) {
+ if ((curr_operating_rate + ops_left) >= operating_rate ||
+ !msm_vidc_clock_scaling ||
+ inst->clk_data.buffer_counter < DCVS_FTB_WINDOW) {
dprintk(VIDC_DBG,
"Requestd operating rate is valid %u\n",
operating_rate);
@@ -796,19 +835,6 @@
return rc;
}
-static inline void msm_dcvs_print_dcvs_stats(struct clock_data *dcvs)
-{
- dprintk(VIDC_PROF,
- "DCVS: Load_Low %d, Load Norm %d, Load High %d\n",
- dcvs->load_low,
- dcvs->load_norm,
- dcvs->load_high);
-
- dprintk(VIDC_PROF,
- "DCVS: min_threshold %d, max_threshold %d\n",
- dcvs->min_threshold, dcvs->max_threshold);
-}
-
void msm_clock_data_reset(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
@@ -852,6 +878,10 @@
}
dcvs->max_threshold = output_buf_req->buffer_count_actual -
output_buf_req->buffer_count_min_host + 1;
+ /* Compensate for decode only frames */
+ if (inst->fmts[OUTPUT_PORT].fourcc == V4L2_PIX_FMT_VP9)
+ dcvs->max_threshold += 2;
+
dcvs->min_threshold =
msm_vidc_get_extra_buff_count(inst, dcvs->buffer_type);
} else {
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
index 37645fe..2e2dd13 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
@@ -45,6 +45,7 @@
#define MIN_SUPPORTED_HEIGHT 32
#define DEFAULT_FPS 15
#define MIN_NUM_OUTPUT_BUFFERS 1
+#define MIN_NUM_OUTPUT_BUFFERS_VP9 6
#define MIN_NUM_CAPTURE_BUFFERS 1
#define MAX_NUM_OUTPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
#define MAX_NUM_CAPTURE_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_platform.c b/drivers/media/platform/msm/vidc/msm_vidc_platform.c
index 56524ccd4..1818788 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_platform.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_platform.c
@@ -66,6 +66,7 @@
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 125, 675, 320),
+ CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4476e51..ae89ea9 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2701,8 +2701,8 @@
data->host_cookie = COOKIE_UNMAPPED;
- if (host->ops->pre_req)
- host->ops->pre_req(host, mrq);
+ if (host->ops->post_req)
+ host->ops->post_req(host, mrq);
}
static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
@@ -2714,6 +2714,9 @@
if (host->flags & SDHCI_REQ_USE_DMA)
sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
+
+ if (host->ops->pre_req)
+ host->ops->pre_req(host, mrq);
}
static inline bool sdhci_has_requests(struct sdhci_host *host)
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 57dc4a0..c857150 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -140,6 +140,7 @@
#define PERST_PROPAGATION_DELAY_US_MIN 1000
#define PERST_PROPAGATION_DELAY_US_MAX 1005
+#define SWITCH_DELAY_MAX 20
#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
#define REFCLK_STABILIZATION_DELAY_US_MAX 1005
#define LINK_UP_TIMEOUT_US_MIN 5000
@@ -492,6 +493,7 @@
uint32_t max_link_speed;
bool ext_ref_clk;
uint32_t ep_latency;
+ uint32_t switch_latency;
uint32_t wr_halt_size;
uint32_t slv_addr_space_size;
uint32_t cpl_timeout;
@@ -1112,6 +1114,8 @@
dev->n_fts);
PCIE_DBG_FS(dev, "ep_latency: %dms\n",
dev->ep_latency);
+ PCIE_DBG_FS(dev, "switch_latency: %dms\n",
+ dev->switch_latency);
PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",
dev->wr_halt_size);
PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",
@@ -3821,6 +3825,16 @@
goto link_fail;
}
+ if (dev->switch_latency) {
+ PCIE_DBG(dev, "switch_latency: %dms\n",
+ dev->switch_latency);
+ if (dev->switch_latency <= SWITCH_DELAY_MAX)
+ usleep_range(dev->switch_latency * 1000,
+ dev->switch_latency * 1000);
+ else
+ msleep(dev->switch_latency);
+ }
+
msm_pcie_config_controller(dev);
if (!dev->msi_gicm_addr)
@@ -5366,6 +5380,20 @@
PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n",
rc_idx, msm_pcie_dev[rc_idx].ep_latency);
+ msm_pcie_dev[rc_idx].switch_latency = 0;
+ ret = of_property_read_u32((&pdev->dev)->of_node,
+ "qcom,switch-latency",
+ &msm_pcie_dev[rc_idx].switch_latency);
+
+ if (ret)
+ PCIE_DBG(&msm_pcie_dev[rc_idx],
+ "RC%d: switch-latency does not exist.\n",
+ rc_idx);
+ else
+ PCIE_DBG(&msm_pcie_dev[rc_idx],
+ "RC%d: switch-latency: 0x%x.\n",
+ rc_idx, msm_pcie_dev[rc_idx].switch_latency);
+
msm_pcie_dev[rc_idx].wr_halt_size = 0;
ret = of_property_read_u32(pdev->dev.of_node,
"qcom,wr-halt-size",
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c b/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
index d582ba4..e77dcd9 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
@@ -1692,7 +1692,7 @@
{24, 517},
{26, 518},
{30, 519},
- {31, 639},
+ {31, 632},
{32, 521},
{34, 522},
{36, 523},
@@ -1705,7 +1705,7 @@
{44, 530},
{46, 531},
{48, 532},
- {49, 640},
+ {49, 633 },
{52, 534},
{53, 535},
{54, 536},
@@ -1730,7 +1730,7 @@
{85, 555},
{86, 556},
{88, 557},
- {89, 638},
+ {89, 631},
{91, 559},
{92, 560},
{95, 561},
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index c973d62..ee5bd19 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -1663,7 +1663,7 @@
{24, 517},
{26, 518},
{30, 519},
- {31, 639},
+ {31, 632},
{32, 521},
{34, 522},
{36, 523},
@@ -1676,7 +1676,7 @@
{44, 530},
{46, 531},
{48, 532},
- {49, 640},
+ {49, 633},
{52, 534},
{53, 535},
{54, 536},
@@ -1701,7 +1701,7 @@
{85, 555},
{86, 556},
{88, 557},
- {89, 638},
+ {89, 631},
{91, 559},
{92, 560},
{95, 561},
diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c
index 4a9232e..abb714d 100644
--- a/drivers/platform/msm/ipa/ipa_api.c
+++ b/drivers/platform/msm/ipa/ipa_api.c
@@ -3004,6 +3004,57 @@
}
EXPORT_SYMBOL(ipa_ntn_uc_dereg_rdyCB);
+/**
+ * ipa_conn_wdi3_pipes() - connect wdi3 pipes
+ */
+int ipa_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_conn_wdi3_pipes, in, out);
+
+ return ret;
+}
+
+/**
+ * ipa_disconn_wdi3_pipes() - disconnect wdi3 pipes
+ */
+int ipa_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_disconn_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
+
+/**
+ * ipa_enable_wdi3_pipes() - enable wdi3 pipes
+ */
+int ipa_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_enable_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
+
+/**
+ * ipa_disable_wdi3_pipes() - disable wdi3 pipes
+ */
+int ipa_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_disable_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
static const struct dev_pm_ops ipa_pm_ops = {
.suspend_noirq = ipa_ap_suspend,
diff --git a/drivers/platform/msm/ipa/ipa_api.h b/drivers/platform/msm/ipa/ipa_api.h
index 20471eb..7a48b68 100644
--- a/drivers/platform/msm/ipa/ipa_api.h
+++ b/drivers/platform/msm/ipa/ipa_api.h
@@ -12,6 +12,7 @@
#include <linux/ipa_mhi.h>
#include <linux/ipa_uc_offload.h>
+#include <linux/ipa_wdi3.h>
#include "ipa_common_i.h"
#ifndef _IPA_API_H_
@@ -385,6 +386,18 @@
void *user_data);
void (*ipa_ntn_uc_dereg_rdyCB)(void);
+
+ int (*ipa_conn_wdi3_pipes)(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+ int (*ipa_disconn_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
+
+ int (*ipa_enable_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
+
+ int (*ipa_disable_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
};
#ifdef CONFIG_IPA
diff --git a/drivers/platform/msm/ipa/ipa_clients/Makefile b/drivers/platform/msm/ipa/ipa_clients/Makefile
index 61625f5..738d88f 100644
--- a/drivers/platform/msm/ipa/ipa_clients/Makefile
+++ b/drivers/platform/msm/ipa/ipa_clients/Makefile
@@ -1,4 +1,4 @@
-obj-$(CONFIG_IPA3) += ipa_usb.o odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o
-obj-$(CONFIG_IPA) += odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o
+obj-$(CONFIG_IPA3) += ipa_usb.o odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o ipa_wdi3.o
+obj-$(CONFIG_IPA) += odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o ipa_wdi3.o
obj-$(CONFIG_ECM_IPA) += ecm_ipa.o
obj-$(CONFIG_RNDIS_IPA) += rndis_ipa.o
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c b/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c
new file mode 100644
index 0000000..f4c8763
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c
@@ -0,0 +1,526 @@
+/* Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ipa_wdi3.h>
+#include <linux/msm_ipa.h>
+#include <linux/string.h>
+#include "../ipa_common_i.h"
+
+#define OFFLOAD_DRV_NAME "ipa_wdi3"
+#define IPA_WDI3_DBG(fmt, args...) \
+ do { \
+ pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+#define IPA_WDI3_DBG_LOW(fmt, args...) \
+ do { \
+ pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+#define IPA_WDI3_ERR(fmt, args...) \
+ do { \
+ pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+struct ipa_wdi3_intf_info {
+ char netdev_name[IPA_RESOURCE_NAME_MAX];
+ u8 hdr_len;
+ u32 partial_hdr_hdl[IPA_IP_MAX];
+ struct list_head link;
+};
+
+struct ipa_wdi3_context {
+ struct list_head head_intf_list;
+ ipa_notify_cb notify;
+ void *priv;
+ struct completion wdi3_completion;
+ struct mutex lock;
+};
+
+static struct ipa_wdi3_context *ipa_wdi3_ctx;
+
+static int ipa_wdi3_commit_partial_hdr(
+ struct ipa_ioc_add_hdr *hdr,
+ const char *netdev_name,
+ struct ipa_wdi3_hdr_info *hdr_info)
+{
+ int i;
+
+ if (!hdr || !hdr_info || !netdev_name) {
+ IPA_WDI3_ERR("Invalid input\n");
+ return -EINVAL;
+ }
+
+ hdr->commit = 1;
+ hdr->num_hdrs = 2;
+
+ snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name),
+ "%s_ipv4", netdev_name);
+ snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name),
+ "%s_ipv6", netdev_name);
+ for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) {
+ hdr->hdr[i].hdr_len = hdr_info[i].hdr_len;
+ memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len);
+ hdr->hdr[i].type = hdr_info[i].hdr_type;
+ hdr->hdr[i].is_partial = 1;
+ hdr->hdr[i].is_eth2_ofst_valid = 1;
+ hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset;
+ }
+
+ if (ipa_add_hdr(hdr)) {
+ IPA_WDI3_ERR("fail to add partial headers\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+int ipa_wdi3_reg_intf(struct ipa_wdi3_reg_intf_in_params *in)
+{
+ struct ipa_ioc_add_hdr *hdr;
+ struct ipa_wdi3_intf_info *new_intf;
+ struct ipa_wdi3_intf_info *entry;
+ struct ipa_tx_intf tx;
+ struct ipa_rx_intf rx;
+ struct ipa_ioc_tx_intf_prop tx_prop[2];
+ struct ipa_ioc_rx_intf_prop rx_prop[2];
+ u32 len;
+ int ret = 0;
+
+ if (in == NULL) {
+ IPA_WDI3_ERR("invalid params in=%pK\n", in);
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ ipa_wdi3_ctx = kzalloc(sizeof(*ipa_wdi3_ctx), GFP_KERNEL);
+ if (ipa_wdi3_ctx == NULL) {
+ IPA_WDI3_ERR("fail to alloc wdi3 ctx\n");
+ return -ENOMEM;
+ }
+ mutex_init(&ipa_wdi3_ctx->lock);
+ INIT_LIST_HEAD(&ipa_wdi3_ctx->head_intf_list);
+ }
+
+ IPA_WDI3_DBG("register interface for netdev %s\n",
+ in->netdev_name);
+
+ mutex_lock(&ipa_wdi3_ctx->lock);
+ list_for_each_entry(entry, &ipa_wdi3_ctx->head_intf_list, link)
+ if (strcmp(entry->netdev_name, in->netdev_name) == 0) {
+ IPA_WDI3_DBG("intf was added before.\n");
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return 0;
+ }
+
+ IPA_WDI3_DBG("intf was not added before, proceed.\n");
+ new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL);
+ if (new_intf == NULL) {
+ IPA_WDI3_ERR("fail to alloc new intf\n");
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return -ENOMEM;
+ }
+
+ INIT_LIST_HEAD(&new_intf->link);
+ strlcpy(new_intf->netdev_name, in->netdev_name,
+ sizeof(new_intf->netdev_name));
+ new_intf->hdr_len = in->hdr_info[0].hdr_len;
+
+ /* add partial header */
+ len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add);
+ hdr = kzalloc(len, GFP_KERNEL);
+ if (hdr == NULL) {
+ IPA_WDI3_ERR("fail to alloc %d bytes\n", len);
+ ret = -EFAULT;
+ goto fail_alloc_hdr;
+ }
+
+ if (ipa_wdi3_commit_partial_hdr(hdr, in->netdev_name, in->hdr_info)) {
+ IPA_WDI3_ERR("fail to commit partial headers\n");
+ ret = -EFAULT;
+ goto fail_commit_hdr;
+ }
+
+ new_intf->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl;
+ new_intf->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl;
+ IPA_WDI3_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n",
+ hdr->hdr[IPA_IP_v4].hdr_hdl, hdr->hdr[IPA_IP_v6].hdr_hdl);
+
+ /* populate tx prop */
+ tx.num_props = 2;
+ tx.prop = tx_prop;
+
+ memset(tx_prop, 0, sizeof(tx_prop));
+ tx_prop[0].ip = IPA_IP_v4;
+ tx_prop[0].dst_pipe = IPA_CLIENT_WLAN1_CONS;
+ tx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type;
+ strlcpy(tx_prop[0].hdr_name, hdr->hdr[IPA_IP_v4].name,
+ sizeof(tx_prop[0].hdr_name));
+
+ tx_prop[1].ip = IPA_IP_v6;
+ tx_prop[1].dst_pipe = IPA_CLIENT_WLAN1_CONS;
+ tx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type;
+ strlcpy(tx_prop[1].hdr_name, hdr->hdr[IPA_IP_v6].name,
+ sizeof(tx_prop[1].hdr_name));
+
+ /* populate rx prop */
+ rx.num_props = 2;
+ rx.prop = rx_prop;
+
+ memset(rx_prop, 0, sizeof(rx_prop));
+ rx_prop[0].ip = IPA_IP_v4;
+ rx_prop[0].src_pipe = IPA_CLIENT_WLAN1_PROD;
+ rx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type;
+ if (in->is_meta_data_valid) {
+ rx_prop[0].attrib.attrib_mask |= IPA_FLT_META_DATA;
+ rx_prop[0].attrib.meta_data = in->meta_data;
+ rx_prop[0].attrib.meta_data_mask = in->meta_data_mask;
+ }
+
+ rx_prop[1].ip = IPA_IP_v6;
+ rx_prop[1].src_pipe = IPA_CLIENT_WLAN1_PROD;
+ rx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type;
+ if (in->is_meta_data_valid) {
+ rx_prop[1].attrib.attrib_mask |= IPA_FLT_META_DATA;
+ rx_prop[1].attrib.meta_data = in->meta_data;
+ rx_prop[1].attrib.meta_data_mask = in->meta_data_mask;
+ }
+
+ if (ipa_register_intf(in->netdev_name, &tx, &rx)) {
+ IPA_WDI3_ERR("fail to add interface prop\n");
+ ret = -EFAULT;
+ goto fail_commit_hdr;
+ }
+
+ list_add(&new_intf->link, &ipa_wdi3_ctx->head_intf_list);
+ init_completion(&ipa_wdi3_ctx->wdi3_completion);
+
+ kfree(hdr);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return 0;
+
+fail_commit_hdr:
+ kfree(hdr);
+fail_alloc_hdr:
+ kfree(new_intf);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_reg_intf);
+
+int ipa_wdi3_dereg_intf(const char *netdev_name)
+{
+ int len, ret = 0;
+ struct ipa_ioc_del_hdr *hdr = NULL;
+ struct ipa_wdi3_intf_info *entry;
+ struct ipa_wdi3_intf_info *next;
+
+ if (!netdev_name) {
+ IPA_WDI3_ERR("no netdev name.\n");
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ mutex_lock(&ipa_wdi3_ctx->lock);
+ list_for_each_entry_safe(entry, next, &ipa_wdi3_ctx->head_intf_list,
+ link)
+ if (strcmp(entry->netdev_name, netdev_name) == 0) {
+ len = sizeof(struct ipa_ioc_del_hdr) +
+ 2 * sizeof(struct ipa_hdr_del);
+ hdr = kzalloc(len, GFP_KERNEL);
+ if (hdr == NULL) {
+ IPA_WDI3_ERR("fail to alloc %d bytes\n", len);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return -ENOMEM;
+ }
+
+ hdr->commit = 1;
+ hdr->num_hdls = 2;
+ hdr->hdl[0].hdl = entry->partial_hdr_hdl[0];
+ hdr->hdl[1].hdl = entry->partial_hdr_hdl[1];
+ IPA_WDI3_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n",
+ hdr->hdl[0].hdl, hdr->hdl[1].hdl);
+
+ if (ipa_del_hdr(hdr)) {
+ IPA_WDI3_ERR("fail to delete partial header\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa_deregister_intf(entry->netdev_name)) {
+ IPA_WDI3_ERR("fail to del interface props\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+ list_del(&entry->link);
+ kfree(entry);
+
+ break;
+ }
+
+fail:
+ kfree(hdr);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_dereg_intf);
+
+static void ipa_wdi3_rm_notify(void *user_data, enum ipa_rm_event event,
+ unsigned long data)
+{
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("Invalid context\n");
+ return;
+ }
+
+ switch (event) {
+ case IPA_RM_RESOURCE_GRANTED:
+ complete_all(&ipa_wdi3_ctx->wdi3_completion);
+ break;
+
+ case IPA_RM_RESOURCE_RELEASED:
+ break;
+
+ default:
+ IPA_WDI3_ERR("Invalid RM Evt: %d", event);
+ break;
+ }
+}
+
+static int ipa_wdi3_cons_release(void)
+{
+ return 0;
+}
+
+static int ipa_wdi3_cons_request(void)
+{
+ int ret = 0;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized\n");
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ int ret = 0;
+ struct ipa_rm_create_params param;
+
+ if (!(in && out)) {
+ IPA_WDI3_ERR("empty parameters. in=%pK out=%pK\n", in, out);
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ ipa_wdi3_ctx = kzalloc(sizeof(*ipa_wdi3_ctx), GFP_KERNEL);
+ if (ipa_wdi3_ctx == NULL) {
+ IPA_WDI3_ERR("fail to alloc wdi3 ctx\n");
+ return -EFAULT;
+ }
+ mutex_init(&ipa_wdi3_ctx->lock);
+ INIT_LIST_HEAD(&ipa_wdi3_ctx->head_intf_list);
+ }
+ ipa_wdi3_ctx->notify = in->notify;
+ ipa_wdi3_ctx->priv = in->priv;
+
+ memset(¶m, 0, sizeof(param));
+ param.name = IPA_RM_RESOURCE_WLAN_PROD;
+ param.reg_params.user_data = ipa_wdi3_ctx;
+ param.reg_params.notify_cb = ipa_wdi3_rm_notify;
+ param.floor_voltage = IPA_VOLTAGE_SVS;
+ ret = ipa_rm_create_resource(¶m);
+ if (ret) {
+ IPA_WDI3_ERR("fail to create WLAN_PROD resource\n");
+ return -EFAULT;
+ }
+
+ memset(¶m, 0, sizeof(param));
+ param.name = IPA_RM_RESOURCE_WLAN_CONS;
+ param.request_resource = ipa_wdi3_cons_request;
+ param.release_resource = ipa_wdi3_cons_release;
+ ret = ipa_rm_create_resource(¶m);
+ if (ret) {
+ IPA_WDI3_ERR("fail to create WLAN_CONS resource\n");
+ goto fail_create_rm_cons;
+ }
+
+ if (ipa_rm_add_dependency(IPA_RM_RESOURCE_WLAN_PROD,
+ IPA_RM_RESOURCE_APPS_CONS)) {
+ IPA_WDI3_ERR("fail to add rm dependency\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa_conn_wdi3_pipes(in, out)) {
+ IPA_WDI3_ERR("fail to setup wdi3 pipes\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_CONS);
+fail_create_rm_cons:
+ ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_PROD);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_conn_pipes);
+
+int ipa_wdi3_disconn_pipes(void)
+{
+ int ipa_ep_idx_rx, ipa_ep_idx_tx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized\n");
+ return -EPERM;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_disconn_wdi3_pipes(ipa_ep_idx_rx, ipa_ep_idx_tx)) {
+ IPA_WDI3_ERR("fail to tear down wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_dependency(IPA_RM_RESOURCE_WLAN_PROD,
+ IPA_RM_RESOURCE_APPS_CONS)) {
+ IPA_WDI3_ERR("fail to delete rm dependency\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_PROD)) {
+ IPA_WDI3_ERR("fail to delete WLAN_PROD resource\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_CONS)) {
+ IPA_WDI3_ERR("fail to delete WLAN_CONS resource\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_disconn_pipes);
+
+int ipa_wdi3_enable_pipes(void)
+{
+ int ret;
+ int ipa_ep_idx_tx, ipa_ep_idx_rx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_enable_wdi3_pipes(ipa_ep_idx_tx, ipa_ep_idx_rx)) {
+ IPA_WDI3_ERR("fail to enable wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ ret = ipa_rm_request_resource(IPA_RM_RESOURCE_WLAN_PROD);
+ if (ret == -EINPROGRESS) {
+ if (wait_for_completion_timeout(&ipa_wdi3_ctx->wdi3_completion,
+ 10*HZ) == 0) {
+ IPA_WDI3_ERR("WLAN_PROD resource req time out\n");
+ return -EFAULT;
+ }
+ } else if (ret != 0) {
+ IPA_WDI3_ERR("fail to request resource\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_enable_pipes);
+
+int ipa_wdi3_disable_pipes(void)
+{
+ int ret;
+ int ipa_ep_idx_tx, ipa_ep_idx_rx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ ret = ipa_rm_release_resource(IPA_RM_RESOURCE_WLAN_PROD);
+ if (ret != 0) {
+ IPA_WDI3_ERR("fail to release resource\n");
+ return -EFAULT;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_disable_wdi3_pipes(ipa_ep_idx_tx, ipa_ep_idx_rx)) {
+ IPA_WDI3_ERR("fail to disable wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_disable_pipes);
+
+int ipa_wdi3_set_perf_profile(struct ipa_wdi3_perf_profile *profile)
+{
+ struct ipa_rm_perf_profile rm_profile;
+ enum ipa_rm_resource_name resource_name;
+
+ if (profile == NULL) {
+ IPA_WDI3_ERR("Invalid input\n");
+ return -EINVAL;
+ }
+
+ rm_profile.max_supported_bandwidth_mbps =
+ profile->max_supported_bw_mbps;
+
+ if (profile->client == IPA_CLIENT_WLAN1_PROD) {
+ resource_name = IPA_RM_RESOURCE_WLAN_PROD;
+ } else if (profile->client == IPA_CLIENT_WLAN1_CONS) {
+ resource_name = IPA_RM_RESOURCE_WLAN_CONS;
+ } else {
+ IPA_WDI3_ERR("not supported\n");
+ return -EINVAL;
+ }
+
+ if (ipa_rm_set_perf_profile(resource_name, &rm_profile)) {
+ IPA_WDI3_ERR("fail to setup rm perf profile\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_set_perf_profile);
diff --git a/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c b/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
index 1c47e69..2e87bd2 100644
--- a/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
@@ -2490,9 +2490,13 @@
(struct file *file,
const char __user *buf, size_t count, loff_t *ppos)
{
- struct rndis_ipa_dev *rndis_ipa_ctx = file->private_data;
+ struct rndis_ipa_dev *rndis_ipa_ctx = NULL;
int result;
+ if (file == NULL)
+ return -EFAULT;
+ rndis_ipa_ctx = file->private_data;
+
result = ipa_cfg_ep(rndis_ipa_ctx->usb_to_ipa_hdl, &ipa_to_usb_ep_cfg);
if (result) {
pr_err("failed to re-configure USB to IPA point\n");
diff --git a/drivers/platform/msm/ipa/ipa_common_i.h b/drivers/platform/msm/ipa/ipa_common_i.h
index a487bf4..fe8cbc0 100644
--- a/drivers/platform/msm/ipa/ipa_common_i.h
+++ b/drivers/platform/msm/ipa/ipa_common_i.h
@@ -18,6 +18,7 @@
#include <linux/ipc_logging.h>
#include <linux/ipa.h>
#include <linux/ipa_uc_offload.h>
+#include <linux/ipa_wdi3.h>
#define __FILENAME__ \
(strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__)
@@ -383,6 +384,16 @@
int ipa_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data),
void *user_data);
void ipa_ntn_uc_dereg_rdyCB(void);
+
+int ipa_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+int ipa_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
+int ipa_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
+int ipa_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
const char *ipa_get_version_string(enum ipa_hw_type ver);
int ipa_start_gsi_channel(u32 clnt_hdl);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
index f7b0864..918630f 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
@@ -23,10 +23,10 @@
static int ipa_generate_hw_rule_from_eq(
const struct ipa_ipfltri_rule_eq *attrib, u8 **buf)
{
- int num_offset_meq_32 = attrib->num_offset_meq_32;
- int num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
- int num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
- int num_offset_meq_128 = attrib->num_offset_meq_128;
+ uint8_t num_offset_meq_32 = attrib->num_offset_meq_32;
+ uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
+ uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
+ uint8_t num_offset_meq_128 = attrib->num_offset_meq_128;
int i;
if (attrib->tos_eq_present) {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
index d4e39d7..2f72d88 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
@@ -1374,6 +1374,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(lookup->name);
if (entry) {
lookup->hdl = entry->id;
@@ -1496,6 +1497,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ copy->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(copy->name);
if (entry) {
memcpy(copy->hdr, entry->hdr, entry->hdr_len);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
index e6954b7..e6048d1 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
@@ -234,6 +234,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, lookup->name)) {
lookup->num_tx_props = entry->num_tx_props;
@@ -269,6 +270,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ tx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, tx->name)) {
/* add the entry check */
@@ -310,6 +312,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ rx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, rx->name)) {
/* add the entry check */
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
index 2608e1d..825c538 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
@@ -512,6 +512,7 @@
struct ipa_install_fltr_rule_resp_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
if (req->filter_spec_list_len == 0) {
@@ -521,6 +522,38 @@
req->filter_spec_list_len);
}
+ if (req->filter_spec_list_len >= QMI_IPA_MAX_FILTERS_V01) {
+ IPAWANDBG(
+ "IPACM passes the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ }
+ for (i = 0; i < req->filter_spec_list_len; i++) {
+ if ((req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
mutex_lock(&ipa_qmi_lock);
if (ipa_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -673,6 +706,25 @@
req->filter_index_list[i].filter_handle,
req->filter_index_list[i].filter_index);
return -EINVAL;
+ } else if (req->install_status != IPA_QMI_RESULT_SUCCESS_V01) {
+ IPAWANERR(" UL filter rule for pipe %d install_status = %d\n",
+ req->source_pipe_index, req->install_status);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ } else if (((req->embedded_pipe_index_valid != true) ||
+ (req->embedded_call_mux_id_valid != true)) &&
+ ((req->embedded_pipe_index_valid != false) ||
+ (req->embedded_call_mux_id_valid != false))) {
+ IPAWANERR(
+ "IPACM passes embedded pipe and mux valid not valid\n");
+ return -EINVAL;
+ } else if (req->embedded_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
}
mutex_lock(&ipa_qmi_lock);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
index bada5cc..321cc89 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
@@ -863,6 +863,7 @@
mutex_lock(&ipa_ctx->lock);
/* check if this table exists */
+ in->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_rt_tbl(in->ip, in->name);
if (!entry) {
mutex_unlock(&ipa_ctx->lock);
@@ -1099,6 +1100,7 @@
mutex_lock(&ipa_ctx->lock);
for (i = 0; i < rules->num_rules; i++) {
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name,
&rules->rules[i].rule,
rules->rules[i].at_rear,
@@ -1368,6 +1370,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_rt_tbl(lookup->ip, lookup->name);
if (entry && entry->cookie == IPA_RT_TBL_COOKIE) {
if (entry->ref_cnt == U32_MAX) {
diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
index 39a1cc2..217f49c 100644
--- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
@@ -649,6 +649,8 @@
return -ENOMEM;
}
+ memset(req, 0, sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
+
param->commit = 1;
param->ep = IPA_CLIENT_APPS_LAN_WAN_PROD;
param->global = false;
@@ -1516,8 +1518,8 @@
/* Get driver name */
case RMNET_IOCTL_GET_DRIVER_NAME:
memcpy(&extend_ioctl_data.u.if_name,
- ipa_netdevs[0]->name,
- sizeof(IFNAMSIZ));
+ ipa_netdevs[0]->name, IFNAMSIZ);
+ extend_ioctl_data.u.if_name[IFNAMSIZ - 1] = '\0';
if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data,
&extend_ioctl_data,
sizeof(struct rmnet_ioctl_extended_s)))
@@ -1661,6 +1663,7 @@
sizeof(wan_msg->upstream_ifname);
strlcpy(wan_msg->upstream_ifname,
extend_ioctl_data.u.if_name, len);
+ wan_msg->upstream_ifname[len - 1] = '\0';
memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
msg_meta.msg_type = WAN_XLAT_CONNECT;
msg_meta.msg_len = sizeof(struct ipa_wan_msg);
diff --git a/drivers/platform/msm/ipa/ipa_v3/Makefile b/drivers/platform/msm/ipa/ipa_v3/Makefile
index 5db2545..ae4dccf 100644
--- a/drivers/platform/msm/ipa/ipa_v3/Makefile
+++ b/drivers/platform/msm/ipa/ipa_v3/Makefile
@@ -4,6 +4,6 @@
ipat-y := ipa.o ipa_debugfs.o ipa_hdr.o ipa_flt.o ipa_rt.o ipa_dp.o ipa_client.o \
ipa_utils.o ipa_nat.o ipa_intf.o teth_bridge.o ipa_interrupts.o \
ipa_uc.o ipa_uc_wdi.o ipa_dma.o ipa_uc_mhi.o ipa_mhi.o ipa_uc_ntn.o \
- ipa_hw_stats.o ipa_pm.o
+ ipa_hw_stats.o ipa_pm.o ipa_wdi3_i.o
obj-$(CONFIG_RMNET_IPA3) += rmnet_ipa.o ipa_qmi_service_v01.o ipa_qmi_service.o rmnet_ipa_fd_ioctl.o
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index 180d03eb..a40d038 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -4446,6 +4446,9 @@
return -EFAULT;
}
+ if (count > 0)
+ dbg_buff[count - 1] = '\0';
+
/* Prevent consequent calls from trying to load the FW again. */
if (ipa3_is_ready())
return count;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
index cc29f8f..34624c0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
@@ -1133,6 +1133,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(lookup->name);
if (entry) {
lookup->hdl = entry->id;
@@ -1255,6 +1256,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ copy->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(copy->name);
if (entry) {
memcpy(copy->hdr, entry->hdr, entry->hdr_len);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index a74c924..fb3c3a0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -1832,6 +1832,11 @@
int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
int ipa3_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv);
void ipa3_ntn_uc_dereg_rdyCB(void);
+int ipa3_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
/*
* To retrieve doorbell physical address of
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c b/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
index 2bd7b79..4ada018 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
@@ -225,6 +225,7 @@
return result;
}
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(lookup->name, IPA_RESOURCE_NAME_MAX) ==
IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", lookup->name);
@@ -267,6 +268,7 @@
return result;
}
+ tx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(tx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", tx->name);
return result;
@@ -314,6 +316,7 @@
return result;
}
+ rx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(rx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", rx->name);
return result;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
index fbaa4ae..e3a3821 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
@@ -603,15 +603,49 @@
struct ipa_install_fltr_rule_resp_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
- if (req->filter_spec_ex_list_len == 0) {
+ if (req->filter_spec_list_len == 0) {
IPAWANDBG("IPACM pass zero rules to Q6\n");
} else {
IPAWANDBG("IPACM pass %u rules to Q6\n",
req->filter_spec_ex_list_len);
}
+ if (req->filter_spec_list_len >= QMI_IPA_MAX_FILTERS_V01) {
+ IPAWANDBG(
+ "IPACM passes the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ }
+ for (i = 0; i < req->filter_spec_list_len; i++) {
+ if ((req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
+
mutex_lock(&ipa3_qmi_lock);
if (ipa3_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -653,6 +687,7 @@
struct ipa_install_fltr_rule_resp_ex_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
if (req->filter_spec_ex_list_len == 0) {
@@ -662,6 +697,34 @@
req->filter_spec_ex_list_len);
}
+ if (req->filter_spec_ex_list_len >= QMI_IPA_MAX_FILTERS_EX_V01) {
+ IPAWANDBG(
+ "IPACM pass the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < req->filter_spec_ex_list_len-1; i++) {
+ if ((req->filter_spec_ex_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_ex_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_ex_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_ex_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_ex_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_ex_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
mutex_lock(&ipa3_qmi_lock);
if (ipa3_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -805,6 +868,30 @@
req->source_pipe_index,
req->rule_id_len);
return -EINVAL;
+ } else if (req->install_status != IPA_QMI_RESULT_SUCCESS_V01) {
+ IPAWANERR(" UL filter rule for pipe %d install_status = %d\n",
+ req->source_pipe_index, req->install_status);
+ return -EINVAL;
+ } else if (req->rule_id_valid != 1) {
+ IPAWANERR(" UL filter rule for pipe %d rule_id_valid = %d\n",
+ req->source_pipe_index, req->rule_id_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ } else if (((req->embedded_pipe_index_valid != true) ||
+ (req->embedded_call_mux_id_valid != true)) &&
+ ((req->embedded_pipe_index_valid != false) ||
+ (req->embedded_call_mux_id_valid != false))) {
+ IPAWANERR(
+ "IPACM passes embedded pipe and mux valid not valid\n");
+ return -EINVAL;
+ } else if (req->embedded_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
}
if (req->source_pipe_index == -1) {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
index 8bd7d30..8d7b107 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
@@ -732,6 +732,7 @@
}
mutex_lock(&ipa3_ctx->lock);
+ in->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
/* check if this table exists */
entry = __ipa3_find_rt_tbl(in->ip, in->name);
if (!entry) {
@@ -1081,6 +1082,7 @@
mutex_lock(&ipa3_ctx->lock);
for (i = 0; i < rules->num_rules; i++) {
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name,
&rules->rules[i].rule,
rules->rules[i].at_rear,
@@ -1126,7 +1128,7 @@
}
mutex_lock(&ipa3_ctx->lock);
-
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
tbl = __ipa3_find_rt_tbl(rules->ip, rules->rt_tbl_name);
if (tbl == NULL || (tbl->cookie != IPA_RT_TBL_COOKIE)) {
IPAERR_RL("failed finding rt tbl name = %s\n",
@@ -1456,6 +1458,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa3_find_rt_tbl(lookup->ip, lookup->name);
if (entry && entry->cookie == IPA_RT_TBL_COOKIE) {
if (entry->ref_cnt == U32_MAX) {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
index 44afb28..8d415a1 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
@@ -26,6 +26,9 @@
#define IPA_NTN_TX_DIR 1
#define IPA_NTN_RX_DIR 2
+#define IPA_WDI3_TX_DIR 1
+#define IPA_WDI3_RX_DIR 2
+
/**
* @brief Enum value determined based on the feature it
* corresponds to
@@ -48,9 +51,9 @@
* @IPA_HW_FEATURE_MHI : Feature related to MHI operation in IPA HW
* @IPA_HW_FEATURE_POWER_COLLAPSE: Feature related to IPA Power collapse
* @IPA_HW_FEATURE_WDI : Feature related to WDI operation in IPA HW
- * @IPA_HW_FEATURE_ZIP: Feature related to CMP/DCMP operation in IPA HW
* @IPA_HW_FEATURE_NTN : Feature related to NTN operation in IPA HW
* @IPA_HW_FEATURE_OFFLOAD : Feature related to NTN operation in IPA HW
+ * @IPA_HW_FEATURE_WDI3 : Feature related to WDI operation in IPA HW
*/
enum ipa3_hw_features {
IPA_HW_FEATURE_COMMON = 0x0,
@@ -59,7 +62,8 @@
IPA_HW_FEATURE_WDI = 0x3,
IPA_HW_FEATURE_ZIP = 0x4,
IPA_HW_FEATURE_NTN = 0x5,
- IPA_HW_FEATURE_OFFLOAD = 0x6,
+ IPA_HW_FEATURE_OFFLOAD = 0x6,
+ IPA_HW_FEATURE_WDI3 = 0x7,
IPA_HW_FEATURE_MAX = IPA_HW_NUM_FEATURES
};
@@ -343,6 +347,33 @@
} __packed;
+struct IpaHwWdi3SetUpCmdData_t {
+ u32 transfer_ring_base_pa;
+ u32 transfer_ring_base_pa_hi;
+
+ u32 transfer_ring_size;
+
+ u32 transfer_ring_doorbell_pa;
+ u32 transfer_ring_doorbell_pa_hi;
+
+ u32 event_ring_base_pa;
+ u32 event_ring_base_pa_hi;
+
+ u32 event_ring_size;
+
+ u32 event_ring_doorbell_pa;
+ u32 event_ring_doorbell_pa_hi;
+
+ u16 num_pkt_buffers;
+ u8 ipa_pipe_number;
+ u8 dir;
+
+ u16 pkt_offset;
+ u16 reserved0;
+
+ u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE];
+} __packed;
+
/**
* struct Ipa3HwNtnCommonChCmdData_t - Structure holding the
* parameters for Ntn Tear down command data params
@@ -357,6 +388,13 @@
uint32_t raw32b;
} __packed;
+union IpaHwWdi3CommonChCmdData_t {
+ struct IpaHwWdi3CommonChCmdParams_t {
+ u32 ipa_pipe_number :8;
+ u32 reserved :24;
+ } __packed params;
+ u32 raw32b;
+} __packed;
/**
* struct Ipa3HwNTNErrorEventData_t - Structure holding the
@@ -447,13 +485,30 @@
* the offload commands from CPU
* @IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP : Command to set up
* Offload protocol's Tx/Rx Path
- * @IPA_CPU_2_HW_CMD_OFFLOAD_RX_SET_UP : Command to tear down
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN : Command to tear down
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE : Command to enable
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE : Command to disable
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND : Command to suspend
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_RESUME : Command to resume
* Offload protocol's Tx/ Rx Path
*/
enum ipa_cpu_2_hw_offload_commands {
IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 1),
- IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 2),
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 3),
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 4),
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 5),
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 6),
};
@@ -523,6 +578,7 @@
*/
union IpaHwSetUpCmd {
struct Ipa3HwNtnSetUpCmdData_t NtnSetupCh_params;
+ struct IpaHwWdi3SetUpCmdData_t Wdi3SetupCh_params;
} __packed;
/**
@@ -553,6 +609,7 @@
*/
union IpaHwCommonChCmd {
union Ipa3HwNtnCommonChCmdData_t NtnCommonCh_params;
+ union IpaHwWdi3CommonChCmdData_t Wdi3CommonCh_params;
} __packed;
struct IpaHwOffloadCommonChCmdData_t {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index f717264..ae05880 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -4497,6 +4497,10 @@
api_ctrl->ipa_get_pdev = ipa3_get_pdev;
api_ctrl->ipa_ntn_uc_reg_rdyCB = ipa3_ntn_uc_reg_rdyCB;
api_ctrl->ipa_ntn_uc_dereg_rdyCB = ipa3_ntn_uc_dereg_rdyCB;
+ api_ctrl->ipa_conn_wdi3_pipes = ipa3_conn_wdi3_pipes;
+ api_ctrl->ipa_disconn_wdi3_pipes = ipa3_disconn_wdi3_pipes;
+ api_ctrl->ipa_enable_wdi3_pipes = ipa3_enable_wdi3_pipes;
+ api_ctrl->ipa_disable_wdi3_pipes = ipa3_disable_wdi3_pipes;
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c
new file mode 100644
index 0000000..7801745
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c
@@ -0,0 +1,407 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipa_i.h"
+#include <linux/ipa_wdi3.h>
+
+#define IPA_HW_WDI3_RX_MBOX_START_INDEX 48
+#define IPA_HW_WDI3_TX_MBOX_START_INDEX 50
+
+static int ipa3_send_wdi3_setup_pipe_cmd(
+ struct ipa_wdi3_setup_info *info, u8 dir)
+{
+ int ipa_ep_idx;
+ int result = 0;
+ struct ipa_mem_buffer cmd;
+ struct IpaHwWdi3SetUpCmdData_t *wdi3_params;
+ struct IpaHwOffloadSetUpCmdData_t *cmd_data;
+
+ if (info == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx = ipa_get_ep_mapping(info->client);
+ if (ipa_ep_idx == -1) {
+ IPAERR("fail to get ep idx.\n");
+ return -EFAULT;
+ }
+
+ IPADBG("client=%d ep=%d\n", info->client, ipa_ep_idx);
+ IPADBG("ring_base_pa = 0x%pad\n", &info->transfer_ring_base_pa);
+ IPADBG("ring_size = %hu\n", info->transfer_ring_size);
+ IPADBG("ring_db_pa = 0x%pad\n", &info->transfer_ring_doorbell_pa);
+ IPADBG("evt_ring_base_pa = 0x%pad\n", &info->event_ring_base_pa);
+ IPADBG("evt_ring_size = %hu\n", info->event_ring_size);
+ IPADBG("evt_ring_db_pa = 0x%pad\n", &info->event_ring_doorbell_pa);
+ IPADBG("num_pkt_buffers = %hu\n", info->num_pkt_buffers);
+ IPADBG("pkt_offset = %d\n", info->pkt_offset);
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+
+ cmd_data = (struct IpaHwOffloadSetUpCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3_params = &cmd_data->SetupCh_params.Wdi3SetupCh_params;
+ wdi3_params->transfer_ring_base_pa = (u32)info->transfer_ring_base_pa;
+ wdi3_params->transfer_ring_base_pa_hi =
+ (u32)((u64)info->transfer_ring_base_pa >> 32);
+ wdi3_params->transfer_ring_size = info->transfer_ring_size;
+ wdi3_params->transfer_ring_doorbell_pa =
+ (u32)info->transfer_ring_doorbell_pa;
+ wdi3_params->transfer_ring_doorbell_pa_hi =
+ (u32)((u64)info->transfer_ring_doorbell_pa >> 32);
+ wdi3_params->event_ring_base_pa = (u32)info->event_ring_base_pa;
+ wdi3_params->event_ring_base_pa_hi =
+ (u32)((u64)info->event_ring_base_pa >> 32);
+ wdi3_params->event_ring_size = info->event_ring_size;
+ wdi3_params->event_ring_doorbell_pa =
+ (u32)info->event_ring_doorbell_pa;
+ wdi3_params->event_ring_doorbell_pa_hi =
+ (u32)((u64)info->event_ring_doorbell_pa >> 32);
+ wdi3_params->num_pkt_buffers = info->num_pkt_buffers;
+ wdi3_params->ipa_pipe_number = ipa_ep_idx;
+ wdi3_params->dir = dir;
+ wdi3_params->pkt_offset = info->pkt_offset;
+ memcpy(wdi3_params->desc_format_template, info->desc_format_template,
+ sizeof(wdi3_params->desc_format_template));
+
+ result = ipa3_uc_send_cmd((u32)(cmd.phys_base),
+ IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ IPAERR("uc setup channel cmd failed: %d\n", result);
+ result = -EFAULT;
+ }
+
+ dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ return result;
+}
+
+int ipa3_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ struct ipa3_ep_context *ep_rx;
+ struct ipa3_ep_context *ep_tx;
+ int ipa_ep_idx_rx;
+ int ipa_ep_idx_tx;
+ int result = 0;
+
+ if (in == NULL || out == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(in->rx.client);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(in->tx.client);
+ if (ipa_ep_idx_rx == -1 || ipa_ep_idx_tx == -1) {
+ IPAERR("fail to alloc EP.\n");
+ return -EFAULT;
+ }
+ if (ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES ||
+ ipa_ep_idx_tx >= IPA3_MAX_NUM_PIPES) {
+ IPAERR("ep out of range.\n");
+ return -EFAULT;
+ }
+
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+
+ if (ep_rx->valid || ep_tx->valid) {
+ IPAERR("EP already allocated.\n");
+ return -EFAULT;
+ }
+
+ memset(ep_rx, 0, offsetof(struct ipa3_ep_context, sys));
+ memset(ep_tx, 0, offsetof(struct ipa3_ep_context, sys));
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* setup rx ep cfg */
+ ep_rx->valid = 1;
+ ep_rx->client = in->rx.client;
+ result = ipa3_disable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("disable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+ ep_rx->client_notify = in->notify;
+ ep_rx->priv = in->priv;
+
+ memcpy(&ep_rx->cfg, &in->rx.ipa_ep_cfg, sizeof(ep_rx->cfg));
+
+ if (ipa3_cfg_ep(ipa_ep_idx_rx, &ep_rx->cfg)) {
+ IPAERR("fail to setup rx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa3_send_wdi3_setup_pipe_cmd(&in->rx, IPA_WDI3_RX_DIR)) {
+ IPAERR("fail to send cmd to uc for rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_install_dflt_flt_rules(ipa_ep_idx_rx);
+ out->rx_uc_db_pa = ipa3_ctx->ipa_wrapper_base +
+ ipahal_get_reg_base() +
+ ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n,
+ IPA_HW_WDI3_RX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_RX_MBOX_START_INDEX % 32);
+
+ IPADBG("client %d (ep: %d) connected\n", in->rx.client,
+ ipa_ep_idx_rx);
+
+ /* setup dl ep cfg */
+ ep_tx->valid = 1;
+ ep_tx->client = in->tx.client;
+ result = ipa3_disable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("disable data path failed res=%d ep=%d.\n", result,
+ ipa_ep_idx_tx);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ memcpy(&ep_tx->cfg, &in->tx.ipa_ep_cfg, sizeof(ep_tx->cfg));
+
+ if (ipa3_cfg_ep(ipa_ep_idx_tx, &ep_tx->cfg)) {
+ IPAERR("fail to setup tx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa3_send_wdi3_setup_pipe_cmd(&in->tx, IPA_WDI3_TX_DIR)) {
+ IPAERR("fail to send cmd to uc for tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ out->tx_uc_db_pa = ipa3_ctx->ipa_wrapper_base +
+ ipahal_get_reg_base() +
+ ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n,
+ IPA_HW_WDI3_TX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_TX_MBOX_START_INDEX % 32);
+ out->tx_uc_db_va = ioremap(out->tx_uc_db_pa, 4);
+ if (!out->tx_uc_db_va) {
+ IPAERR("fail to ioremap tx uc db\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPADBG("client %d (ep: %d) connected\n", in->tx.client,
+ ipa_ep_idx_tx);
+
+fail:
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+static int ipa3_send_wdi3_common_ch_cmd(int ipa_ep_idx, int command)
+{
+ struct ipa_mem_buffer cmd;
+ struct IpaHwOffloadCommonChCmdData_t *cmd_data;
+ union IpaHwWdi3CommonChCmdData_t *wdi3;
+ int result = 0;
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+ /* enable the TX pipe */
+ cmd_data = (struct IpaHwOffloadCommonChCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3 = &cmd_data->CommonCh_params.Wdi3CommonCh_params;
+ wdi3->params.ipa_pipe_number = ipa_ep_idx;
+ result = ipa3_uc_send_cmd((u32)(cmd.phys_base), command,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ if (ipa_ep_idx_tx < 0 || ipa_ep_idx_tx >= IPA3_MAX_NUM_PIPES ||
+ ipa_ep_idx_rx < 0 || ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES) {
+ IPAERR("invalid ipa ep index\n");
+ return -EINVAL;
+ }
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* tear down tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_disable_data_path(ipa_ep_idx_tx);
+ memset(ep_tx, 0, sizeof(struct ipa3_ep_context));
+ IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx);
+
+ /* tear down rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_disable_data_path(ipa_ep_idx_rx);
+ ipa3_delete_dflt_flt_rules(ipa_ep_idx_rx);
+ memset(ep_rx, 0, sizeof(struct ipa3_ep_context));
+ IPADBG("rx client (ep: %d) disconnected\n", ipa_ep_idx_rx);
+
+fail:
+ return result;
+}
+
+int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* enable tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* enable rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* enable data path */
+ result = ipa3_enable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ result = ipa3_enable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_tx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+
+fail:
+ return result;
+}
+
+int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* suspend tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* suspend rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ return result;
+}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
index acc72f0..d6dbc85 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
@@ -1500,10 +1500,10 @@
static int ipa_fltrt_generate_hw_rule_bdy_from_eq(
const struct ipa_ipfltri_rule_eq *attrib, u8 **buf)
{
- int num_offset_meq_32 = attrib->num_offset_meq_32;
- int num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
- int num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
- int num_offset_meq_128 = attrib->num_offset_meq_128;
+ uint8_t num_offset_meq_32 = attrib->num_offset_meq_32;
+ uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
+ uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
+ uint8_t num_offset_meq_128 = attrib->num_offset_meq_128;
int i;
int extra_bytes;
u8 *extra;
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index e5791b1..e945ec6 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -677,6 +677,8 @@
param->global = false;
param->num_rules = (uint8_t)1;
+ memset(req, 0, sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
+
for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) {
param->ip = ipa3_qmi_ctx->q6_ul_filter_rule[i].ip;
memset(&flt_rule_entry, 0, sizeof(struct ipa_flt_rule_add));
@@ -1639,8 +1641,8 @@
/* Get driver name */
case RMNET_IOCTL_GET_DRIVER_NAME:
memcpy(&extend_ioctl_data.u.if_name,
- IPA_NETDEV()->name,
- sizeof(IFNAMSIZ));
+ IPA_NETDEV()->name, IFNAMSIZ);
+ extend_ioctl_data.u.if_name[IFNAMSIZ - 1] = '\0';
if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data,
&extend_ioctl_data,
sizeof(struct rmnet_ioctl_extended_s)))
@@ -1731,6 +1733,7 @@
sizeof(wan_msg->upstream_ifname);
strlcpy(wan_msg->upstream_ifname,
extend_ioctl_data.u.if_name, len);
+ wan_msg->upstream_ifname[len-1] = '\0';
memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
msg_meta.msg_type = WAN_XLAT_CONNECT;
msg_meta.msg_len = sizeof(struct ipa_wan_msg);
diff --git a/drivers/platform/msm/ipa/test/ipa_ut_framework.c b/drivers/platform/msm/ipa/test/ipa_ut_framework.c
index 3bf9ac1..dfc8442 100644
--- a/drivers/platform/msm/ipa/test/ipa_ut_framework.c
+++ b/drivers/platform/msm/ipa/test/ipa_ut_framework.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -215,6 +215,10 @@
IPA_UT_DBG("Entry\n");
mutex_lock(&ipa_ut_ctx->lock);
+ if (file == NULL) {
+ rc = -EFAULT;
+ goto unlock_mutex;
+ }
suite = file->f_inode->i_private;
ipa_assert_on(!suite);
meta_type = (long)(file->private_data);
@@ -470,6 +474,10 @@
IPA_UT_DBG("Entry\n");
mutex_lock(&ipa_ut_ctx->lock);
+ if (file == NULL) {
+ rc = -EFAULT;
+ goto unlock_mutex;
+ }
test = file->f_inode->i_private;
ipa_assert_on(!test);
diff --git a/drivers/power/reset/msm-poweroff.c b/drivers/power/reset/msm-poweroff.c
index 8d023a8..c090b2a 100644
--- a/drivers/power/reset/msm-poweroff.c
+++ b/drivers/power/reset/msm-poweroff.c
@@ -533,7 +533,7 @@
pr_err("unable to map imem KASLR offset\n");
}
- if (kaslr_imem_addr && scm_is_secure_device()) {
+ if (kaslr_imem_addr) {
__raw_writel(0xdead4ead, kaslr_imem_addr);
__raw_writel(KASLR_OFFSET_BIT_MASK &
(kimage_vaddr - KIMAGE_VADDR), kaslr_imem_addr + 4);
@@ -603,7 +603,6 @@
if (scm_is_call_available(SCM_SVC_PWR, SCM_IO_DEASSERT_PS_HOLD) > 0)
scm_deassert_ps_hold_supported = true;
- download_mode = scm_is_secure_device();
set_dload_mode(download_mode);
return 0;
diff --git a/drivers/power/supply/qcom/fg-core.h b/drivers/power/supply/qcom/fg-core.h
index 3ca5def..7c10e63 100644
--- a/drivers/power/supply/qcom/fg-core.h
+++ b/drivers/power/supply/qcom/fg-core.h
@@ -426,6 +426,7 @@
int batt_id_ohms;
int ki_coeff_full_soc;
int charge_status;
+ int prev_charge_status;
int charge_done;
int charge_type;
int online_status;
diff --git a/drivers/power/supply/qcom/fg-util.c b/drivers/power/supply/qcom/fg-util.c
index fc60b26..622bfad 100644
--- a/drivers/power/supply/qcom/fg-util.c
+++ b/drivers/power/supply/qcom/fg-util.c
@@ -266,8 +266,7 @@
int fg_sram_write(struct fg_chip *chip, u16 address, u8 offset,
u8 *val, int len, int flags)
{
- int rc = 0;
- bool tried_again = false;
+ int rc = 0, tries = 0;
bool atomic_access = false;
if (!chip)
@@ -292,7 +291,7 @@
enable_irq(chip->irqs[SOC_UPDATE_IRQ].irq);
atomic_access = true;
}
-wait:
+
/*
* Atomic access mean waiting upon SOC_UPDATE interrupt from
* FG_ALG and do the transaction after that. This is to make
@@ -301,16 +300,20 @@
* FG cycle (~1.47 seconds).
*/
if (atomic_access) {
- /* Wait for SOC_UPDATE completion */
- rc = wait_for_completion_interruptible_timeout(
- &chip->soc_update,
- msecs_to_jiffies(SOC_UPDATE_WAIT_MS));
+ for (tries = 0; tries < 2; tries++) {
+ /* Wait for SOC_UPDATE completion */
+ rc = wait_for_completion_interruptible_timeout(
+ &chip->soc_update,
+ msecs_to_jiffies(SOC_UPDATE_WAIT_MS));
+ if (rc > 0) {
+ rc = 0;
+ break;
+ } else if (!rc) {
+ rc = -ETIMEDOUT;
+ }
+ }
- /* If we were interrupted wait again one more time. */
- if (rc == -ERESTARTSYS && !tried_again) {
- tried_again = true;
- goto wait;
- } else if (rc <= 0) {
+ if (rc < 0) {
pr_err("wait for soc_update timed out rc=%d\n", rc);
goto out;
}
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index fc34a8c9..48e42f2 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -562,6 +562,21 @@
return 0;
}
+#define BATT_SOC_32BIT GENMASK(31, 0)
+static int fg_get_charge_counter_shadow(struct fg_chip *chip, int *val)
+{
+ int rc, batt_soc;
+
+ rc = fg_get_sram_prop(chip, FG_SRAM_BATT_SOC, &batt_soc);
+ if (rc < 0) {
+ pr_err("Error in getting BATT_SOC, rc=%d\n", rc);
+ return rc;
+ }
+
+ *val = div_u64((u32)batt_soc * chip->cl.learned_cc_uah, BATT_SOC_32BIT);
+ return 0;
+}
+
static int fg_get_charge_counter(struct fg_chip *chip, int *val)
{
int rc, cc_soc;
@@ -1148,7 +1163,7 @@
enable_irq_wake(chip->irqs[BATT_MISSING_IRQ].irq);
} else {
disable_irq_wake(chip->irqs[BATT_MISSING_IRQ].irq);
- disable_irq(chip->irqs[BATT_MISSING_IRQ].irq);
+ disable_irq_nosync(chip->irqs[BATT_MISSING_IRQ].irq);
}
return 0;
@@ -1167,7 +1182,7 @@
enable_irq_wake(chip->irqs[BSOC_DELTA_IRQ].irq);
} else {
disable_irq_wake(chip->irqs[BSOC_DELTA_IRQ].irq);
- disable_irq(chip->irqs[BSOC_DELTA_IRQ].irq);
+ disable_irq_nosync(chip->irqs[BSOC_DELTA_IRQ].irq);
}
return 0;
@@ -1249,6 +1264,21 @@
return true;
}
+static int fg_prime_cc_soc_sw(struct fg_chip *chip, int cc_soc_sw)
+{
+ int rc;
+
+ rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
+ chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
+ chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ if (rc < 0)
+ pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
+ else
+ fg_dbg(chip, FG_STATUS, "cc_soc_sw: %x\n", cc_soc_sw);
+
+ return rc;
+}
+
static int fg_save_learned_cap_to_sram(struct fg_chip *chip)
{
int16_t cc_mah;
@@ -1434,7 +1464,6 @@
return 0;
}
-#define BATT_SOC_32BIT GENMASK(31, 0)
static int fg_cap_learning_begin(struct fg_chip *chip, u32 batt_soc)
{
int rc, cc_soc_sw, batt_soc_msb;
@@ -1453,16 +1482,13 @@
/* Prime cc_soc_sw with battery SOC when capacity learning begins */
cc_soc_sw = div64_s64((int64_t)batt_soc * CC_SOC_30BIT,
BATT_SOC_32BIT);
- rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
- chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
- chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
if (rc < 0) {
pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
goto out;
}
chip->cl.init_cc_soc_sw = cc_soc_sw;
- chip->cl.active = true;
fg_dbg(chip, FG_CAP_LEARN, "Capacity learning started @ battery SOC %d init_cc_soc_sw:%d\n",
batt_soc_msb, chip->cl.init_cc_soc_sw);
out:
@@ -1482,9 +1508,7 @@
/* Write a FULL value to cc_soc_sw */
cc_soc_sw = CC_SOC_30BIT;
- rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
- chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
- chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
if (rc < 0) {
pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
goto out;
@@ -1497,8 +1521,9 @@
static void fg_cap_learning_update(struct fg_chip *chip)
{
- int rc, batt_soc, batt_soc_msb;
+ int rc, batt_soc, batt_soc_msb, cc_soc_sw;
bool input_present = is_input_present(chip);
+ bool prime_cc = false;
mutex_lock(&chip->cl.lock);
@@ -1511,6 +1536,9 @@
goto out;
}
+ if (chip->charge_status == chip->prev_charge_status)
+ goto out;
+
rc = fg_get_sram_prop(chip, FG_SRAM_BATT_SOC, &batt_soc);
if (rc < 0) {
pr_err("Error in getting ACT_BATT_CAP, rc=%d\n", rc);
@@ -1526,8 +1554,12 @@
if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) {
rc = fg_cap_learning_begin(chip, batt_soc);
chip->cl.active = (rc == 0);
+ } else {
+ if ((chip->charge_status ==
+ POWER_SUPPLY_STATUS_DISCHARGING) ||
+ chip->charge_done)
+ prime_cc = true;
}
-
} else {
if (chip->charge_done) {
rc = fg_cap_learning_done(chip);
@@ -1545,6 +1577,7 @@
batt_soc_msb);
chip->cl.active = false;
chip->cl.init_cc_uah = 0;
+ prime_cc = true;
}
}
@@ -1561,10 +1594,29 @@
batt_soc_msb);
chip->cl.active = false;
chip->cl.init_cc_uah = 0;
+ prime_cc = true;
}
}
}
+ /*
+ * Prime CC_SOC_SW when the device is not charging or during charge
+ * termination when the capacity learning is not active.
+ */
+
+ if (prime_cc) {
+ if (chip->charge_done)
+ cc_soc_sw = CC_SOC_30BIT;
+ else
+ cc_soc_sw = div_u64((u32)batt_soc *
+ CC_SOC_30BIT, BATT_SOC_32BIT);
+
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
+ if (rc < 0)
+ pr_err("Error in writing cc_soc_sw, rc=%d\n",
+ rc);
+ }
+
out:
mutex_unlock(&chip->cl.lock);
}
@@ -1779,7 +1831,8 @@
fg_dbg(chip, FG_STATUS, "Terminated charging @ SOC%d\n",
msoc);
}
- } else if (msoc_raw <= recharge_soc && chip->charge_full) {
+ } else if ((msoc_raw <= recharge_soc || !chip->charge_done)
+ && chip->charge_full) {
if (chip->dt.linearize_soc) {
chip->delta_soc = FULL_CAPACITY - msoc;
@@ -2563,7 +2616,7 @@
}
fg_ttf_update(chip);
-
+ chip->prev_charge_status = chip->charge_status;
out:
fg_dbg(chip, FG_POWER_SUPPLY, "charge_status:%d charge_type:%d charge_done:%d\n",
chip->charge_status, chip->charge_type, chip->charge_done);
@@ -3555,6 +3608,9 @@
case POWER_SUPPLY_PROP_CHARGE_COUNTER:
rc = fg_get_charge_counter(chip, &pval->intval);
break;
+ case POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW:
+ rc = fg_get_charge_counter_shadow(chip, &pval->intval);
+ break;
case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG:
rc = fg_get_time_to_full(chip, &pval->intval);
break;
@@ -3765,6 +3821,7 @@
POWER_SUPPLY_PROP_CHARGE_NOW,
POWER_SUPPLY_PROP_CHARGE_FULL,
POWER_SUPPLY_PROP_CHARGE_COUNTER,
+ POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW,
POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
POWER_SUPPLY_PROP_SOC_REPORTING_READY,
@@ -5000,6 +5057,7 @@
chip->debug_mask = &fg_gen3_debug_mask;
chip->irqs = fg_irqs;
chip->charge_status = -EINVAL;
+ chip->prev_charge_status = -EINVAL;
chip->ki_coeff_full_soc = -EINVAL;
chip->online_status = -EINVAL;
chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
diff --git a/drivers/scsi/ufs/ufs_quirks.c b/drivers/scsi/ufs/ufs_quirks.c
index da2bfd5..a2b98fb 100644
--- a/drivers/scsi/ufs/ufs_quirks.c
+++ b/drivers/scsi/ufs/ufs_quirks.c
@@ -18,8 +18,6 @@
/* UFS cards deviations table */
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
- UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
- UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
UFS_DEVICE_NO_FASTAUTO),
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 8405537..0f87985 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -408,8 +408,8 @@
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
static struct devfreq_simple_ondemand_data ufshcd_ondemand_data = {
- .upthreshold = 35,
- .downdifferential = 30,
+ .upthreshold = 70,
+ .downdifferential = 65,
.simple_scaling = 1,
};
@@ -419,7 +419,7 @@
#endif
static struct devfreq_dev_profile ufs_devfreq_profile = {
- .polling_ms = 40,
+ .polling_ms = 60,
.target = ufshcd_devfreq_target,
.get_dev_status = ufshcd_devfreq_get_dev_status,
};
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index c94f915..62306bad 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -590,13 +590,6 @@
trusted apps, unloading them and marshalling buffers to the
trusted fingerprint app.
-config APSS_CORE_EA
- depends on CPU_FREQ && PM_OPP
- bool "Qualcomm Technology Inc specific power aware driver"
- help
- Platform specific power aware driver to provide power
- and temperature information to the scheduler.
-
if MSM_PM
menuconfig MSM_IDLE_STATS
bool "Collect idle statistics"
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4966c04..9a4e010 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -73,7 +73,6 @@
obj-$(CONFIG_MSM_QBT1000) += qbt1000.o
obj-$(CONFIG_MSM_EVENT_TIMER) += event_timer.o
obj-$(CONFIG_MSM_IDLE_STATS) += lpm-stats.o
-obj-$(CONFIG_APSS_CORE_EA) += msm-core.o debug_core.o
obj-$(CONFIG_QCOM_DCC_V2) += dcc_v2.o
obj-$(CONFIG_QTI_RPM_STATS_LOG) += rpm_stats.o
obj-$(CONFIG_QCOM_SMCINVOKE) += smcinvoke.o
diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c
index 9be0821..04c611c 100644
--- a/drivers/soc/qcom/icnss.c
+++ b/drivers/soc/qcom/icnss.c
@@ -73,6 +73,8 @@
#define ICNSS_THRESHOLD_LOW 3450000
#define ICNSS_THRESHOLD_GUARD 20000
+#define ICNSS_MAX_PROBE_CNT 2
+
#define icnss_ipc_log_string(_x...) do { \
if (icnss_ipc_log_context) \
ipc_log_string(icnss_ipc_log_context, _x); \
@@ -2103,7 +2105,8 @@
static int icnss_call_driver_probe(struct icnss_priv *priv)
{
- int ret;
+ int ret = 0;
+ int probe_cnt = 0;
if (!priv->ops || !priv->ops->probe)
return 0;
@@ -2115,10 +2118,15 @@
icnss_hw_power_on(priv);
- ret = priv->ops->probe(&priv->pdev->dev);
+ while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
+ ret = priv->ops->probe(&priv->pdev->dev);
+ probe_cnt++;
+ if (ret != -EPROBE_DEFER)
+ break;
+ }
if (ret < 0) {
- icnss_pr_err("Driver probe failed: %d, state: 0x%lx\n",
- ret, priv->state);
+ icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
+ ret, priv->state, probe_cnt);
goto out;
}
@@ -2226,6 +2234,7 @@
static int icnss_driver_event_register_driver(void *data)
{
int ret = 0;
+ int probe_cnt = 0;
if (penv->ops)
return -EEXIST;
@@ -2245,11 +2254,15 @@
if (ret)
goto out;
- ret = penv->ops->probe(&penv->pdev->dev);
-
+ while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
+ ret = penv->ops->probe(&penv->pdev->dev);
+ probe_cnt++;
+ if (ret != -EPROBE_DEFER)
+ break;
+ }
if (ret) {
- icnss_pr_err("Driver probe failed: %d, state: 0x%lx\n",
- ret, penv->state);
+ icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
+ ret, penv->state, probe_cnt);
goto power_off;
}
diff --git a/drivers/soc/qcom/llcc-sdm670.c b/drivers/soc/qcom/llcc-sdm670.c
index 68ad755..494b93b 100644
--- a/drivers/soc/qcom/llcc-sdm670.c
+++ b/drivers/soc/qcom/llcc-sdm670.c
@@ -57,13 +57,14 @@
}
static struct llcc_slice_config sdm670_data[] = {
- SCT_ENTRY("cpuss", 1, 1, 512, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 1),
- SCT_ENTRY("vidsc0", 2, 2, 64, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("vidsc1", 3, 3, 64, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("rotator", 4, 4, 384, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("modem", 8, 8, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("gpuhtw", 11, 11, 128, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("gpu", 12, 12, 384, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
+ SCT_ENTRY("cpuss", 1, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 1),
+ SCT_ENTRY("rotator", 4, 4, 384, 2, 1, 0x0, 0xE, 2, 0, 1, 1, 0),
+ SCT_ENTRY("voice", 5, 5, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("audio", 6, 6, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("modem", 8, 8, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("gpu", 12, 12, 384, 1, 1, 0x0, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("mmuhwt", 13, 13, 512, 1, 0, 0x0, 0x8, 0, 0, 1, 0, 1),
+ SCT_ENTRY("audiohw", 22, 22, 512, 1, 1, 0xF, 0x0, 0, 0, 1, 1, 0),
};
static int sdm670_qcom_llcc_probe(struct platform_device *pdev)
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
index bdcdf29..282f2ac 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
@@ -33,6 +33,7 @@
#define MAX_SAT_FIELD (NOC_QOS_SATn_SAT_BMSK >> NOC_QOS_SATn_SAT_SHFT)
#define MIN_SAT_FIELD 1
#define MIN_BW_FIELD 1
+#define QM_BASE 0x010B8000
#define MSM_BUS_FAB_MEM_NOC 6152
#define NOC_QOS_REG_BASE(b, o) ((b) + (o))
@@ -107,6 +108,16 @@
NOC_QOS_SATn_SAT_SHFT = 0x0,
};
+#define QM_CLn_TH_LVL_MUX_ADDR(b, o, n, d) \
+ (NOC_QOS_REG_BASE(b, o) + 0x8C0 + (d) * (n))
+enum qm_cl_id_th_lvl_mux_cfg {
+ QM_CLn_TH_LVL_SW_OVERRD_BMSK = 0x80000000,
+ QM_CLn_TH_LVL_SW_OVERRD_SHFT = 0x1F,
+ QM_CLn_TH_LVL_SW_BMSK = 0x00000007,
+ QM_CLn_TH_LVL_SW_SHFT = 0x0,
+};
+
+static void __iomem *qm_base;
static void __iomem *memnoc_qos_base;
static int noc_div(uint64_t *a, uint32_t b)
@@ -159,6 +170,18 @@
}
#define MAX_WS(bw, timebase) noc_ws((bw), MAX_SAT_FIELD, (timebase))
+static void noc_set_qm_th_lvl_cfg(void __iomem *base, uint32_t off,
+ uint32_t n, uint32_t delta,
+ uint32_t override_val, uint32_t override)
+{
+ writel_relaxed(((override << QM_CLn_TH_LVL_SW_OVERRD_SHFT) |
+ (override_val & QM_CLn_TH_LVL_SW_BMSK)),
+ QM_CLn_TH_LVL_MUX_ADDR(base, off, n, delta));
+
+ /* Ensure QM CFG is set before exiting */
+ wmb();
+}
+
static void noc_set_qos_dflt_prio(void __iomem *base, uint32_t qos_off,
uint32_t mport, uint32_t qos_delta,
uint32_t prio)
@@ -355,6 +378,16 @@
goto err_qos_init;
}
+ if (!qm_base) {
+ qm_base = ioremap_nocache(QM_BASE, 0x4000);
+ if (!qm_base) {
+ MSM_BUS_ERR("%s: Error remapping address 0x%zx",
+ __func__, (size_t)QM_BASE);
+ ret = -ENOMEM;
+ goto err_qos_init;
+ }
+ }
+
spin_lock_irqsave(&noc_lock, flags);
if (fabdev->node_info->id == MSM_BUS_FAB_MEM_NOC)
@@ -395,45 +428,17 @@
spin_lock_irqsave(&noc_lock, flags);
- if (!memnoc_qos_base) {
- MSM_BUS_ERR("Memnoc QoS Base address not found!");
+ if (!qm_base) {
+ MSM_BUS_ERR("QM CFG base address not found!");
goto noc_throttle_exit;
}
if (enable) {
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0x1B);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0x1B);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0x30);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0x30);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 10,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 11,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 2,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 3,
- 0x1000, 1);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 8, 0x4, 0x3, 0x1);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 9, 0x4, 0x3, 0x1);
} else {
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 8, 0x4, 0, 0);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 9, 0x4, 0, 0);
}
noc_throttle_exit:
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c
index ec3063e..a3eb551 100644
--- a/drivers/soc/qcom/pil-msa.c
+++ b/drivers/soc/qcom/pil-msa.c
@@ -124,13 +124,6 @@
int ret = 0;
u32 regval;
- if (drv->vreg) {
- ret = regulator_enable(drv->vreg);
- if (ret)
- dev_err(drv->desc.dev, "Failed to enable modem regulator(rc:%d)\n",
- ret);
- }
-
if (drv->cxrail_bhs) {
regval = readl_relaxed(drv->cxrail_bhs);
regval |= EXTERNAL_BHS_ON;
@@ -153,9 +146,6 @@
writel_relaxed(regval, drv->cxrail_bhs);
}
- if (drv->vreg)
- return regulator_disable(drv->vreg);
-
return 0;
}
@@ -456,7 +446,44 @@
return ret;
}
+ if (drv->vreg) {
+ ret = of_property_read_u32(pil->dev->of_node, "vdd_mss-uV",
+ &uv);
+ if (ret) {
+ dev_err(pil->dev,
+ "missing vdd_mss-uV property(rc:%d)\n", ret);
+ goto out;
+ }
+
+ ret = regulator_set_voltage(drv->vreg, uv,
+ INT_MAX);
+ if (ret) {
+ dev_err(pil->dev, "Failed to set vreg voltage(rc:%d)\n",
+ ret);
+ goto out;
+ }
+
+ ret = regulator_set_load(drv->vreg, 100000);
+ if (ret < 0) {
+ dev_err(pil->dev, "Failed to set vreg mode(rc:%d)\n",
+ ret);
+ goto out;
+ }
+ ret = regulator_enable(drv->vreg);
+ if (ret) {
+ dev_err(pil->dev, "Failed to enable vreg(rc:%d)\n",
+ ret);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ goto out;
+ }
+ }
+
ret = pil_q6v5_make_proxy_votes(pil);
+ if (ret && drv->vreg) {
+ regulator_disable(drv->vreg);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ }
+out:
if (ret) {
regulator_disable(drv->vreg_mx);
regulator_set_voltage(drv->vreg_mx, 0, INT_MAX);
@@ -472,6 +499,10 @@
pil_q6v5_remove_proxy_votes(pil);
regulator_disable(drv->vreg_mx);
regulator_set_voltage(drv->vreg_mx, 0, INT_MAX);
+ if (drv->vreg) {
+ regulator_disable(drv->vreg);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ }
}
static int pil_mss_mem_setup(struct pil_desc *pil,
diff --git a/drivers/soc/qcom/pil-msa.h b/drivers/soc/qcom/pil-msa.h
index 7a6a3cc..0f1e75b 100644
--- a/drivers/soc/qcom/pil-msa.h
+++ b/drivers/soc/qcom/pil-msa.h
@@ -17,8 +17,6 @@
#include "peripheral-loader.h"
-#define VDD_MSS_UV 1000000
-
struct modem_data {
struct q6v5_data *q6;
struct subsys_device *subsys;
diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c
index cf5f7e4..0477064 100644
--- a/drivers/soc/qcom/pil-q6v5-mss.c
+++ b/drivers/soc/qcom/pil-q6v5-mss.c
@@ -35,7 +35,6 @@
#include "pil-q6v5.h"
#include "pil-msa.h"
-#define MAX_VDD_MSS_UV 1150000
#define PROXY_TIMEOUT_MS 10000
#define MAX_SSR_REASON_LEN 256U
#define STOP_ACK_TIMEOUT_MS 1000
@@ -332,19 +331,6 @@
q6->vreg = devm_regulator_get(&pdev->dev, "vdd_mss");
if (IS_ERR(q6->vreg))
return PTR_ERR(q6->vreg);
-
- ret = regulator_set_voltage(q6->vreg, VDD_MSS_UV,
- MAX_VDD_MSS_UV);
- if (ret)
- dev_err(&pdev->dev, "Failed to set vreg voltage(rc:%d)\n",
- ret);
-
- ret = regulator_set_load(q6->vreg, 100000);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to set vreg mode(rc:%d)\n",
- ret);
- return ret;
- }
}
q6->vreg_mx = devm_regulator_get(&pdev->dev, "vdd_mx");
diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c
index af119f4..e7ed9f4 100644
--- a/drivers/tty/serial/msm_geni_serial.c
+++ b/drivers/tty/serial/msm_geni_serial.c
@@ -184,6 +184,7 @@
static void msm_geni_serial_power_off(struct uart_port *uport);
static int msm_geni_serial_poll_bit(struct uart_port *uport,
int offset, int bit_field, bool set);
+static void msm_geni_serial_stop_rx(struct uart_port *uport);
static atomic_t uart_line_id = ATOMIC_INIT(0);
@@ -541,6 +542,7 @@
msm_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
S_GENI_CMD_ABORT, false);
geni_write_reg_nolog(irq_clear, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ geni_write_reg(FORCE_DEFAULT, uport->membase, GENI_FORCE_DEFAULT_REG);
}
#ifdef CONFIG_CONSOLE_POLL
@@ -916,7 +918,8 @@
geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
if (geni_status & S_GENI_CMD_ACTIVE)
- msm_geni_serial_abort_rx(uport);
+ msm_geni_serial_stop_rx(uport);
+
geni_setup_s_cmd(uport->membase, UART_START_READ, 0);
if (port->xfer_mode == FIFO_MODE) {
@@ -938,7 +941,7 @@
if (ret) {
dev_err(uport->dev, "%s: RX Prep dma failed %d\n",
__func__, ret);
- msm_geni_serial_abort_rx(uport);
+ msm_geni_serial_stop_rx(uport);
return;
}
}
@@ -976,6 +979,7 @@
unsigned int geni_m_irq_en;
unsigned int geni_status;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ u32 irq_clear = S_CMD_DONE_EN;
if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
@@ -1007,7 +1011,17 @@
/* Possible stop rx is called multiple times. */
if (!(geni_status & S_GENI_CMD_ACTIVE))
return;
- msm_geni_serial_abort_rx(uport);
+ geni_cancel_s_cmd(uport->membase);
+ /*
+ * Ensure that the cancel goes through before polling for the
+ * cancel control bit.
+ */
+ mb();
+ msm_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
+ S_GENI_CMD_CANCEL, false);
+ geni_write_reg_nolog(irq_clear, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ if ((geni_status & S_GENI_CMD_ACTIVE))
+ msm_geni_serial_abort_rx(uport);
}
static int handle_rx_hs(struct uart_port *uport,
@@ -1586,7 +1600,6 @@
goto exit_startup;
}
- msm_geni_serial_start_rx(uport);
/*
* Ensure that all the port configuration writes complete
* before returning to the framework.
@@ -1707,11 +1720,17 @@
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
unsigned long clk_rate;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
- IPC_LOG_MSG(port->ipc_log_pwr,
- "%s Device suspended,vote clocks on.\n", __func__);
- return;
+ if (!uart_console(uport)) {
+ int ret = msm_geni_serial_power_on(uport);
+
+ if (ret) {
+ IPC_LOG_MSG(port->ipc_log_misc,
+ "%s: Failed to vote clock on:%d\n",
+ __func__, ret);
+ return;
+ }
}
+ msm_geni_serial_stop_rx(uport);
/* baud rate */
baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
port->cur_baud = baud;
@@ -1800,6 +1819,9 @@
IPC_LOG_MSG(port->ipc_log_misc, "BitsChar%d stop bit%d\n",
bits_per_char, stop_bit_len);
exit_set_termios:
+ msm_geni_serial_start_rx(uport);
+ if (!uart_console(uport))
+ msm_geni_serial_power_off(uport);
return;
}
diff --git a/drivers/uio/msm_sharedmem/msm_sharedmem.c b/drivers/uio/msm_sharedmem/msm_sharedmem.c
index b25f55a..8be3e36 100644
--- a/drivers/uio/msm_sharedmem/msm_sharedmem.c
+++ b/drivers/uio/msm_sharedmem/msm_sharedmem.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -107,10 +107,12 @@
struct resource *clnt_res = NULL;
u32 client_id = ((u32)~0U);
u32 shared_mem_size = 0;
+ u32 shared_mem_tot_sz = 0;
void *shared_mem = NULL;
phys_addr_t shared_mem_pyhsical = 0;
bool is_addr_dynamic = false;
struct sharemem_qmi_entry qmi_entry;
+ bool guard_memory = false;
/* Get the addresses from platform-data */
if (!pdev->dev.of_node) {
@@ -145,13 +147,30 @@
if (shared_mem_pyhsical == 0) {
is_addr_dynamic = true;
- shared_mem = dma_alloc_coherent(&pdev->dev, shared_mem_size,
+
+ /*
+ * If guard_memory is set, then the shared memory region
+ * will be guarded by SZ_4K at the start and at the end.
+ * This is needed to overcome the XPU limitation on few
+ * MSM HW, so as to make this memory not contiguous with
+ * other allocations that may possibly happen from other
+ * clients in the system.
+ */
+ guard_memory = of_property_read_bool(pdev->dev.of_node,
+ "qcom,guard-memory");
+
+ shared_mem_tot_sz = guard_memory ? shared_mem_size + SZ_8K :
+ shared_mem_size;
+
+ shared_mem = dma_alloc_coherent(&pdev->dev, shared_mem_tot_sz,
&shared_mem_pyhsical, GFP_KERNEL);
if (shared_mem == NULL) {
pr_err("Shared mem alloc client=%s, size=%u\n",
clnt_res->name, shared_mem_size);
return -ENOMEM;
}
+ if (guard_memory)
+ shared_mem_pyhsical += SZ_4K;
}
/* Set up the permissions for the shared ram that was allocated. */
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 088aa18..5ca987a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1171,6 +1171,10 @@
"snps,is-utmi-l1-suspend");
device_property_read_u8(dev, "snps,hird-threshold",
&hird_threshold);
+
+ device_property_read_u32(dev, "snps,xhci-imod-value",
+ &dwc->xhci_imod_value);
+
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5af75fd..63d0a3e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -952,6 +952,7 @@
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
* @create_reg_debugfs: create debugfs entry to allow dwc3 register dump
+ * @xhci_imod_value: imod value to use with xhci
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -1147,6 +1148,7 @@
int last_fifo_depth;
struct dwc3_gadget_events dbg_gadget_events;
bool create_reg_debugfs;
+ u32 xhci_imod_value;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index a68de4e..3f79aa4 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -52,14 +52,16 @@
return irq;
}
+#define NUMBER_OF_PROPS 4
int dwc3_host_init(struct dwc3 *dwc)
{
- struct property_entry props[3];
+ struct property_entry props[NUMBER_OF_PROPS];
struct platform_device *xhci;
int ret, irq;
struct resource *res;
struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
int prop_idx = 0;
+ struct property_entry imod_prop;
irq = dwc3_host_get_irq(dwc);
if (irq < 0)
@@ -101,6 +103,15 @@
if (dwc->usb3_lpm_capable)
props[prop_idx++].name = "usb3-lpm-capable";
+ if (dwc->xhci_imod_value) {
+ imod_prop.name = "xhci-imod-value";
+ imod_prop.length = sizeof(u32);
+ imod_prop.is_string = false;
+ imod_prop.is_array = false;
+ imod_prop.value.u32_data = dwc->xhci_imod_value;
+ props[prop_idx++] = imod_prop;
+ }
+
/**
* WORKAROUND: dwc3 revisions <=3.00a have a limitation
* where Port Disable command doesn't work.
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 14c0203..588546a 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -313,7 +313,7 @@
if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
- if (device_property_read_u32(sysdev, "snps,xhci-imod-value", &imod))
+ if (device_property_read_u32(&pdev->dev, "xhci-imod-value", &imod))
imod = 0;
if (device_property_read_u32(sysdev, "usb-core-id", &xhci->core_id))
diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c
index e8961b5..aabfb41 100644
--- a/drivers/usb/pd/policy_engine.c
+++ b/drivers/usb/pd/policy_engine.c
@@ -1038,6 +1038,16 @@
static void phy_shutdown(struct usbpd *pd)
{
usbpd_dbg(&pd->dev, "shutdown");
+
+ if (pd->vconn_enabled) {
+ regulator_disable(pd->vconn);
+ pd->vconn_enabled = false;
+ }
+
+ if (pd->vbus_enabled) {
+ regulator_disable(pd->vbus);
+ pd->vbus_enabled = false;
+ }
}
static enum hrtimer_restart pd_timeout(struct hrtimer *timer)
@@ -1211,14 +1221,13 @@
case PE_SRC_READY:
pd->in_explicit_contract = true;
- if (pd->current_dr == DR_DFP) {
- /* don't start USB host until after SVDM discovery */
- if (pd->vdm_state == VDM_NONE)
- usbpd_send_svdm(pd, USBPD_SID,
- USBPD_SVDM_DISCOVER_IDENTITY,
- SVDM_CMD_TYPE_INITIATOR, 0,
- NULL, 0);
- }
+
+ if (pd->vdm_tx)
+ kick_sm(pd, 0);
+ else if (pd->current_dr == DR_DFP && pd->vdm_state == VDM_NONE)
+ usbpd_send_svdm(pd, USBPD_SID,
+ USBPD_SVDM_DISCOVER_IDENTITY,
+ SVDM_CMD_TYPE_INITIATOR, 0, NULL, 0);
kobject_uevent(&pd->dev.kobj, KOBJ_CHANGE);
complete(&pd->is_ready);
@@ -1358,6 +1367,14 @@
case PE_SNK_READY:
pd->in_explicit_contract = true;
+
+ if (pd->vdm_tx)
+ kick_sm(pd, 0);
+ else if (pd->current_dr == DR_DFP && pd->vdm_state == VDM_NONE)
+ usbpd_send_svdm(pd, USBPD_SID,
+ USBPD_SVDM_DISCOVER_IDENTITY,
+ SVDM_CMD_TYPE_INITIATOR, 0, NULL, 0);
+
kobject_uevent(&pd->dev.kobj, KOBJ_CHANGE);
complete(&pd->is_ready);
dual_role_instance_changed(pd->dual_role);
@@ -2046,6 +2063,10 @@
switch (pd->current_state) {
case PE_UNKNOWN:
+ val.intval = 0;
+ power_supply_set_property(pd->usb_psy,
+ POWER_SUPPLY_PROP_PD_IN_HARD_RESET, &val);
+
if (pd->current_pr == PR_SINK) {
usbpd_set_state(pd, PE_SNK_STARTUP);
} else if (pd->current_pr == PR_SRC) {
@@ -2208,8 +2229,11 @@
case PE_SRC_TRANSITION_TO_DEFAULT:
if (pd->vconn_enabled)
regulator_disable(pd->vconn);
+ pd->vconn_enabled = false;
+
if (pd->vbus_enabled)
regulator_disable(pd->vbus);
+ pd->vbus_enabled = false;
if (pd->current_dr != DR_DFP) {
extcon_set_state_sync(pd->extcon, EXTCON_USB, 0);
@@ -2217,24 +2241,9 @@
pd_phy_update_roles(pd->current_dr, pd->current_pr);
}
- msleep(SRC_RECOVER_TIME);
-
- pd->vbus_enabled = false;
- enable_vbus(pd);
-
- if (pd->vconn_enabled) {
- ret = regulator_enable(pd->vconn);
- if (ret) {
- usbpd_err(&pd->dev, "Unable to enable vconn\n");
- pd->vconn_enabled = false;
- }
- }
-
- val.intval = 0;
- power_supply_set_property(pd->usb_psy,
- POWER_SUPPLY_PROP_PD_IN_HARD_RESET, &val);
-
- usbpd_set_state(pd, PE_SRC_STARTUP);
+ /* PE_UNKNOWN will turn on VBUS and go back to PE_SRC_STARTUP */
+ pd->current_state = PE_UNKNOWN;
+ kick_sm(pd, SRC_RECOVER_TIME);
break;
case PE_SRC_HARD_RESET:
diff --git a/drivers/usb/pd/qpnp-pdphy.c b/drivers/usb/pd/qpnp-pdphy.c
index 735774a..6395ca2 100644
--- a/drivers/usb/pd/qpnp-pdphy.c
+++ b/drivers/usb/pd/qpnp-pdphy.c
@@ -112,7 +112,6 @@
int tx_status;
u8 frame_filter_val;
bool in_test_data_mode;
- bool rx_busy;
enum data_role data_role;
enum power_role power_role;
@@ -490,7 +489,7 @@
}
ret = pdphy_reg_read(pdphy, &val, USB_PDPHY_RX_ACKNOWLEDGE, 1);
- if (ret || val || pdphy->rx_busy) {
+ if (ret || val) {
dev_err(pdphy->dev, "%s: RX message pending\n", __func__);
return -EBUSY;
}
@@ -668,15 +667,6 @@
BIST_MODE_MASK | BIST_ENABLE, bist_mode | BIST_ENABLE);
}
-static irqreturn_t pdphy_msg_rx_irq(int irq, void *data)
-{
- struct usb_pdphy *pdphy = data;
-
- pdphy->rx_busy = true;
-
- return IRQ_WAKE_THREAD;
-}
-
static irqreturn_t pdphy_msg_rx_irq_thread(int irq, void *data)
{
u8 size, rx_status, frame_type;
@@ -733,7 +723,6 @@
false);
pdphy->rx_bytes += size + 1;
done:
- pdphy->rx_busy = false;
return IRQ_HANDLED;
}
@@ -819,7 +808,7 @@
return ret;
ret = pdphy_request_irq(pdphy, pdev->dev.of_node,
- &pdphy->msg_rx_irq, "msg-rx", pdphy_msg_rx_irq,
+ &pdphy->msg_rx_irq, "msg-rx", NULL,
pdphy_msg_rx_irq_thread, (IRQF_TRIGGER_RISING | IRQF_ONESHOT));
if (ret < 0)
return ret;
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
index e20175d..b073c5f 100644
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ b/include/dt-bindings/msm/msm-bus-ids.h
@@ -89,6 +89,13 @@
#define MSM_BUS_BCM_ACV 7037
#define MSM_BUS_BCM_ALC 7038
#define MSM_BUS_BCM_QUP0 7039
+#define MSM_BUS_BCM_CE 7040
+#define MSM_BUS_BCM_PN0 7041
+#define MSM_BUS_BCM_PN1 7042
+#define MSM_BUS_BCM_PN2 7043
+#define MSM_BUS_BCM_PN3 7044
+#define MSM_BUS_BCM_PN4 7045
+#define MSM_BUS_BCM_PN5 7046
#define MSM_BUS_RSC_APPS 8000
#define MSM_BUS_RSC_DISP 8001
@@ -252,7 +259,10 @@
#define MSM_BUS_MASTER_CAMNOC_SF_UNCOMP 148
#define MSM_BUS_MASTER_GIC 149
#define MSM_BUS_MASTER_EMMC 150
-#define MSM_BUS_MASTER_MASTER_LAST 151
+#define MSM_BUS_MASTER_SPMI_FETCHER 151
+#define MSM_BUS_MASTER_ANOC_SNOC 152
+#define MSM_BUS_MASTER_ANOC_IPA 153
+#define MSM_BUS_MASTER_MASTER_LAST 154
#define MSM_BUS_MASTER_LLCC_DISPLAY 20000
#define MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001
@@ -593,7 +603,10 @@
#define MSM_BUS_SLAVE_MEM_NOC_SNOC 776
#define MSM_BUS_SLAVE_IPA_CORE 777
#define MSM_BUS_SLAVE_CAMNOC_UNCOMP 778
-#define MSM_BUS_SLAVE_LAST 779
+#define MSM_BUS_SLAVE_ANOC_SNOC 779
+#define MSM_BUS_SLAVE_ANOC_IPA 780
+#define MSM_BUS_SLAVE_EMAC_CFG 781
+#define MSM_BUS_SLAVE_LAST 782
#define MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512
#define MSM_BUS_SLAVE_LLCC_DISPLAY 20513
diff --git a/include/linux/ipa_wdi3.h b/include/linux/ipa_wdi3.h
new file mode 100644
index 0000000..aed8c59
--- /dev/null
+++ b/include/linux/ipa_wdi3.h
@@ -0,0 +1,254 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_WDI3_H_
+#define _IPA_WDI3_H_
+
+#include <linux/ipa.h>
+
+#define IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE 32
+#define IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE 8
+
+#define IPA_HW_WDI3_MAX_ER_DESC_SIZE \
+ (((IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) > \
+ (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE)) ? \
+ (IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) : \
+ (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE))
+
+/**
+ * struct ipa_wdi3_hdr_info - Header to install on IPA HW
+ *
+ * @hdr: header to install on IPA HW
+ * @hdr_len: length of header
+ * @dst_mac_addr_offset: destination mac address offset
+ * @hdr_type: layer two header type
+ */
+struct ipa_wdi3_hdr_info {
+ u8 *hdr;
+ u8 hdr_len;
+ u8 dst_mac_addr_offset;
+ enum ipa_hdr_l2_type hdr_type;
+};
+
+/**
+ * struct ipa_wdi3_reg_intf_in_params - parameters for uC offload
+ * interface registration
+ *
+ * @netdev_name: network interface name
+ * @hdr_info: header information
+ * @is_meta_data_valid: if meta data is valid
+ * @meta_data: meta data if any
+ * @meta_data_mask: meta data mask
+ */
+struct ipa_wdi3_reg_intf_in_params {
+ const char *netdev_name;
+ struct ipa_wdi3_hdr_info hdr_info[IPA_IP_MAX];
+ u8 is_meta_data_valid;
+ u32 meta_data;
+ u32 meta_data_mask;
+};
+
+/**
+ * struct ipa_wdi3_setup_info - WDI3 TX/Rx configuration
+ * @ipa_ep_cfg: ipa endpoint configuration
+ * @client: type of "client"
+ * @transfer_ring_base_pa: physical address of the base of the transfer ring
+ * @transfer_ring_size: size of the transfer ring
+ * @transfer_ring_doorbell_pa: physical address of the doorbell that
+ IPA uC will update the tailpointer of the transfer ring
+ * @event_ring_base_pa: physical address of the base of the event ring
+ * @event_ring_size: event ring size
+ * @event_ring_doorbell_pa: physical address of the doorbell that IPA uC
+ will update the headpointer of the event ring
+ * @num_pkt_buffers: Number of pkt buffers allocated. The size of the event
+ ring and the transfer ring has to be atleast ( num_pkt_buffers + 1)
+ * @pkt_offset: packet offset (wdi3 header length)
+ * @desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]: Holds a cached
+ template of the desc format
+ */
+struct ipa_wdi3_setup_info {
+ struct ipa_ep_cfg ipa_ep_cfg;
+ enum ipa_client_type client;
+ dma_addr_t transfer_ring_base_pa;
+ u32 transfer_ring_size;
+ dma_addr_t transfer_ring_doorbell_pa;
+
+ dma_addr_t event_ring_base_pa;
+ u32 event_ring_size;
+ dma_addr_t event_ring_doorbell_pa;
+ u16 num_pkt_buffers;
+
+ u16 pkt_offset;
+
+ u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE];
+};
+
+/**
+ * struct ipa_wdi3_conn_in_params - information provided by
+ * uC offload client
+ * @notify: client callback function
+ * @priv: client cookie
+ * @tx: parameters to connect TX pipe(from IPA to WLAN)
+ * @rx: parameters to connect RX pipe(from WLAN to IPA)
+ */
+struct ipa_wdi3_conn_in_params {
+ ipa_notify_cb notify;
+ void *priv;
+ struct ipa_wdi3_setup_info tx;
+ struct ipa_wdi3_setup_info rx;
+};
+
+/**
+ * struct ipa_wdi3_conn_out_params - information provided
+ * to WLAN driver
+ * @tx_uc_db_pa: physical address of IPA uC doorbell for TX
+ * @tx_uc_db_va: virtual address of IPA uC doorbell for TX
+ * @rx_uc_db_pa: physical address of IPA uC doorbell for RX
+ */
+struct ipa_wdi3_conn_out_params {
+ dma_addr_t tx_uc_db_pa;
+ void __iomem *tx_uc_db_va;
+ dma_addr_t rx_uc_db_pa;
+};
+
+/**
+ * struct ipa_wdi3_perf_profile - To set BandWidth profile
+ *
+ * @client: type of client
+ * @max_supported_bw_mbps: maximum bandwidth needed (in Mbps)
+ */
+struct ipa_wdi3_perf_profile {
+ enum ipa_client_type client;
+ u32 max_supported_bw_mbps;
+};
+
+#if defined CONFIG_IPA || defined CONFIG_IPA3
+
+/**
+ * ipa_wdi3_reg_intf - Client should call this function to
+ * init WDI3 IPA offload data path
+ *
+ * Note: Should not be called from atomic context and only
+ * after checking IPA readiness using ipa_register_ipa_ready_cb()
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_reg_intf(
+ struct ipa_wdi3_reg_intf_in_params *in);
+
+/**
+ * ipa_wdi3_dereg_intf - Client Driver should call this
+ * function to deregister before unload and after disconnect
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_dereg_intf(const char *netdev_name);
+
+/**
+ * ipa_wdi3_conn_pipes - Client should call this
+ * function to connect pipes
+ *
+ * @in: [in] input parameters from client
+ * @out: [out] output params to client
+ *
+ * Note: Should not be called from atomic context and only
+ * after checking IPA readiness using ipa_register_ipa_ready_cb()
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+/**
+ * ipa_wdi3_disconn_pipes() - Client should call this
+ * function to disconnect pipes
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_disconn_pipes(void);
+
+/**
+ * ipa_wdi3_enable_pipes() - Client should call this
+ * function to enable IPA offload data path
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_enable_pipes(void);
+
+/**
+ * ipa_wdi3_disable_pipes() - Client should call this
+ * function to disable IPA offload data path
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_disable_pipes(void);
+
+/**
+ * ipa_wdi3_set_perf_profile() - Client should call this function to
+ * set IPA clock bandwidth based on data rates
+ *
+ * @profile: [in] BandWidth profile to use
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_set_perf_profile(struct ipa_wdi3_perf_profile *profile);
+
+
+#else /* (CONFIG_IPA || CONFIG_IPA3) */
+
+static inline int ipa_wdi3_reg_intf(
+ struct ipa_wdi3_reg_intf_in_params *in)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_dereg_intf(const char *netdev_name)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_disconn_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_enable_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_disable_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_set_perf_profile(
+ struct ipa_wdi3_perf_profile *profile)
+{
+ return -EPERM;
+}
+
+#endif /* CONFIG_IPA3 */
+
+#endif /* _IPA_WDI3_H_ */
diff --git a/include/net/neighbour.h b/include/net/neighbour.h
index 8b68384..ddfb742 100644
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -62,6 +62,7 @@
NEIGH_VAR_GC_THRESH1,
NEIGH_VAR_GC_THRESH2,
NEIGH_VAR_GC_THRESH3,
+ NEIGH_VAR_PROBE,
NEIGH_VAR_MAX
};
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 8495824..b6fdf29 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -106,7 +106,7 @@
#endif
#define SNDRV_PCM_IOCTL1_RESET 0
-#define SNDRV_PCM_IOCTL1_INFO 1
+/* 1 is absent slot. */
#define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2
#define SNDRV_PCM_IOCTL1_GSTATE 3
#define SNDRV_PCM_IOCTL1_FIFO_SIZE 4
diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h
index 0765527..fcf84e3 100644
--- a/include/uapi/drm/msm_drm_pp.h
+++ b/include/uapi/drm/msm_drm_pp.h
@@ -69,7 +69,39 @@
__u32 val[PA_VLUT_SIZE];
};
-/* struct drm_msm_memcol - Memory color feature strucuture.
+#define PA_HSIC_HUE_ENABLE (1 << 0)
+#define PA_HSIC_SAT_ENABLE (1 << 1)
+#define PA_HSIC_VAL_ENABLE (1 << 2)
+#define PA_HSIC_CONT_ENABLE (1 << 3)
+/**
+ * struct drm_msm_pa_hsic - pa hsic feature structure
+ * @flags: flags for the feature customization, values can be:
+ * - PA_HSIC_HUE_ENABLE: Enable hue adjustment
+ * - PA_HSIC_SAT_ENABLE: Enable saturation adjustment
+ * - PA_HSIC_VAL_ENABLE: Enable value adjustment
+ * - PA_HSIC_CONT_ENABLE: Enable contrast adjustment
+ *
+ * @hue: hue setting
+ * @saturation: saturation setting
+ * @value: value setting
+ * @contrast: contrast setting
+ */
+#define DRM_MSM_PA_HSIC
+struct drm_msm_pa_hsic {
+ __u64 flags;
+ __u32 hue;
+ __u32 saturation;
+ __u32 value;
+ __u32 contrast;
+};
+
+#define MEMCOL_PROT_HUE (1 << 0)
+#define MEMCOL_PROT_SAT (1 << 1)
+#define MEMCOL_PROT_VAL (1 << 2)
+#define MEMCOL_PROT_CONT (1 << 3)
+#define MEMCOL_PROT_SIXZONE (1 << 4)
+#define MEMCOL_PROT_BLEND (1 << 5)
+/* struct drm_msm_memcol - Memory color feature structure.
* Skin, sky, foliage features are supported.
* @prot_flags: Bit mask for enabling protection feature.
* @color_adjust_p0: Adjustment curve.
@@ -96,6 +128,42 @@
__u32 val_region;
};
+#define DRM_MSM_SIXZONE
+#define SIXZONE_LUT_SIZE 384
+#define SIXZONE_HUE_ENABLE (1 << 0)
+#define SIXZONE_SAT_ENABLE (1 << 1)
+#define SIXZONE_VAL_ENABLE (1 << 2)
+/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure.
+ * @p0: Hue adjustment.
+ * @p1: Saturation/Value adjustment.
+ */
+struct drm_msm_sixzone_curve {
+ __u32 p1;
+ __u32 p0;
+};
+
+/* struct drm_msm_sixzone - Sixzone feature structure.
+ * @flags: for feature customization, values can be:
+ * - SIXZONE_HUE_ENABLE: Enable hue adjustment
+ * - SIXZONE_SAT_ENABLE: Enable saturation adjustment
+ * - SIXZONE_VAL_ENABLE: Enable value adjustment
+ * @threshold: threshold qualifier.
+ * @adjust_p0: Adjustment curve.
+ * @adjust_p1: Adjustment curve.
+ * @sat_hold: Saturation hold info.
+ * @val_hold: Value hold info.
+ * @curve: HSV adjustment curve lut.
+ */
+struct drm_msm_sixzone {
+ __u64 flags;
+ __u32 threshold;
+ __u32 adjust_p0;
+ __u32 adjust_p1;
+ __u32 sat_hold;
+ __u32 val_hold;
+ struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
+};
+
#define GAMUT_3D_MODE_17 1
#define GAMUT_3D_MODE_5 2
#define GAMUT_3D_MODE_13 3
diff --git a/kernel/locking/osq_lock.c b/kernel/locking/osq_lock.c
index 99b8d99..0befa20 100644
--- a/kernel/locking/osq_lock.c
+++ b/kernel/locking/osq_lock.c
@@ -106,6 +106,19 @@
prev = decode_cpu(old);
node->prev = prev;
+
+ /*
+ * osq_lock() unqueue
+ *
+ * node->prev = prev osq_wait_next()
+ * WMB MB
+ * prev->next = node next->prev = prev // unqueue-C
+ *
+ * Here 'node->prev' and 'next->prev' are the same variable and we need
+ * to ensure these stores happen in-order to avoid corrupting the list.
+ */
+ smp_wmb();
+
WRITE_ONCE(prev->next, node);
/*
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index f27d47f..bc55f3f 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -376,7 +376,7 @@
j_util = j_sg_cpu->util;
j_max = j_sg_cpu->max;
- if (j_util * max > j_max * util) {
+ if (j_util * max >= j_max * util) {
util = j_util;
max = j_max;
}
@@ -514,7 +514,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->hispeed_load);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->hispeed_load);
}
static ssize_t hispeed_load_store(struct gov_attr_set *attr_set,
@@ -534,7 +534,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->hispeed_freq);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->hispeed_freq);
}
static ssize_t hispeed_freq_store(struct gov_attr_set *attr_set,
@@ -566,7 +566,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->pl);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->pl);
}
static ssize_t pl_store(struct gov_attr_set *attr_set, const char *buf,
diff --git a/net/core/neighbour.c b/net/core/neighbour.c
index 227c249..62893eb 100644
--- a/net/core/neighbour.c
+++ b/net/core/neighbour.c
@@ -56,6 +56,7 @@
static void neigh_update_notify(struct neighbour *neigh);
static int pneigh_ifdown(struct neigh_table *tbl, struct net_device *dev);
+static unsigned int neigh_probe_enable;
#ifdef CONFIG_PROC_FS
static const struct file_operations neigh_stat_seq_fops;
#endif
@@ -1258,9 +1259,20 @@
{
struct neighbour *neigh = __neigh_lookup(tbl, saddr, dev,
lladdr || !dev->addr_len);
- if (neigh)
- neigh_update(neigh, lladdr, NUD_STALE,
- NEIGH_UPDATE_F_OVERRIDE);
+ if (neigh) {
+ if (neigh_probe_enable) {
+ if (!(neigh->nud_state == NUD_REACHABLE)) {
+ neigh_update(neigh, lladdr, NUD_STALE,
+ NEIGH_UPDATE_F_OVERRIDE);
+ write_lock(&neigh->lock);
+ neigh_probe(neigh);
+ neigh_update_notify(neigh);
+ }
+ } else {
+ neigh_update(neigh, lladdr, NUD_STALE,
+ NEIGH_UPDATE_F_OVERRIDE);
+ }
+ }
return neigh;
}
EXPORT_SYMBOL(neigh_event_ns);
@@ -3107,6 +3119,12 @@
.extra2 = &int_max,
.proc_handler = proc_dointvec_minmax,
},
+ [NEIGH_VAR_PROBE] = {
+ .procname = "neigh_probe",
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec,
+ },
{},
},
};
@@ -3142,6 +3160,7 @@
t->neigh_vars[NEIGH_VAR_GC_THRESH1].data = &tbl->gc_thresh1;
t->neigh_vars[NEIGH_VAR_GC_THRESH2].data = &tbl->gc_thresh2;
t->neigh_vars[NEIGH_VAR_GC_THRESH3].data = &tbl->gc_thresh3;
+ t->neigh_vars[NEIGH_VAR_PROBE].data = &neigh_probe_enable;
}
if (handler) {
diff --git a/net/netfilter/nf_nat_sip.c b/net/netfilter/nf_nat_sip.c
index 791fac4..2f2414e2 100644
--- a/net/netfilter/nf_nat_sip.c
+++ b/net/netfilter/nf_nat_sip.c
@@ -111,13 +111,26 @@
newaddr = ct->tuplehash[!dir].tuple.src.u3;
newport = ct_sip_info->forced_dport ? :
ct->tuplehash[!dir].tuple.src.u.udp.port;
+ } else if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.src.u3, addr) &&
+ ct->tuplehash[dir].tuple.src.u.udp.port != port) {
+ newaddr = ct->tuplehash[!dir].tuple.dst.u3;
+ newport = 0;
+ } else if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.dst.u3, addr) &&
+ ct->tuplehash[dir].tuple.dst.u.udp.port != port) {
+ newaddr = ct->tuplehash[!dir].tuple.src.u3;
+ newport = 0;
} else
return 1;
if (nf_inet_addr_cmp(&newaddr, addr) && newport == port)
return 1;
- buflen = sip_sprintf_addr_port(ct, buffer, &newaddr, ntohs(newport));
+ if (newport == 0)
+ buflen = sip_sprintf_addr(ct, buffer, &newaddr, false);
+ else
+ buflen = sip_sprintf_addr_port(ct, buffer, &newaddr,
+ ntohs(newport));
+
return mangle_packet(skb, protoff, dataoff, dptr, datalen,
matchoff, matchlen, buffer, buflen);
}
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index 6faddfb..f8d0bd8 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -1857,8 +1857,6 @@
unsigned int cmd, void *arg)
{
switch (cmd) {
- case SNDRV_PCM_IOCTL1_INFO:
- return 0;
case SNDRV_PCM_IOCTL1_RESET:
return snd_pcm_lib_ioctl_reset(substream, arg);
case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 3d9ff6d..8e5649a 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -197,7 +197,6 @@
int snd_pcm_info(struct snd_pcm_substream *substream, struct snd_pcm_info *info)
{
- struct snd_pcm_runtime *runtime;
struct snd_pcm *pcm = substream->pcm;
struct snd_pcm_str *pstr = substream->pstr;
@@ -213,12 +212,7 @@
info->subdevices_count = pstr->substream_count;
info->subdevices_avail = pstr->substream_count - pstr->substream_opened;
strlcpy(info->subname, substream->name, sizeof(info->subname));
- runtime = substream->runtime;
- /* AB: FIXME!!! This is definitely nonsense */
- if (runtime) {
- info->sync = runtime->sync;
- substream->ops->ioctl(substream, SNDRV_PCM_IOCTL1_INFO, info);
- }
+
return 0;
}
diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c
index 19d6af8..fc9c9b0 100644
--- a/sound/soc/soc-ops.c
+++ b/sound/soc/soc-ops.c
@@ -379,7 +379,7 @@
unsigned int rshift = mc->rshift;
int max = mc->max;
int min = mc->min;
- int mask = (1 << (fls(min + max) - 1)) - 1;
+ unsigned int mask = (1 << (fls(min + max) - 1)) - 1;
unsigned int val;
int ret;
@@ -424,7 +424,7 @@
unsigned int rshift = mc->rshift;
int max = mc->max;
int min = mc->min;
- int mask = (1 << (fls(min + max) - 1)) - 1;
+ unsigned int mask = (1 << (fls(min + max) - 1)) - 1;
int err = 0;
unsigned int val, val_mask, val2 = 0;