drm/msm/sde: add qseedv3.x support for sde
Qseedv3.x block supports filtering, scaling and sharpening.
Change adds support to program scaler, detail enhancer
and LUT coefficients.
Change-Id: Idfec866dd9f7acb73c79780e2c3b6b6ce73d42c8
Signed-off-by: abeykun <abeykun@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 4624996..6ff191f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -79,8 +79,12 @@
enum msm_mdp_plane_property {
/* blob properties, always put these first */
PLANE_PROP_SCALER_V1,
+ PLANE_PROP_SCALER_V2,
PLANE_PROP_CSC_V1,
PLANE_PROP_INFO,
+ PLANE_PROP_SCALER_LUT_ED,
+ PLANE_PROP_SCALER_LUT_CIR,
+ PLANE_PROP_SCALER_LUT_SEP,
/* # of blob properties */
PLANE_PROP_BLOBCOUNT,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 911fbe2..64af8b3 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -262,9 +262,11 @@
/**
* struct sde_scaler_blk: Scaler information
* @info: HW register and features supported by this sub-blk
+ * @version: qseed block revision
*/
struct sde_scaler_blk {
SDE_HW_SUBBLK_INFO;
+ u32 version;
};
struct sde_csc_blk {
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
index 42473f8..20e42b0 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
@@ -37,6 +37,9 @@
#endif
#define PIPES_PER_STAGE 2
+#ifndef SDE_MAX_DE_CURVES
+#define SDE_MAX_DE_CURVES 3
+#endif
#define SDE_FORMAT_FLAG_YUV (1 << 0)
#define SDE_FORMAT_FLAG_DX (1 << 1)
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index c589c0c..36c6fe2 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -85,6 +85,57 @@
#define COMP1_2_INIT_PHASE_Y 0x2C
#define VIG_0_QSEED2_SHARP 0x30
+/* SDE_SSPP_SCALER_QSEED3 */
+#define QSEED3_HW_VERSION 0x00
+#define QSEED3_OP_MODE 0x04
+#define QSEED3_RGB2Y_COEFF 0x08
+#define QSEED3_PHASE_INIT 0x0C
+#define QSEED3_PHASE_STEP_Y_H 0x10
+#define QSEED3_PHASE_STEP_Y_V 0x14
+#define QSEED3_PHASE_STEP_UV_H 0x18
+#define QSEED3_PHASE_STEP_UV_V 0x1C
+#define QSEED3_PRELOAD 0x20
+#define QSEED3_DE_SHARPEN 0x24
+#define QSEED3_DE_SHARPEN_CTL 0x28
+#define QSEED3_DE_SHAPE_CTL 0x2C
+#define QSEED3_DE_THRESHOLD 0x30
+#define QSEED3_DE_ADJUST_DATA_0 0x34
+#define QSEED3_DE_ADJUST_DATA_1 0x38
+#define QSEED3_DE_ADJUST_DATA_2 0x3C
+#define QSEED3_SRC_SIZE_Y_RGB_A 0x40
+#define QSEED3_SRC_SIZE_UV 0x44
+#define QSEED3_DST_SIZE 0x48
+#define QSEED3_COEF_LUT_CTRL 0x4C
+#define QSEED3_COEF_LUT_SWAP_BIT 0
+#define QSEED3_COEF_LUT_DIR_BIT 1
+#define QSEED3_COEF_LUT_Y_CIR_BIT 2
+#define QSEED3_COEF_LUT_UV_CIR_BIT 3
+#define QSEED3_COEF_LUT_Y_SEP_BIT 4
+#define QSEED3_COEF_LUT_UV_SEP_BIT 5
+#define QSEED3_BUFFER_CTRL 0x50
+#define QSEED3_CLK_CTRL0 0x54
+#define QSEED3_CLK_CTRL1 0x58
+#define QSEED3_CLK_STATUS 0x5C
+#define QSEED3_MISR_CTRL 0x70
+#define QSEED3_MISR_SIGNATURE_0 0x74
+#define QSEED3_MISR_SIGNATURE_1 0x78
+#define QSEED3_PHASE_INIT_Y_H 0x90
+#define QSEED3_PHASE_INIT_Y_V 0x94
+#define QSEED3_PHASE_INIT_UV_H 0x98
+#define QSEED3_PHASE_INIT_UV_V 0x9C
+#define QSEED3_COEF_LUT 0x100
+#define QSEED3_FILTERS 5
+#define QSEED3_LUT_REGIONS 4
+#define QSEED3_CIRCULAR_LUTS 9
+#define QSEED3_SEPARABLE_LUTS 10
+#define QSEED3_LUT_SIZE 60
+#define QSEED3_ENABLE 2
+#define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32))
+#define QSEED3_CIR_LUT_SIZE \
+ (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
+#define QSEED3_SEP_LUT_SIZE \
+ (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
+
/*
* Definitions for ViG op modes
*/
@@ -147,17 +198,19 @@
u32 idx;
u32 opmode;
- if (!_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) &&
- test_bit(SDE_SSPP_CSC, &ctx->cap->features)) {
- opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
+ if (!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features) ||
+ _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) ||
+ !test_bit(SDE_SSPP_CSC, &ctx->cap->features))
+ return;
- if (en)
- opmode |= mask;
- else
- opmode &= ~mask;
+ opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);
- SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
- }
+ if (en)
+ opmode |= mask;
+ else
+ opmode &= ~mask;
+
+ SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode);
}
/**
* Setup source pixel format, flip,
@@ -305,13 +358,17 @@
}
static void _sde_hw_sspp_setup_scaler(struct sde_hw_pipe *ctx,
- struct sde_hw_pixel_ext *pe)
+ struct sde_hw_pipe_cfg *sspp,
+ struct sde_hw_pixel_ext *pe,
+ void *scaler_cfg)
{
struct sde_hw_blk_reg_map *c;
int config_h = 0x0;
int config_v = 0x0;
u32 idx;
+ (void)sspp;
+ (void)scaler_cfg;
if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !pe)
return;
@@ -358,12 +415,249 @@
pe->phase_step_y[SDE_SSPP_COMP_1_2]);
}
+static void _sde_hw_sspp_setup_scaler3_lut(struct sde_hw_pipe *ctx,
+ struct sde_hw_scaler3_cfg *scaler3_cfg)
+{
+ u32 idx;
+ int i, j, filter;
+ int config_lut = 0x0;
+ unsigned long lut_flags;
+ u32 lut_addr, lut_offset, lut_len;
+ u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
+ static const uint32_t offset[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
+ {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
+ {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
+ {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
+ {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
+ {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
+ };
+
+ if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) ||
+ !scaler3_cfg)
+ return;
+
+ lut_flags = (unsigned long) scaler3_cfg->lut_flag;
+ if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
+ (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
+ lut[0] = scaler3_cfg->dir_lut;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
+ (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+ (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+ lut[1] = scaler3_cfg->cir_lut +
+ scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
+ (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
+ (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
+ lut[2] = scaler3_cfg->cir_lut +
+ scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
+ (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+ (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+ lut[3] = scaler3_cfg->sep_lut +
+ scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+ if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
+ (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
+ (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
+ lut[4] = scaler3_cfg->sep_lut +
+ scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
+ config_lut = 1;
+ }
+
+ if (config_lut) {
+ for (filter = 0; filter < QSEED3_FILTERS; filter++) {
+ if (!lut[filter])
+ continue;
+ lut_offset = 0;
+ for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
+ lut_addr = QSEED3_COEF_LUT + idx
+ + offset[filter][i][1];
+ lut_len = offset[filter][i][0] << 2;
+ for (j = 0; j < lut_len; j++) {
+ SDE_REG_WRITE(&ctx->hw,
+ lut_addr,
+ (lut[filter])[lut_offset++]);
+ lut_addr += 4;
+ }
+ }
+ }
+ }
+
+ if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
+ SDE_REG_WRITE(&ctx->hw, QSEED3_COEF_LUT_CTRL + idx, BIT(0));
+
+}
+
+static void _sde_hw_sspp_setup_scaler3_de(struct sde_hw_pipe *ctx,
+ struct sde_hw_scaler3_de_cfg *de_cfg)
+{
+ u32 idx;
+ u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
+ u32 adjust_a, adjust_b, adjust_c;
+ struct sde_hw_blk_reg_map *hw;
+
+ if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !de_cfg)
+ return;
+
+ if (!de_cfg->enable)
+ return;
+
+ hw = &ctx->hw;
+ sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
+ ((de_cfg->sharpen_level2 & 0x1FF) << 16);
+
+ sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
+ ((de_cfg->prec_shift & 0x7) << 13) |
+ ((de_cfg->clip & 0x7) << 16);
+
+ shape_ctl = (de_cfg->thr_quiet & 0xFF) |
+ ((de_cfg->thr_dieout & 0x3FF) << 16);
+
+ de_thr = (de_cfg->thr_low & 0x3FF) |
+ ((de_cfg->thr_high & 0x3FF) << 16);
+
+ adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
+ ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_a[2] & 0x3FF) << 20);
+
+ adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
+ ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_b[2] & 0x3FF) << 20);
+
+ adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
+ ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
+ ((de_cfg->adjust_c[2] & 0x3FF) << 20);
+
+ SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN + idx, sharp_lvl);
+ SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN_CTL + idx, sharp_ctl);
+ SDE_REG_WRITE(hw, QSEED3_DE_SHAPE_CTL + idx, shape_ctl);
+ SDE_REG_WRITE(hw, QSEED3_DE_THRESHOLD + idx, de_thr);
+ SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_0 + idx, adjust_a);
+ SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_1 + idx, adjust_b);
+ SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_2 + idx, adjust_c);
+
+}
+
+static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
+ struct sde_hw_pipe_cfg *sspp,
+ struct sde_hw_pixel_ext *pe,
+ void *scaler_cfg)
+{
+ u32 idx;
+ u32 op_mode = 0;
+ u32 phase_init, preload, src_y_rgb, src_uv, dst;
+ struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
+
+ (void)pe;
+ if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !sspp
+ || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
+ return;
+
+ if (!scaler3_cfg->enable) {
+ SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, 0x0);
+ return;
+ }
+
+ op_mode |= BIT(0);
+ op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
+
+ if (SDE_FORMAT_IS_YUV(sspp->layout.format)) {
+ op_mode |= BIT(12);
+ op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
+ }
+
+ if (!SDE_FORMAT_IS_DX(sspp->layout.format))
+ op_mode |= BIT(14);
+
+ op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
+ op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+
+ preload =
+ ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
+ ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
+ ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
+ ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
+
+ src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
+ ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
+
+ src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
+ ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
+
+ dst = (scaler3_cfg->dst_width & 0x1FFFF) |
+ ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
+
+ if (scaler3_cfg->de.enable) {
+ _sde_hw_sspp_setup_scaler3_de(ctx, &scaler3_cfg->de);
+ op_mode |= BIT(8);
+ }
+
+ if (scaler3_cfg->lut_flag)
+ _sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg);
+
+ if (ctx->cap->sblk->scaler_blk.version == 0x1002) {
+ if (sspp->layout.format->alpha_enable) {
+ op_mode |= BIT(10);
+ op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
+ }
+ phase_init =
+ ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
+ ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
+ ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
+ ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init);
+ } else {
+ if (sspp->layout.format->alpha_enable) {
+ op_mode |= BIT(10);
+ op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
+ }
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx,
+ scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx,
+ scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_H + idx,
+ scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_V + idx,
+ scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
+ }
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_H + idx,
+ scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_V + idx,
+ scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_H + idx,
+ scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_V + idx,
+ scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_PRELOAD + idx, preload);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_Y_RGB_A + idx, src_y_rgb);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_UV + idx, src_uv);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst);
+
+ SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode);
+}
+
/**
* sde_hw_sspp_setup_rects()
*/
static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx,
struct sde_hw_pipe_cfg *cfg,
- struct sde_hw_pixel_ext *pe_ext)
+ struct sde_hw_pixel_ext *pe_ext,
+ void *scale_cfg)
{
struct sde_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
@@ -395,8 +689,7 @@
/* program decimation */
decimation = ((1 << cfg->horz_decimation) - 1) << 8;
decimation |= ((1 << cfg->vert_decimation) - 1);
-
- _sde_hw_sspp_setup_scaler(ctx, pe_ext);
+ ctx->ops.setup_scaler(ctx, cfg, pe_ext, scale_cfg);
}
/* rectangle register programming */
@@ -530,6 +823,11 @@
if (test_bit(SDE_SSPP_SCALER_QSEED2, &features))
ops->setup_sharpening = sde_hw_sspp_setup_sharpening;
+
+ if (test_bit(SDE_SSPP_SCALER_QSEED3, &features))
+ ops->setup_scaler = _sde_hw_sspp_setup_scaler3;
+ else
+ ops->setup_scaler = _sde_hw_sspp_setup_scaler;
}
static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
index 43070fa..488936e 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -119,8 +119,112 @@
};
+/**
+ * struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
+ * @enable: detail enhancer enable/disable
+ * @sharpen_level1: sharpening strength for noise
+ * @sharpen_level2: sharpening strength for signal
+ * @ clip: clip shift
+ * @ limit: limit value
+ * @ thr_quiet: quiet threshold
+ * @ thr_dieout: dieout threshold
+ * @ thr_high: low threshold
+ * @ thr_high: high threshold
+ * @ prec_shift: precision shift
+ * @ adjust_a: A-coefficients for mapping curve
+ * @ adjust_b: B-coefficients for mapping curve
+ * @ adjust_c: C-coefficients for mapping curve
+ */
+struct sde_hw_scaler3_de_cfg {
+ u32 enable;
+ int16_t sharpen_level1;
+ int16_t sharpen_level2;
+ uint16_t clip;
+ uint16_t limit;
+ uint16_t thr_quiet;
+ uint16_t thr_dieout;
+ uint16_t thr_low;
+ uint16_t thr_high;
+ uint16_t prec_shift;
+ int16_t adjust_a[SDE_MAX_DE_CURVES];
+ int16_t adjust_b[SDE_MAX_DE_CURVES];
+ int16_t adjust_c[SDE_MAX_DE_CURVES];
+};
+
+/**
+ * struct sde_hw_scaler3_cfg : QSEEDv3 configuration
+ * @enable: scaler enable
+ * @dir_en: direction detection block enable
+ * @ init_phase_x: horizontal initial phase
+ * @ phase_step_x: horizontal phase step
+ * @ init_phase_y: vertical initial phase
+ * @ phase_step_y: vertical phase step
+ * @ preload_x: horizontal preload value
+ * @ preload_y: vertical preload value
+ * @ src_width: source width
+ * @ src_height: source height
+ * @ dst_width: destination width
+ * @ dst_height: destination height
+ * @ y_rgb_filter_cfg: y/rgb plane filter configuration
+ * @ uv_filter_cfg: uv plane filter configuration
+ * @ alpha_filter_cfg: alpha filter configuration
+ * @ blend_cfg: blend coefficients configuration
+ * @ lut_flag: scaler LUT update flags
+ * 0x1 swap LUT bank
+ * 0x2 update 2D filter LUT
+ * 0x4 update y circular filter LUT
+ * 0x8 update uv circular filter LUT
+ * 0x10 update y separable filter LUT
+ * 0x20 update uv separable filter LUT
+ * @ dir_lut_idx: 2D filter LUT index
+ * @ y_rgb_cir_lut_idx: y circular filter LUT index
+ * @ uv_cir_lut_idx: uv circular filter LUT index
+ * @ y_rgb_sep_lut_idx: y circular filter LUT index
+ * @ uv_sep_lut_idx: uv separable filter LUT index
+ * @ dir_lut: pointer to 2D LUT
+ * @ cir_lut: pointer to circular filter LUT
+ * @ sep_lut: pointer to separable filter LUT
+ * @ de: detail enhancer configuration
+ */
struct sde_hw_scaler3_cfg {
- uint32_t filter_mode;
+ u32 enable;
+ u32 dir_en;
+ int32_t init_phase_x[SDE_MAX_PLANES];
+ int32_t phase_step_x[SDE_MAX_PLANES];
+ int32_t init_phase_y[SDE_MAX_PLANES];
+ int32_t phase_step_y[SDE_MAX_PLANES];
+
+ u32 preload_x[SDE_MAX_PLANES];
+ u32 preload_y[SDE_MAX_PLANES];
+ u32 src_width[SDE_MAX_PLANES];
+ u32 src_height[SDE_MAX_PLANES];
+
+ u32 dst_width;
+ u32 dst_height;
+
+ u32 y_rgb_filter_cfg;
+ u32 uv_filter_cfg;
+ u32 alpha_filter_cfg;
+ u32 blend_cfg;
+
+ u32 lut_flag;
+ u32 dir_lut_idx;
+
+ u32 y_rgb_cir_lut_idx;
+ u32 uv_cir_lut_idx;
+ u32 y_rgb_sep_lut_idx;
+ u32 uv_sep_lut_idx;
+ u32 *dir_lut;
+ size_t dir_len;
+ u32 *cir_lut;
+ size_t cir_len;
+ u32 *sep_lut;
+ size_t sep_len;
+
+ /*
+ * Detail enhancer settings
+ */
+ struct sde_hw_scaler3_de_cfg de;
};
/**
@@ -184,10 +288,12 @@
* @ctx: Pointer to pipe context
* @cfg: Pointer to pipe config structure
* @pe_ext: Pointer to pixel ext settings
+ * @scale_cfg: Pointer to scaler settings
*/
void (*setup_rects)(struct sde_hw_pipe *ctx,
struct sde_hw_pipe_cfg *cfg,
- struct sde_hw_pixel_ext *pe_ext);
+ struct sde_hw_pixel_ext *pe_ext,
+ void *scale_cfg);
/**
* setup_sourceaddress - setup pipe source addresses
@@ -269,6 +375,18 @@
*/
void (*setup_histogram)(struct sde_hw_pipe *ctx,
void *cfg);
+
+ /**
+ * setup_scaler - setup scaler
+ * @ctx: Pointer to pipe context
+ * @pipe_cfg: Pointer to pipe configuration
+ * @pe_cfg: Pointer to pixel extension configuration
+ * @scaler_cfg: Pointer to scaler configuration
+ */
+ void (*setup_scaler)(struct sde_hw_pipe *ctx,
+ struct sde_hw_pipe_cfg *pipe_cfg,
+ struct sde_hw_pixel_ext *pe_cfg,
+ void *scaler_cfg);
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 86e44ad..28c3606 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -86,7 +86,7 @@
struct sde_hw_pipe *pipe_hw;
struct sde_hw_pipe_cfg pipe_cfg;
struct sde_hw_sharp_cfg sharp_cfg;
- struct sde_hw_scaler3_cfg scaler3_cfg;
+ struct sde_hw_scaler3_cfg *scaler3_cfg;
struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
uint32_t color_fill;
bool is_error;
@@ -547,6 +547,29 @@
psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
}
+static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
+ struct sde_plane_state *pstate)
+{
+ struct sde_hw_scaler3_cfg *cfg = psde->scaler3_cfg;
+ int ret = 0;
+
+ cfg->dir_lut = msm_property_get_blob(
+ &psde->property_info,
+ pstate->property_blobs, &cfg->dir_len,
+ PLANE_PROP_SCALER_LUT_ED);
+ cfg->cir_lut = msm_property_get_blob(
+ &psde->property_info,
+ pstate->property_blobs, &cfg->cir_len,
+ PLANE_PROP_SCALER_LUT_CIR);
+ cfg->sep_lut = msm_property_get_blob(
+ &psde->property_info,
+ pstate->property_blobs, &cfg->sep_len,
+ PLANE_PROP_SCALER_LUT_SEP);
+ if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
+ ret = -ENODATA;
+ return ret;
+}
+
static void _sde_plane_setup_scaler3(struct sde_plane *psde,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct sde_hw_scaler3_cfg *scale_cfg,
@@ -766,14 +789,17 @@
/* update scaler */
if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
- if (!psde->pixel_ext_usr) {
+ int error;
+
+ error = _sde_plane_setup_scaler3_lut(psde, pstate);
+ if (error || !psde->pixel_ext_usr) {
/* calculate default config for QSEED3 */
_sde_plane_setup_scaler3(psde,
psde->pipe_cfg.src_rect.w,
psde->pipe_cfg.src_rect.h,
psde->pipe_cfg.dst_rect.w,
psde->pipe_cfg.dst_rect.h,
- &psde->scaler3_cfg, fmt,
+ psde->scaler3_cfg, fmt,
chroma_subsmpl_h, chroma_subsmpl_v);
}
} else if (!psde->pixel_ext_usr) {
@@ -888,7 +914,8 @@
if (psde->pipe_hw->ops.setup_rects)
psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
- &psde->pipe_cfg, &psde->pixel_ext);
+ &psde->pipe_cfg, &psde->pixel_ext,
+ psde->scaler3_cfg);
}
return 0;
@@ -932,6 +959,7 @@
while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
switch (idx) {
case PLANE_PROP_SCALER_V1:
+ case PLANE_PROP_SCALER_V2:
case PLANE_PROP_H_DECIMATE:
case PLANE_PROP_V_DECIMATE:
case PLANE_PROP_SRC_CONFIG:
@@ -1012,7 +1040,8 @@
_sde_plane_setup_scaler(psde, fmt, pstate);
psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
- &psde->pipe_cfg, &psde->pixel_ext);
+ &psde->pipe_cfg, &psde->pixel_ext,
+ psde->scaler3_cfg);
}
}
@@ -1428,7 +1457,16 @@
PLANE_PROP_V_DECIMATE);
}
- if (psde->features & SDE_SSPP_SCALER) {
+ if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
+ msm_property_install_volatile_range(&psde->property_info,
+ "scaler_v2", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
+ msm_property_install_blob(&psde->property_info, "lut_ed", 0,
+ PLANE_PROP_SCALER_LUT_ED);
+ msm_property_install_blob(&psde->property_info, "lut_cir", 0,
+ PLANE_PROP_SCALER_LUT_CIR);
+ msm_property_install_blob(&psde->property_info, "lut_sep", 0,
+ PLANE_PROP_SCALER_LUT_SEP);
+ } else if (psde->features & SDE_SSPP_SCALER) {
msm_property_install_volatile_range(&psde->property_info,
"scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
}
@@ -1581,6 +1619,99 @@
SDE_DEBUG_PLANE(psde, "user property data copied\n");
}
+static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
+ struct sde_plane_state *pstate, void *usr)
+{
+ struct sde_drm_scaler_v2 scale_v2;
+ struct sde_hw_pixel_ext *pe;
+ int i;
+ struct sde_hw_scaler3_cfg *cfg;
+
+ if (!psde) {
+ SDE_ERROR("invalid plane\n");
+ return;
+ }
+
+ cfg = psde->scaler3_cfg;
+ psde->pixel_ext_usr = false;
+ if (!usr) {
+ SDE_DEBUG_PLANE(psde, "scale data removed\n");
+ return;
+ }
+
+ if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
+ SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
+ return;
+ }
+
+ /* populate from user space */
+ pe = &(psde->pixel_ext);
+ memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
+ cfg->enable = scale_v2.enable;
+ cfg->dir_en = scale_v2.dir_en;
+ for (i = 0; i < SDE_MAX_PLANES; i++) {
+ cfg->init_phase_x[i] = scale_v2.init_phase_x[i];
+ cfg->phase_step_x[i] = scale_v2.phase_step_x[i];
+ cfg->init_phase_y[i] = scale_v2.init_phase_y[i];
+ cfg->phase_step_y[i] = scale_v2.phase_step_y[i];
+
+ cfg->preload_x[i] = scale_v2.preload_x[i];
+ cfg->preload_y[i] = scale_v2.preload_y[i];
+ cfg->src_width[i] = scale_v2.src_width[i];
+ cfg->src_height[i] = scale_v2.src_height[i];
+ }
+ cfg->dst_width = scale_v2.dst_width;
+ cfg->dst_height = scale_v2.dst_height;
+
+ cfg->y_rgb_filter_cfg = scale_v2.y_rgb_filter_cfg;
+ cfg->uv_filter_cfg = scale_v2.uv_filter_cfg;
+ cfg->alpha_filter_cfg = scale_v2.alpha_filter_cfg;
+ cfg->blend_cfg = scale_v2.blend_cfg;
+
+ cfg->lut_flag = scale_v2.lut_flag;
+ cfg->dir_lut_idx = scale_v2.dir_lut_idx;
+ cfg->y_rgb_cir_lut_idx = scale_v2.y_rgb_cir_lut_idx;
+ cfg->uv_cir_lut_idx = scale_v2.uv_cir_lut_idx;
+ cfg->y_rgb_sep_lut_idx = scale_v2.y_rgb_sep_lut_idx;
+ cfg->uv_sep_lut_idx = scale_v2.uv_sep_lut_idx;
+
+ cfg->de.enable = scale_v2.de.enable;
+ cfg->de.sharpen_level1 = scale_v2.de.sharpen_level1;
+ cfg->de.sharpen_level2 = scale_v2.de.sharpen_level2;
+ cfg->de.clip = scale_v2.de.clip;
+ cfg->de.limit = scale_v2.de.limit;
+ cfg->de.thr_quiet = scale_v2.de.thr_quiet;
+ cfg->de.thr_dieout = scale_v2.de.thr_dieout;
+ cfg->de.thr_low = scale_v2.de.thr_low;
+ cfg->de.thr_high = scale_v2.de.thr_high;
+ cfg->de.prec_shift = scale_v2.de.prec_shift;
+ for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
+ cfg->de.adjust_a[i] = scale_v2.de.adjust_a[i];
+ cfg->de.adjust_b[i] = scale_v2.de.adjust_b[i];
+ cfg->de.adjust_c[i] = scale_v2.de.adjust_c[i];
+ }
+ for (i = 0; i < SDE_MAX_PLANES; i++) {
+ pe->num_ext_pxls_left[i] = scale_v2.lr.num_pxls_start[i];
+ pe->num_ext_pxls_right[i] = scale_v2.lr.num_pxls_end[i];
+ pe->left_ftch[i] = scale_v2.lr.ftch_start[i];
+ pe->right_ftch[i] = scale_v2.lr.ftch_end[i];
+ pe->left_rpt[i] = scale_v2.lr.rpt_start[i];
+ pe->right_rpt[i] = scale_v2.lr.rpt_end[i];
+ pe->roi_w[i] = scale_v2.lr.roi[i];
+
+ pe->num_ext_pxls_top[i] = scale_v2.tb.num_pxls_start[i];
+ pe->num_ext_pxls_btm[i] = scale_v2.tb.num_pxls_end[i];
+ pe->top_ftch[i] = scale_v2.tb.ftch_start[i];
+ pe->btm_ftch[i] = scale_v2.tb.ftch_end[i];
+ pe->top_rpt[i] = scale_v2.tb.rpt_start[i];
+ pe->btm_rpt[i] = scale_v2.tb.rpt_end[i];
+ pe->roi_h[i] = scale_v2.tb.roi[i];
+ }
+ psde->pixel_ext_usr = true;
+
+ SDE_DEBUG_PLANE(psde, "user property data copied\n");
+}
+
static int sde_plane_atomic_set_property(struct drm_plane *plane,
struct drm_plane_state *state, struct drm_property *property,
uint64_t val)
@@ -1613,6 +1744,10 @@
case PLANE_PROP_SCALER_V1:
_sde_plane_set_scaler_v1(psde, (void *)val);
break;
+ case PLANE_PROP_SCALER_V2:
+ _sde_plane_set_scaler_v2(psde, pstate,
+ (void *)val);
+ break;
default:
/* nothing to do */
break;
@@ -1930,6 +2065,17 @@
goto clean_sspp;
}
+ if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
+ psde->scaler3_cfg = kzalloc(sizeof(struct sde_hw_scaler3_cfg),
+ GFP_KERNEL);
+ if (!psde->scaler3_cfg) {
+ SDE_ERROR("[%u]failed to allocate scale struct\n",
+ pipe);
+ ret = -ENOMEM;
+ goto clean_sspp;
+ }
+ }
+
/* add plane to DRM framework */
psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
psde->formats,
@@ -1975,6 +2121,9 @@
clean_sspp:
if (psde && psde->pipe_hw)
sde_hw_sspp_destroy(psde->pipe_hw);
+
+ if (psde && psde->scaler3_cfg)
+ kfree(psde->scaler3_cfg);
clean_plane:
kfree(psde);
exit: