| commit | 4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e | [log] [tgz] |
|---|---|---|
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | Tue Jul 12 00:51:58 2016 +0300 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Jul 15 13:20:39 2016 +0900 |
| tree | bf9472a2ceab27ae04308e0008bf5bc8391ed9ac | |
| parent | 8fd763c75c3ab8e72e5d7f0d4c53531e6ff76197 [diff] |
ARM: dts: r8a7792: add PLL1 divided by 2 clock Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the latter hasn't been added to the R8A7792 device tree. This patch corrects that oversight. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>