tree a148753cbfea2eee98989d253b9ca572a7873023
parent ba86bf8bfc1add5f515db8cf1d6042bb9396a299
author Zhenyu Wang <zhenyuw@linux.intel.com> 1257148349 +0000
committer Eric Anholt <eric@anholt.net> 1257458432 -0800

drm/i915: Fix and cleanup DPLL calculation for Ironlake

When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.

This fixes DPLL clock issue against one monitor at 1680x1050@60hz.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>