tree 0ca9f5254f74590f8f3bd72064b327a77395e01c
parent 0774539948b23984f1c866135ba307fa2c441d0e
author Shinya Kuribayashi <shinya.kuribayashi@necel.com> 1257511692 +0900
committer Ben Dooks <ben-linux@fluff.org> 1260317951 +0000

i2c-designware: Set Tx/Rx FIFO threshold levels

As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.

In other words, we must never make "Tx FIFO underrun" happen during
a transaction, except for the last byte.  For the safety's sake, we'd
make TX_EMPTY interrupt get triggered every time one byte is processed.

The Rx FIFO threshold needs to be set as well.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>