tree f6b8dec7781a7ece62f55af354ba6f5e49d37fdb
parent 5b5b544ed32a1b6ad4d7706fcee530eb67670e71
author Gabor Juhos <juhosg@openwrt.org> 1331718324 +0100
committer Ralf Baechle <ralf@linux-mips.org> 1337096948 +0200

MIPS: ath79: rework IP2/IP3 interrupt handling

The current implementation assumes that flushing the
DDR writeback buffer is required for IP2/IP3 interrupts,
however this is not true for all SoCs.

Use SoC specific IP2/IP3 handlers instead of flushing
the buffers in the dispatcher code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>