| commit | 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 | [log] [tgz] |
|---|---|---|
| author | Rajendra Nayak <rnayak@ti.com> | Mon May 07 23:55:21 2012 -0600 |
| committer | Paul Walmsley <paul@pwsan.com> | Mon May 07 23:55:21 2012 -0600 |
| tree | 1756942d86be26b7790a7fb825e816708f5b197d | |
| parent | 96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 [diff] |
ARM: OMAP3: Fix CM register bit masks The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL register are 3 bits wide. Fix the MASK definition accordingly. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>