tree e30e456d03ce4b8ad85e3ed4980b425efd7d3e62
parent 67d62c57465e5da7647cb13ef567b80f6deb9a3c
author Ville Syrjälä <ville.syrjala@linux.intel.com> 1359034186 +0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1359065593 +0100

drm/i915: Pipe timing registers need an offset on VLV

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>