Merge "power: qos: check for NULL irq desc object"
diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
index 669997c..cbe8378 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
@@ -144,10 +144,11 @@
0xff = default value.
- qcom,mdss-dsi-border-color: Defines the border color value if border is present.
0 = default value.
-- qcom,mdss-dsi-panel-jitter: An integer value defines the panel jitter timing for rsc
- backoff time. The jitter configurition causes the early
- wakeup if panel needs to adjust before vsync.
- Default jitter value is 5%. Max allowed value is 25%.
+- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator
+ and denominator. It contains two u32 values - numerator
+ followed by denominator. The jitter configurition causes
+ the early wakeup if panel needs to adjust before vsync.
+ Default jitter value is 2.0%. Max allowed value is 10%.
- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to
calculate the backoff time of rsc.
Default value is 16 lines. Max allowed value is vtotal.
@@ -664,7 +665,7 @@
<40 120 128>,
<128 240 64>;
qcom,mdss-dsi-panel-orientation = "180"
- qcom,mdss-dsi-panel-jitter = <0x8>;
+ qcom,mdss-dsi-panel-jitter = <0x8 0x10>;
qcom,mdss-dsi-panel-prefill-lines = <0x10>;
qcom,mdss-dsi-force-clock-lane-hs;
qcom,compression-mode = "dsc";
diff --git a/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt b/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt
index 58bac0b..46649af 100644
--- a/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt
+++ b/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt
@@ -81,6 +81,7 @@
limits.
- qcom,mdss-rot-vbif-qos-setting: This array is used to program vbif qos remapper register
priority for rotator clients.
+- qcom,mdss-rot-vbif-memtype: Array of u32 vbif memory type settings for each xin port.
- qcom,mdss-rot-cdp-setting: Integer array of size two, to indicate client driven
prefetch is available or not. Index 0 represents
if CDP is enabled for read and index 1, if CDP
@@ -173,6 +174,7 @@
/* VBIF QoS remapper settings*/
qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
com,mdss-rot-cdp-setting = <1 1>;
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 58c6398..ee4a723 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -182,6 +182,20 @@
extern void dmac_clean_range(const void *, const void *);
extern void dmac_flush_range(const void *, const void *);
+static inline void __dma_inv_area(const void *start, size_t len)
+{
+ dmac_inv_range(start, start + len);
+}
+
+static inline void __dma_clean_area(const void *start, size_t len)
+{
+ dmac_clean_range(start, start + len);
+}
+
+static inline void __dma_flush_area(const void *start, size_t len)
+{
+ dmac_flush_range(start, start + len);
+}
#endif
/*
diff --git a/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi b/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
index da3cf00..dcc646c93b 100644
--- a/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
@@ -196,6 +196,7 @@
hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
qcom,no-status-check-on-disable;
qcom,gds-timeout = <500>;
+ qcom,clk-dis-wait-val = <8>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index e313e58..7ceb5b2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -354,6 +354,7 @@
/* Offline rotator QoS setting */
qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
qcom,mdss-rot-cdp-setting = <1 1>;
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
qcom,mdss-rot-danger-lut = <0x0 0x0>;
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index b2f6a3c..5f1b1ef 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -36,6 +36,11 @@
#include "clk-alpha-pll.h"
#include "vdd-level-sdm845.h"
+#define CX_GMU_CBCR_SLEEP_MASK 0xF
+#define CX_GMU_CBCR_SLEEP_SHIFT 4
+#define CX_GMU_CBCR_WAKE_MASK 0xF
+#define CX_GMU_CBCR_WAKE_SHIFT 8
+
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static int vdd_gx_corner[] = {
@@ -648,6 +653,7 @@
{
struct regmap *regmap;
int ret = 0;
+ unsigned int value, mask;
regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
if (IS_ERR(regmap))
@@ -668,6 +674,12 @@
return ret;
}
+ mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
+ mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
+ value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
+ regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
+ mask, value);
+
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
return ret;
diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c
index 13daf30..e11ea50 100644
--- a/drivers/cpuidle/lpm-levels.c
+++ b/drivers/cpuidle/lpm-levels.c
@@ -66,7 +66,8 @@
CPU_EXIT,
CLUSTER_ENTER,
CLUSTER_EXIT,
- PRE_PC_CB,
+ CPU_HP_STARTING,
+ CPU_HP_DYING,
};
struct lpm_debug {
@@ -324,6 +325,9 @@
{
struct lpm_cluster *cluster = per_cpu(cpu_lpm, cpu)->parent;
+ update_debug_pc_event(CPU_HP_DYING, cpu,
+ cluster->num_children_in_sync.bits[0],
+ cluster->child_cpus.bits[0], false);
cluster_prepare(cluster, get_cpu_mask(cpu), NR_LPM_LEVELS, false, 0);
return 0;
}
@@ -332,6 +336,9 @@
{
struct lpm_cluster *cluster = per_cpu(cpu_lpm, cpu)->parent;
+ update_debug_pc_event(CPU_HP_STARTING, cpu,
+ cluster->num_children_in_sync.bits[0],
+ cluster->child_cpus.bits[0], false);
cluster_unprepare(cluster, get_cpu_mask(cpu), NR_LPM_LEVELS, false, 0);
return 0;
}
@@ -582,7 +589,7 @@
uint32_t *min_residency = get_per_cpu_min_residency(dev->cpu);
uint32_t *max_residency = get_per_cpu_max_residency(dev->cpu);
- if (sleep_disabled || sleep_us < 0)
+ if ((sleep_disabled && !cpu_isolated(dev->cpu)) || sleep_us < 0)
return 0;
idx_restrict = cpu->nlevels + 1;
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 70b47ca..eeb7c49 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -28,16 +28,28 @@
config DRM_MSM_HDMI_HDCP
bool "Enable HDMI HDCP support in MSM DRM driver"
depends on DRM_MSM && QCOM_SCM
- default y
+ default n
help
- Choose this option to enable HDCP state machine
+ Compile in support for logging register reads/writes in a format
+ that can be parsed by envytools demsm tool. If enabled, register
+ logging can be switched on via msm.reglog=y module param.
+
+config DRM_MSM_HDMI
+ bool "Enable HDMI support in MSM DRM driver"
+ depends on DRM_MSM
+ default n
+ help
+ Compile in support for HDMI driver in msm drm
+ driver. HDMI external display support is enabled
+ through this config option. It can be primary or
+ secondary display on device.
config DRM_MSM_DSI
bool "Enable DSI support in MSM DRM driver"
depends on DRM_MSM
select DRM_PANEL
select DRM_MIPI_DSI
- default y
+ default n
help
Choose this option if you have a need for MIPI DSI connector
support.
@@ -83,6 +95,17 @@
help
Choose this option if the 28nm DSI PHY 8960 variant is used on the
platform.
+
+config DRM_MSM_MDP5
+ tristate "MSM MDP5 DRM driver"
+ depends on DRM_MSM
+ default n
+ help
+ Choose this option if MSM MDP5 revision support is
+ needed in DRM/KMS. This is not required if sde/mdp4
+ only target enabled. MDP5 supports DSI and HDMI
+ displays.
+
config DRM_MSM_MDP4
tristate "MSM MDP4 DRM driver"
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 1ac5c6c..b698b65 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -15,32 +15,6 @@
dp/dp_ctrl.o \
dp/dp_display.o \
dp/dp_drm.o \
- hdmi/hdmi.o \
- hdmi/hdmi_audio.o \
- hdmi/hdmi_bridge.o \
- hdmi/hdmi_connector.o \
- hdmi/hdmi_i2c.o \
- hdmi/hdmi_phy.o \
- hdmi/hdmi_phy_8960.o \
- hdmi/hdmi_phy_8x60.o \
- hdmi/hdmi_phy_8x74.o \
- edp/edp.o \
- edp/edp_aux.o \
- edp/edp_bridge.o \
- edp/edp_connector.o \
- edp/edp_ctrl.o \
- edp/edp_phy.o \
- mdp/mdp_format.o \
- mdp/mdp_kms.o \
- mdp/mdp5/mdp5_cfg.o \
- mdp/mdp5/mdp5_ctl.o \
- mdp/mdp5/mdp5_crtc.o \
- mdp/mdp5/mdp5_encoder.o \
- mdp/mdp5/mdp5_irq.o \
- mdp/mdp5/mdp5_mdss.o \
- mdp/mdp5/mdp5_kms.o \
- mdp/mdp5/mdp5_plane.o \
- mdp/mdp5/mdp5_smp.o \
sde/sde_crtc.o \
sde/sde_encoder.o \
sde/sde_encoder_phys_vid.o \
@@ -61,7 +35,36 @@
sde/sde_hw_reg_dma_v1_color_proc.o \
sde/sde_hw_color_proc_v4.o \
sde/sde_hw_ad4.o \
- sde_edid_parser.o
+ sde_edid_parser.o \
+
+msm_drm-$(CONFIG_DRM_MSM_HDMI) += hdmi/hdmi.o \
+ hdmi/hdmi_audio.o \
+ hdmi/hdmi_bridge.o \
+ hdmi/hdmi_connector.o \
+ hdmi/hdmi_i2c.o \
+ hdmi/hdmi_phy.o \
+ hdmi/hdmi_phy_8960.o \
+ hdmi/hdmi_phy_8x60.o \
+ hdmi/hdmi_phy_8x74.o \
+
+msm_drm-$(CONFIG_DRM_MSM_EDP) += edp/edp.o \
+ edp/edp_aux.o \
+ edp/edp_bridge.o \
+ edp/edp_connector.o \
+ edp/edp_ctrl.o \
+ edp/edp_phy.o \
+
+msm_drm-$(CONFIG_DRM_MSM_MDP5) += mdp/mdp_format.o \
+ mdp/mdp_kms.o \
+ mdp/mdp5/mdp5_cfg.o \
+ mdp/mdp5/mdp5_ctl.o \
+ mdp/mdp5/mdp5_crtc.o \
+ mdp/mdp5/mdp5_encoder.o \
+ mdp/mdp5/mdp5_irq.o \
+ mdp/mdp5/mdp5_mdss.o \
+ mdp/mdp5/mdp5_kms.o \
+ mdp/mdp5/mdp5_plane.o \
+ mdp/mdp5/mdp5_smp.o \
msm_drm-$(CONFIG_DRM_SDE_RSC) += sde_rsc.o \
sde_rsc_hw.o \
@@ -85,9 +88,9 @@
msm_drm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm_drm-$(CONFIG_SYNC_FILE) += sde/sde_fence.o
-msm_drm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
-msm_drm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
-msm_drm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
+msm_drm-$(CONFIG_DRM_MSM_MDP4) += mdp/mdp4/mdp4_lvds_pll.o
+msm_drm-$(CONFIG_DRM_MSM_HDMI) += hdmi/hdmi_pll_8960.o
+msm_drm-$(CONFIG_DRM_MSM_HDMI) += hdmi/hdmi_phy_8996.o
msm_drm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 6f6c559..a4a9fb5 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -3114,7 +3114,8 @@
info->frame_rate = timing->refresh_rate;
info->vtotal = DSI_V_TOTAL(timing);
info->prefill_lines = display->panel->panel_prefill_lines;
- info->jitter = display->panel->panel_jitter;
+ info->jitter_numer = display->panel->panel_jitter_numer;
+ info->jitter_denom = display->panel->panel_jitter_denom;
info->width_mm = phy_props.panel_width_mm;
info->height_mm = phy_props.panel_height_mm;
info->max_width = 1920;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index b8bf7a8..8bc82f5 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -35,20 +35,66 @@
#define DEFAULT_MDP_TRANSFER_TIME 14000
-#define DEFAULT_PANEL_JITTER 5
-#define MAX_PANEL_JITTER 25
-#define DEFAULT_PANEL_PREFILL_LINES 16
+#define DEFAULT_PANEL_JITTER_NUMERATOR 2
+#define DEFAULT_PANEL_JITTER_DENOMINATOR 1
+#define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
+#define MAX_PANEL_JITTER 10
+#define DEFAULT_PANEL_PREFILL_LINES 25
+
+enum dsi_dsc_ratio_type {
+ DSC_8BPC_8BPP,
+ DSC_10BPC_8BPP,
+ DSC_12BPC_8BPP,
+ DSC_RATIO_TYPE_MAX
+};
static u32 dsi_dsc_rc_buf_thresh[] = {0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54,
0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e};
-static char dsi_dsc_rc_range_min_qp_1_1[] = {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5,
- 5, 5, 7, 13};
-static char dsi_dsc_rc_range_min_qp_1_1_scr1[] = {0, 0, 1, 1, 3, 3, 3, 3, 3, 3,
- 5, 5, 5, 9, 12};
-static char dsi_dsc_rc_range_max_qp_1_1[] = {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11,
- 12, 13, 13, 15};
-static char dsi_dsc_rc_range_max_qp_1_1_scr1[] = {4, 4, 5, 6, 7, 7, 7, 8, 9, 10,
- 11, 11, 12, 13};
+
+/*
+ * DSC 1.1
+ * Rate control - Min QP values for each ratio type in dsi_dsc_ratio_type
+ */
+static char dsi_dsc_rc_range_min_qp_1_1[][15] = {
+ {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13},
+ {0, 4, 5, 5, 7, 7, 7, 7, 7, 7, 9, 9, 9, 11, 17},
+ {0, 4, 9, 9, 11, 11, 11, 11, 11, 11, 13, 13, 13, 15, 21},
+ };
+
+/*
+ * DSC 1.1 SCR
+ * Rate control - Min QP values for each ratio type in dsi_dsc_ratio_type
+ */
+static char dsi_dsc_rc_range_min_qp_1_1_scr1[][15] = {
+ {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 9, 12},
+ {0, 4, 5, 5, 7, 7, 7, 7, 7, 7, 9, 9, 9, 13, 16},
+ {0, 4, 9, 9, 11, 11, 11, 11, 11, 11, 13, 13, 13, 17, 20},
+ };
+
+/*
+ * DSC 1.1
+ * Rate control - Max QP values for each ratio type in dsi_dsc_ratio_type
+ */
+static char dsi_dsc_rc_range_max_qp_1_1[][15] = {
+ {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15},
+ {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 15, 16, 17, 17, 19},
+ {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 19, 20, 21, 21, 23},
+ };
+
+/*
+ * DSC 1.1 SCR
+ * Rate control - Max QP values for each ratio type in dsi_dsc_ratio_type
+ */
+static char dsi_dsc_rc_range_max_qp_1_1_scr1[][15] = {
+ {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 10, 11, 11, 12, 13},
+ {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 14, 15, 15, 16, 17},
+ {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 20, 21},
+ };
+
+/*
+ * DSC 1.1 and DSC 1.1 SCR
+ * Rate control - bpg offset values
+ */
static char dsi_dsc_rc_range_bpg_offset[] = {2, 0, 0, -2, -4, -6, -8, -8,
-8, -10, -10, -12, -12, -12, -12};
@@ -1579,16 +1625,24 @@
struct device_node *of_node)
{
int rc;
+ u32 jitter[DEFAULT_PANEL_JITTER_ARRAY_SIZE] = {0, 0};
+ u64 jitter_val = 0;
- rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-jitter",
- &panel->panel_jitter);
+ rc = of_property_read_u32_array(of_node, "qcom,mdss-dsi-panel-jitter",
+ jitter, DEFAULT_PANEL_JITTER_ARRAY_SIZE);
if (rc) {
- pr_debug("panel jitter is not defined rc=%d\n", rc);
- panel->panel_jitter = DEFAULT_PANEL_JITTER;
- } else if (panel->panel_jitter > MAX_PANEL_JITTER) {
- pr_debug("invalid jitter config=%d setting to:%d\n",
- panel->panel_jitter, DEFAULT_PANEL_JITTER);
- panel->panel_jitter = DEFAULT_PANEL_JITTER;
+ pr_debug("panel jitter not defined rc=%d\n", rc);
+ } else {
+ jitter_val = jitter[0];
+ jitter_val = div_u64(jitter_val, jitter[1]);
+ }
+
+ if (rc || !jitter_val || (jitter_val > MAX_PANEL_JITTER)) {
+ panel->panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR;
+ panel->panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR;
+ } else {
+ panel->panel_jitter_numer = jitter[0];
+ panel->panel_jitter_denom = jitter[1];
}
rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-prefill-lines",
@@ -1848,6 +1902,7 @@
int target_bpp_x16;
int data;
int final_value, final_scale;
+ int ratio_index;
dsc->version = 0x11;
dsc->scr_rev = 0;
@@ -1857,12 +1912,7 @@
else
dsc->first_line_bpg_offset = 12;
- dsc->min_qp_flatness = 3;
- dsc->max_qp_flatness = 12;
- dsc->line_buf_depth = 9;
dsc->edge_factor = 6;
- dsc->quant_incr_limit0 = 11;
- dsc->quant_incr_limit1 = 11;
dsc->tgt_offset_hi = 3;
dsc->tgt_offset_lo = 3;
dsc->enable_422 = 0;
@@ -1870,27 +1920,60 @@
dsc->vbr_enable = 0;
dsc->buf_thresh = dsi_dsc_rc_buf_thresh;
- if (dsc->version == 0x11 && dsc->scr_rev == 0x1) {
- dsc->range_min_qp = dsi_dsc_rc_range_min_qp_1_1_scr1;
- dsc->range_max_qp = dsi_dsc_rc_range_max_qp_1_1_scr1;
- } else {
- dsc->range_min_qp = dsi_dsc_rc_range_min_qp_1_1;
- dsc->range_max_qp = dsi_dsc_rc_range_max_qp_1_1;
- }
- dsc->range_bpg_offset = dsi_dsc_rc_range_bpg_offset;
bpp = dsc->bpp;
bpc = dsc->bpc;
+ if (bpc == 12)
+ ratio_index = DSC_12BPC_8BPP;
+ else if (bpc == 10)
+ ratio_index = DSC_10BPC_8BPP;
+ else
+ ratio_index = DSC_8BPC_8BPP;
+
+ if (dsc->version == 0x11 && dsc->scr_rev == 0x1) {
+ dsc->range_min_qp =
+ dsi_dsc_rc_range_min_qp_1_1_scr1[ratio_index];
+ dsc->range_max_qp =
+ dsi_dsc_rc_range_max_qp_1_1_scr1[ratio_index];
+ } else {
+ dsc->range_min_qp = dsi_dsc_rc_range_min_qp_1_1[ratio_index];
+ dsc->range_max_qp = dsi_dsc_rc_range_max_qp_1_1[ratio_index];
+ }
+ dsc->range_bpg_offset = dsi_dsc_rc_range_bpg_offset;
+
if (bpp == 8)
dsc->initial_offset = 6144;
else
dsc->initial_offset = 2048; /* bpp = 12 */
- if (bpc <= 8)
- mux_words_size = 48;
+ if (bpc == 12)
+ mux_words_size = 64;
else
- mux_words_size = 64; /* bpc == 12 */
+ mux_words_size = 48; /* bpc == 8/10 */
+
+ if (bpc == 8) {
+ dsc->line_buf_depth = 9;
+ dsc->input_10_bits = 0;
+ dsc->min_qp_flatness = 3;
+ dsc->max_qp_flatness = 12;
+ dsc->quant_incr_limit0 = 11;
+ dsc->quant_incr_limit1 = 11;
+ } else if (bpc == 10) { /* 10bpc */
+ dsc->line_buf_depth = 11;
+ dsc->input_10_bits = 1;
+ dsc->min_qp_flatness = 7;
+ dsc->max_qp_flatness = 16;
+ dsc->quant_incr_limit0 = 15;
+ dsc->quant_incr_limit1 = 15;
+ } else { /* 12 bpc */
+ dsc->line_buf_depth = 9;
+ dsc->input_10_bits = 0;
+ dsc->min_qp_flatness = 11;
+ dsc->max_qp_flatness = 20;
+ dsc->quant_incr_limit0 = 19;
+ dsc->quant_incr_limit1 = 19;
+ }
dsc->slice_last_group_size = 3 - (dsc->slice_width % 3);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
index 3569b5b..5380049 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
@@ -184,7 +184,8 @@
bool ulps_enabled;
bool allow_phy_power_off;
- u32 panel_jitter;
+ u32 panel_jitter_numer;
+ u32 panel_jitter_denom;
u32 panel_prefill_lines;
bool panel_initialized;
bool te_using_watchdog_timer;
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0be17b9..d2ac684 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -284,7 +284,7 @@
list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
- kthread_queue_work(&priv->event_thread[crtc_id].worker,
+ kthread_queue_work(&priv->disp_thread[crtc_id].worker,
&vbl_ctrl->work);
return 0;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 7edd534..96ab883 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -413,7 +413,8 @@
* @frame_rate: Display frame rate
* @prefill_lines: prefill lines based on porches.
* @vtotal: display vertical total
- * @jitter: display jitter configuration
+ * @jitter_numer: display panel jitter numerator configuration
+ * @jitter_denom: display panel jitter denominator configuration
* @comp_info: Compression supported by the display
* @roi_caps: Region of interest capability info
*/
@@ -437,7 +438,8 @@
uint32_t frame_rate;
uint32_t prefill_lines;
uint32_t vtotal;
- uint32_t jitter;
+ uint32_t jitter_numer;
+ uint32_t jitter_denom;
struct msm_compression_info comp_info;
struct msm_roi_caps roi_caps;
@@ -741,16 +743,34 @@
void msm_fbdev_free(struct drm_device *dev);
struct hdmi;
+#ifdef CONFIG_DRM_MSM_HDMI
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
struct drm_encoder *encoder);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);
+#else
+static inline void __init msm_hdmi_register(void)
+{
+}
+static inline void __exit msm_hdmi_unregister(void)
+{
+}
+#endif
struct msm_edp;
+#ifdef CONFIG_DRM_MSM_EDP
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
struct drm_encoder *encoder);
+#else
+static inline void __init msm_edp_register(void)
+{
+}
+static inline void __exit msm_edp_unregister(void)
+{
+}
+#endif
struct msm_dsi;
enum msm_dsi_encoder_id {
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 35e6b71..7692bef 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -115,9 +115,24 @@
static inline
struct msm_kms *mdp4_kms_init(struct drm_device *dev) { return NULL; };
#endif
-struct msm_kms *mdp5_kms_init(struct drm_device *dev);
+
+#ifdef CONFIG_DRM_MSM_MDP5
int msm_mdss_init(struct drm_device *dev);
void msm_mdss_destroy(struct drm_device *dev);
+struct msm_kms *mdp5_kms_init(struct drm_device *dev);
+#else
+static inline int msm_mdss_init(struct drm_device *dev)
+{
+ return 0;
+}
+static inline void msm_mdss_destroy(struct drm_device *dev)
+{
+}
+static inline struct msm_kms *mdp5_kms_init(struct drm_device *dev)
+{
+ return NULL;
+}
+#endif
struct msm_kms *sde_kms_init(struct drm_device *dev);
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_ad4.h b/drivers/gpu/drm/msm/sde/sde_ad4.h
index 4a664a8..5a646e9 100644
--- a/drivers/gpu/drm/msm/sde/sde_ad4.h
+++ b/drivers/gpu/drm/msm/sde/sde_ad4.h
@@ -48,6 +48,9 @@
AD_SUSPEND,
AD_ASSERTIVE,
AD_BACKLIGHT,
+ AD_IPC_SUSPEND,
+ AD_IPC_RESUME,
+ AD_IPC_RESET,
AD_PROPMAX,
};
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
index 0fc982e..9409066 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.c
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -74,6 +74,9 @@
static void sde_cp_notify_ad_event(struct drm_crtc *crtc_drm, void *arg);
+static void sde_cp_ad_set_prop(struct sde_crtc *sde_crtc,
+ enum ad_property ad_prop);
+
#define setup_dspp_prop_install_funcs(func) \
do { \
func[SDE_DSPP_PCC] = dspp_pcc_install_property; \
@@ -753,6 +756,7 @@
DRM_DEBUG_DRIVER("Dirty list is empty\n");
return;
}
+ sde_cp_ad_set_prop(sde_crtc, AD_IPC_RESET);
set_dspp_flush = true;
}
@@ -1457,3 +1461,61 @@
exit:
return ret;
}
+
+static void sde_cp_ad_set_prop(struct sde_crtc *sde_crtc,
+ enum ad_property ad_prop)
+{
+ struct sde_ad_hw_cfg ad_cfg;
+ struct sde_hw_cp_cfg hw_cfg;
+ struct sde_hw_dspp *hw_dspp = NULL;
+ struct sde_hw_mixer *hw_lm = NULL;
+ u32 num_mixers = sde_crtc->num_mixers;
+ int i = 0, ret = 0;
+
+ hw_cfg.num_of_mixers = sde_crtc->num_mixers;
+ hw_cfg.displayh = sde_crtc->base.mode.hdisplay;
+ hw_cfg.displayv = sde_crtc->base.mode.vdisplay;
+
+ for (i = 0; i < num_mixers && !ret; i++) {
+ hw_lm = sde_crtc->mixers[i].hw_lm;
+ hw_dspp = sde_crtc->mixers[i].hw_dspp;
+ if (!hw_lm || !hw_dspp || !hw_dspp->ops.validate_ad ||
+ !hw_dspp->ops.setup_ad) {
+ ret = -EINVAL;
+ continue;
+ }
+
+ hw_cfg.mixer_info = hw_lm;
+ ad_cfg.prop = ad_prop;
+ ad_cfg.hw_cfg = &hw_cfg;
+ ret = hw_dspp->ops.validate_ad(hw_dspp, (u32 *)&ad_prop);
+ if (!ret)
+ hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
+ }
+}
+
+void sde_cp_crtc_pre_ipc(struct drm_crtc *drm_crtc)
+{
+ struct sde_crtc *sde_crtc;
+
+ sde_crtc = to_sde_crtc(drm_crtc);
+ if (!sde_crtc) {
+ DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+ return;
+ }
+
+ sde_cp_ad_set_prop(sde_crtc, AD_IPC_SUSPEND);
+}
+
+void sde_cp_crtc_post_ipc(struct drm_crtc *drm_crtc)
+{
+ struct sde_crtc *sde_crtc;
+
+ sde_crtc = to_sde_crtc(drm_crtc);
+ if (!sde_crtc) {
+ DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
+ return;
+ }
+
+ sde_cp_ad_set_prop(sde_crtc, AD_IPC_RESUME);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h
index e78f690..08e345d 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.h
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h
@@ -103,4 +103,18 @@
*/
int sde_cp_ad_interrupt(struct drm_crtc *crtc, bool en,
struct sde_irq_callback *irq);
+
+/**
+ * sde_cp_crtc_pre_ipc: Handle color processing features
+ * before entering IPC
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_pre_ipc(struct drm_crtc *crtc);
+
+/**
+ * sde_cp_crtc_post_ipc: Handle color processing features
+ * after exiting IPC
+ * @crtc: Pointer to crtc.
+ */
+void sde_cp_crtc_post_ipc(struct drm_crtc *crtc);
#endif /*_SDE_COLOR_PROCESSING_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c
index 6c9d496..e87058e 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.c
+++ b/drivers/gpu/drm/msm/sde/sde_connector.c
@@ -886,7 +886,8 @@
sde_fence_prepare(&to_sde_connector(connector)->retire_fence);
}
-void sde_connector_complete_commit(struct drm_connector *connector)
+void sde_connector_complete_commit(struct drm_connector *connector,
+ ktime_t ts)
{
if (!connector) {
SDE_ERROR("invalid connector\n");
@@ -894,7 +895,7 @@
}
/* signal connector's retire fence */
- sde_fence_signal(&to_sde_connector(connector)->retire_fence, 0);
+ sde_fence_signal(&to_sde_connector(connector)->retire_fence, ts, 0);
}
static enum drm_connector_status
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h
index 8e46a11..8796c52 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.h
+++ b/drivers/gpu/drm/msm/sde/sde_connector.h
@@ -406,8 +406,9 @@
/**
* sde_connector_complete_commit - signal completion of current commit
* @connector: Pointer to drm connector object
+ * @ts: timestamp to be updated in the fence signalling
*/
-void sde_connector_complete_commit(struct drm_connector *connector);
+void sde_connector_complete_commit(struct drm_connector *connector, ktime_t ts);
/**
* sde_connector_get_info - query display specific information
diff --git a/drivers/gpu/drm/msm/sde/sde_core_irq.c b/drivers/gpu/drm/msm/sde/sde_core_irq.c
index cec2b5f..dfdfc1a 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_irq.c
+++ b/drivers/gpu/drm/msm/sde/sde_core_irq.c
@@ -34,8 +34,12 @@
pr_debug("irq_idx=%d\n", irq_idx);
- if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
+ if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
SDE_ERROR("irq_idx=%d has no registered callback\n", irq_idx);
+ SDE_EVT32_IRQ(irq_idx, atomic_read(
+ &sde_kms->irq_obj.enable_counts[irq_idx]),
+ SDE_EVTLOG_ERROR);
+ }
atomic_inc(&irq_obj->irq_counts[irq_idx]);
@@ -53,7 +57,7 @@
* NOTE: sde_core_irq_callback_handler is protected by top-level
* spinlock, so it is safe to clear any interrupt status here.
*/
- sde_kms->hw_intr->ops.clear_interrupt_status(
+ sde_kms->hw_intr->ops.clear_intr_status_nolock(
sde_kms->hw_intr,
irq_idx);
}
@@ -94,7 +98,6 @@
SDE_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
- spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
SDE_EVT32(irq_idx,
atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_inc_return(&sde_kms->irq_obj.enable_counts[irq_idx]) == 1) {
@@ -107,26 +110,33 @@
SDE_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
+ spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
/* empty callback list but interrupt is enabled */
if (list_empty(&sde_kms->irq_obj.irq_cb_tbl[irq_idx]))
SDE_ERROR("irq_idx=%d enabled with no callback\n",
irq_idx);
+ spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
}
- spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
return ret;
}
int sde_core_irq_enable(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count)
{
- int i;
- int ret = 0;
+ int i, ret = 0, counts;
if (!sde_kms || !irq_idxs || !irq_count) {
SDE_ERROR("invalid params\n");
return -EINVAL;
}
+ counts = atomic_read(&sde_kms->irq_obj.enable_counts[irq_idxs[0]]);
+ if (counts) {
+ SDE_ERROR("%pS: irq_idx=%d enable_count=%d\n",
+ __builtin_return_address(0), irq_idxs[0], counts);
+ SDE_EVT32(irq_idxs[0], counts, SDE_EVTLOG_ERROR);
+ }
+
for (i = 0; (i < irq_count) && !ret; i++)
ret = _sde_core_irq_enable(sde_kms, irq_idxs[i]);
@@ -140,7 +150,6 @@
*/
static int _sde_core_irq_disable(struct sde_kms *sde_kms, int irq_idx)
{
- unsigned long irq_flags;
int ret = 0;
if (!sde_kms || !sde_kms->hw_intr || !sde_kms->irq_obj.enable_counts) {
@@ -156,7 +165,6 @@
SDE_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
- spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags);
SDE_EVT32(irq_idx,
atomic_read(&sde_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_dec_return(&sde_kms->irq_obj.enable_counts[irq_idx]) == 0) {
@@ -168,27 +176,48 @@
irq_idx);
SDE_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
}
- spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags);
return ret;
}
int sde_core_irq_disable(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count)
{
- int i;
- int ret = 0;
+ int i, ret = 0, counts;
if (!sde_kms || !irq_idxs || !irq_count) {
SDE_ERROR("invalid params\n");
return -EINVAL;
}
+ counts = atomic_read(&sde_kms->irq_obj.enable_counts[irq_idxs[0]]);
+ if (counts == 2) {
+ SDE_ERROR("%pS: irq_idx=%d enable_count=%d\n",
+ __builtin_return_address(0), irq_idxs[0], counts);
+ SDE_EVT32(irq_idxs[0], counts, SDE_EVTLOG_ERROR);
+ }
+
for (i = 0; (i < irq_count) && !ret; i++)
ret = _sde_core_irq_disable(sde_kms, irq_idxs[i]);
return ret;
}
+u32 sde_core_irq_read_nolock(struct sde_kms *sde_kms, int irq_idx, bool clear)
+{
+ if (!sde_kms || !sde_kms->hw_intr ||
+ !sde_kms->hw_intr->ops.get_interrupt_status)
+ return 0;
+
+ if (irq_idx < 0) {
+ SDE_ERROR("[%pS] invalid irq_idx=%d\n",
+ __builtin_return_address(0), irq_idx);
+ return 0;
+ }
+
+ return sde_kms->hw_intr->ops.get_intr_status_nolock(sde_kms->hw_intr,
+ irq_idx, clear);
+}
+
u32 sde_core_irq_read(struct sde_kms *sde_kms, int irq_idx, bool clear)
{
if (!sde_kms || !sde_kms->hw_intr ||
@@ -210,12 +239,19 @@
{
unsigned long irq_flags;
- if (!sde_kms || !register_irq_cb || !register_irq_cb->func ||
- !sde_kms->irq_obj.irq_cb_tbl) {
+ if (!sde_kms || !sde_kms->irq_obj.irq_cb_tbl) {
SDE_ERROR("invalid params\n");
return -EINVAL;
}
+ if (!register_irq_cb || !register_irq_cb->func) {
+ SDE_ERROR("invalid irq_cb:%d func:%d\n",
+ register_irq_cb != NULL,
+ register_irq_cb ?
+ register_irq_cb->func != NULL : -1);
+ return -EINVAL;
+ }
+
if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
@@ -238,12 +274,19 @@
{
unsigned long irq_flags;
- if (!sde_kms || !register_irq_cb || !register_irq_cb->func ||
- !sde_kms->irq_obj.irq_cb_tbl) {
+ if (!sde_kms || !sde_kms->irq_obj.irq_cb_tbl) {
SDE_ERROR("invalid params\n");
return -EINVAL;
}
+ if (!register_irq_cb || !register_irq_cb->func) {
+ SDE_ERROR("invalid irq_cb:%d func:%d\n",
+ register_irq_cb != NULL,
+ register_irq_cb ?
+ register_irq_cb->func != NULL : -1);
+ return -EINVAL;
+ }
+
if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) {
SDE_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
diff --git a/drivers/gpu/drm/msm/sde/sde_core_irq.h b/drivers/gpu/drm/msm/sde/sde_core_irq.h
index c775f8c..c32c19c 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_irq.h
+++ b/drivers/gpu/drm/msm/sde/sde_core_irq.h
@@ -114,6 +114,18 @@
bool clear);
/**
+ * sde_core_irq_read - no lock version of sde_core_irq_read
+ * @sde_kms: SDE handle
+ * @irq_idx: irq index
+ * @clear: True to clear the irq after read
+ * @return: non-zero if irq detected; otherwise no irq detected
+ */
+u32 sde_core_irq_read_nolock(
+ struct sde_kms *sde_kms,
+ int irq_idx,
+ bool clear);
+
+/**
* sde_core_irq_register_callback - For registering callback function on IRQ
* interrupt
* @sde_kms: SDE handle
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 6bc1309..ff802e6 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -1520,6 +1520,8 @@
struct sde_crtc_state *cstate;
struct sde_kms *sde_kms;
unsigned long flags;
+ bool frame_done = false;
+ int i;
if (!work) {
SDE_ERROR("invalid work handle\n");
@@ -1542,13 +1544,16 @@
return;
}
priv = sde_kms->dev->dev_private;
+ SDE_ATRACE_BEGIN("crtc_frame_event");
SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
ktime_to_ns(fevent->ts));
- if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE ||
- (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR) ||
- (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
+ SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
+
+ if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE
+ | SDE_ENCODER_FRAME_EVENT_ERROR
+ | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
if (atomic_read(&sde_crtc->frame_pending) < 1) {
/* this should not happen */
@@ -1571,26 +1576,39 @@
SDE_EVTLOG_FUNC_CASE3);
}
- if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE ||
- (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR))
- complete_all(&sde_crtc->frame_done_comp);
-
- if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE)
+ if (fevent->event & SDE_ENCODER_FRAME_EVENT_DONE)
sde_core_perf_crtc_update(crtc, 0, false);
- } else {
- SDE_ERROR("crtc%d ts:%lld unknown event %u\n", crtc->base.id,
- ktime_to_ns(fevent->ts),
- fevent->event);
- SDE_EVT32(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_CASE4);
+
+ if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE
+ | SDE_ENCODER_FRAME_EVENT_ERROR))
+ frame_done = true;
+ }
+
+ if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
+ SDE_ATRACE_BEGIN("signal_release_fence");
+ sde_fence_signal(&sde_crtc->output_fence, fevent->ts, 0);
+ SDE_ATRACE_END("signal_release_fence");
+ }
+
+ if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) {
+ SDE_ATRACE_BEGIN("signal_retire_fence");
+ for (i = 0; i < cstate->num_connectors; ++i)
+ sde_connector_complete_commit(cstate->connectors[i],
+ fevent->ts);
+ SDE_ATRACE_END("signal_retire_fence");
}
if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
crtc->base.id, ktime_to_ns(fevent->ts));
+ if (frame_done)
+ complete_all(&sde_crtc->frame_done_comp);
+
spin_lock_irqsave(&sde_crtc->spin_lock, flags);
list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+ SDE_ATRACE_END("crtc_frame_event");
}
static void sde_crtc_frame_event_cb(void *data, u32 event)
@@ -1633,30 +1651,6 @@
kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
}
-void sde_crtc_complete_commit(struct drm_crtc *crtc,
- struct drm_crtc_state *old_state)
-{
- struct sde_crtc *sde_crtc;
- struct sde_crtc_state *cstate;
- int i;
-
- if (!crtc || !crtc->state) {
- SDE_ERROR("invalid crtc\n");
- return;
- }
-
- sde_crtc = to_sde_crtc(crtc);
- cstate = to_sde_crtc_state(crtc->state);
- SDE_EVT32_VERBOSE(DRMID(crtc));
-
- /* signal release fence */
- sde_fence_signal(&sde_crtc->output_fence, 0);
-
- /* signal retire fence */
- for (i = 0; i < cstate->num_connectors; ++i)
- sde_connector_complete_commit(cstate->connectors[i]);
-}
-
/**
* _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
* @cstate: Pointer to sde crtc state
@@ -2131,6 +2125,7 @@
struct msm_drm_private *priv;
struct sde_kms *sde_kms;
struct sde_crtc_state *cstate;
+ int ret;
if (!crtc) {
SDE_ERROR("invalid argument\n");
@@ -2174,7 +2169,10 @@
}
/* wait for frame_event_done completion */
- if (_sde_crtc_wait_for_frame_done(crtc)) {
+ SDE_ATRACE_BEGIN("wait_for_frame_done_event");
+ ret = _sde_crtc_wait_for_frame_done(crtc);
+ SDE_ATRACE_END("wait_for_frame_done_event");
+ if (ret) {
SDE_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
crtc->base.id,
atomic_read(&sde_crtc->frame_pending));
@@ -2305,13 +2303,13 @@
}
/*
- * If the vblank refcount != 0, release a power reference on suspend
- * and take it back during resume (if it is still != 0).
+ * If the vblank is enabled, release a power reference on suspend
+ * and take it back during resume (if it is still enabled).
*/
if (sde_crtc->suspend == enable)
SDE_DEBUG("crtc%d suspend already set to %d, ignoring update\n",
crtc->base.id, enable);
- else if (atomic_read(&sde_crtc->vblank_refcount) != 0)
+ else if (sde_crtc->vblank_enable)
_sde_crtc_vblank_enable_nolock(sde_crtc, !enable);
sde_crtc->suspend = enable;
@@ -2406,25 +2404,15 @@
if (!sde_crtc) {
SDE_ERROR("invalid crtc\n");
return -EINVAL;
- } else if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) {
- SDE_DEBUG("crtc%d vblank enable\n", sde_crtc->base.base.id);
- if (!sde_crtc->suspend)
- _sde_crtc_vblank_enable_nolock(sde_crtc, true);
- } else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) {
- SDE_ERROR("crtc%d invalid vblank disable\n",
- sde_crtc->base.base.id);
- return -EINVAL;
- } else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) {
- SDE_DEBUG("crtc%d vblank disable\n", sde_crtc->base.base.id);
- if (!sde_crtc->suspend)
- _sde_crtc_vblank_enable_nolock(sde_crtc, false);
- } else {
- SDE_DEBUG("crtc%d vblank %s refcount:%d\n",
- sde_crtc->base.base.id,
- en ? "enable" : "disable",
- atomic_read(&sde_crtc->vblank_refcount));
}
+ if (!sde_crtc->base.enabled || sde_crtc->suspend)
+ SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->base.enabled, en,
+ sde_crtc->vblank_enable, sde_crtc->suspend);
+ else if (sde_crtc->vblank_enable != en)
+ _sde_crtc_vblank_enable_nolock(sde_crtc, en);
+ sde_crtc->vblank_enable = en;
+
return 0;
}
@@ -2454,6 +2442,7 @@
sde_encoder_virt_restore(encoder);
}
+ sde_cp_crtc_post_ipc(crtc);
event.type = DRM_EVENT_SDE_POWER;
event.length = sizeof(power_on);
@@ -2477,6 +2466,8 @@
power_on = 0;
msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
(u8 *)&power_on);
+ } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
+ sde_cp_crtc_pre_ipc(crtc);
}
mutex_unlock(&sde_crtc->crtc_lock);
@@ -2514,14 +2505,12 @@
crtc->base.id,
atomic_read(&sde_crtc->frame_pending));
- if (atomic_read(&sde_crtc->vblank_refcount) && !sde_crtc->suspend) {
- SDE_ERROR("crtc%d invalid vblank refcount\n",
+ if (sde_crtc->vblank_enable && !sde_crtc->suspend) {
+ SDE_DEBUG("crtc%d vblank left enabled at disable time\n",
crtc->base.id);
- SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->vblank_refcount),
- SDE_EVTLOG_FUNC_CASE1);
- while (atomic_read(&sde_crtc->vblank_refcount))
- if (_sde_crtc_vblank_no_lock(sde_crtc, false))
- break;
+ SDE_EVT32(DRMID(crtc), sde_crtc->vblank_enable,
+ SDE_EVTLOG_FUNC_CASE1);
+ _sde_crtc_vblank_enable_nolock(sde_crtc, false);
}
if (atomic_read(&sde_crtc->frame_pending)) {
@@ -2592,6 +2581,16 @@
sde_crtc_frame_event_cb, (void *)crtc);
}
+ mutex_lock(&sde_crtc->crtc_lock);
+ if (sde_crtc->vblank_enable) {
+ /* honor user vblank request on crtc while it was disabled */
+ SDE_DEBUG("%s vblank found enabled at crtc enable time\n",
+ sde_crtc->name);
+ SDE_EVT32(DRMID(crtc), sde_crtc->vblank_enable);
+ _sde_crtc_vblank_enable_nolock(sde_crtc, true);
+ }
+ mutex_unlock(&sde_crtc->crtc_lock);
+
spin_lock_irqsave(&sde_crtc->spin_lock, flags);
list_for_each_entry(node, &sde_crtc->user_event_list, list) {
ret = 0;
@@ -2605,7 +2604,8 @@
sde_crtc->power_event = sde_power_handle_register_event(
&priv->phandle,
- SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE,
+ SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
+ SDE_POWER_EVENT_PRE_DISABLE,
sde_crtc_handle_power_event, crtc, sde_crtc->name);
}
@@ -3271,8 +3271,10 @@
{
struct sde_crtc *sde_crtc;
struct sde_crtc_state *cstate;
+ struct drm_encoder *encoder;
int i, ret = -EINVAL;
bool conn_offset = 0;
+ bool is_cmd = true;
if (!crtc || !state) {
SDE_ERROR("invalid argument(s)\n");
@@ -3287,13 +3289,30 @@
break;
}
+ /**
+ * set the cmd flag only when all the encoders attached
+ * to the crtc are in cmd mode. Consider all other cases
+ * as video mode.
+ */
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc == crtc)
+ is_cmd &= sde_encoder_is_cmd_mode(encoder);
+ }
+
i = msm_property_index(&sde_crtc->property_info, property);
if (i == CRTC_PROP_OUTPUT_FENCE) {
uint32_t offset = sde_crtc_get_property(cstate,
CRTC_PROP_OUTPUT_FENCE_OFFSET);
+ /**
+ * set the offset to 0 only for cmd mode panels, so
+ * the release fence for the current frame can be
+ * triggered right after PP_DONE interrupt.
+ */
+ offset = is_cmd ? 0 : (offset + conn_offset);
+
ret = sde_fence_create(&sde_crtc->output_fence, val,
- offset + conn_offset);
+ offset);
if (ret)
SDE_ERROR("fence create failed\n");
} else {
@@ -3441,8 +3460,7 @@
sde_crtc->vblank_cb_time = ktime_set(0, 0);
}
- seq_printf(s, "vblank_refcount:%d\n",
- atomic_read(&sde_crtc->vblank_refcount));
+ seq_printf(s, "vblank_enable:%d\n", sde_crtc->vblank_enable);
mutex_unlock(&sde_crtc->crtc_lock);
@@ -3808,7 +3826,6 @@
crtc = &sde_crtc->base;
crtc->dev = dev;
- atomic_set(&sde_crtc->vblank_refcount, 0);
mutex_init(&sde_crtc->crtc_lock);
spin_lock_init(&sde_crtc->spin_lock);
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 0d72ff1..86b7855 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -30,7 +30,7 @@
#define SDE_CRTC_NAME_SIZE 12
/* define the maximum number of in-flight frame events */
-#define SDE_CRTC_FRAME_EVENT_SIZE 2
+#define SDE_CRTC_FRAME_EVENT_SIZE 4
/**
* enum sde_crtc_client_type: crtc client type
@@ -123,7 +123,7 @@
* @vblank_cb_count : count of vblank callback since last reset
* @play_count : frame count between crtc enable and disable
* @vblank_cb_time : ktime at vblank count reset
- * @vblank_refcount : reference count for vblank enable request
+ * @vblank_enable : whether the user has requested vblank events
* @suspend : whether or not a suspend operation is in progress
* @feature_list : list of color processing features supported on a crtc
* @active_list : list of color processing features are active
@@ -171,7 +171,7 @@
u32 vblank_cb_count;
u64 play_count;
ktime_t vblank_cb_time;
- atomic_t vblank_refcount;
+ bool vblank_enable;
bool suspend;
struct list_head feature_list;
@@ -369,14 +369,6 @@
struct drm_crtc_state *old_state);
/**
- * sde_crtc_complete_commit - callback signalling completion of current commit
- * @crtc: Pointer to drm crtc object
- * @old_state: Pointer to drm crtc old state object
- */
-void sde_crtc_complete_commit(struct drm_crtc *crtc,
- struct drm_crtc_state *old_state);
-
-/**
* sde_crtc_init - create a new crtc object
* @dev: sde device
* @plane: base plane
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index c713692..0f8c485 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -17,6 +17,7 @@
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/kthread.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/sde_rsc.h>
@@ -206,7 +207,7 @@
bool idle_pc_supported;
struct mutex rc_lock;
enum sde_enc_rc_states rc_state;
- struct delayed_work delayed_off_work;
+ struct kthread_delayed_work delayed_off_work;
struct msm_display_topology topology;
bool mode_set_complete;
@@ -417,6 +418,9 @@
sde_core_irq_unregister_callback(phys_enc->sde_kms,
irq->irq_idx, &irq->cb);
+
+ SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, SDE_EVTLOG_ERROR);
irq->irq_idx = -EINVAL;
return ret;
}
@@ -432,6 +436,7 @@
enum sde_intr_idx intr_idx)
{
struct sde_encoder_irq *irq;
+ int ret;
if (!phys_enc) {
SDE_ERROR("invalid encoder\n");
@@ -440,17 +445,32 @@
irq = &phys_enc->irq[intr_idx];
/* silently skip irqs that weren't registered */
- if (irq->irq_idx < 0)
+ if (irq->irq_idx < 0) {
+ SDE_ERROR(
+ "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
+ SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, SDE_EVTLOG_ERROR);
return 0;
+ }
- sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
- sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
+ ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
+ if (ret)
+ SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, ret, SDE_EVTLOG_ERROR);
+
+ ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
&irq->cb);
- irq->irq_idx = -EINVAL;
+ if (ret)
+ SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, ret, SDE_EVTLOG_ERROR);
SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
+ irq->irq_idx = -EINVAL;
+
return 0;
}
@@ -1143,7 +1163,8 @@
rsc_config.fps = disp_info->frame_rate;
rsc_config.vtotal = disp_info->vtotal;
rsc_config.prefill_lines = disp_info->prefill_lines;
- rsc_config.jitter = disp_info->jitter;
+ rsc_config.jitter_numer = disp_info->jitter_numer;
+ rsc_config.jitter_denom = disp_info->jitter_denom;
rsc_config.prefill_lines += config ?
config->inline_rotate_prefill : 0;
/* update it only once */
@@ -1248,12 +1269,22 @@
{
bool schedule_off = false;
struct sde_encoder_virt *sde_enc;
+ struct msm_drm_private *priv;
+ struct msm_drm_thread *disp_thread;
- if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
+ if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private ||
+ !drm_enc->crtc) {
SDE_ERROR("invalid parameters\n");
return -EINVAL;
}
sde_enc = to_sde_encoder_virt(drm_enc);
+ priv = drm_enc->dev->dev_private;
+
+ if (drm_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
+ SDE_ERROR("invalid crtc index\n");
+ return -EINVAL;
+ }
+ disp_thread = &priv->disp_thread[drm_enc->crtc->index];
/*
* when idle_pc is not supported, process only KICKOFF and STOP
@@ -1272,7 +1303,8 @@
switch (sw_event) {
case SDE_ENC_RC_EVENT_KICKOFF:
/* cancel delayed off work, if any */
- if (cancel_delayed_work_sync(&sde_enc->delayed_off_work))
+ if (kthread_cancel_delayed_work_sync(
+ &sde_enc->delayed_off_work))
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
sw_event);
@@ -1319,8 +1351,10 @@
}
/* schedule delayed off work */
- schedule_delayed_work(&sde_enc->delayed_off_work,
- msecs_to_jiffies(IDLE_TIMEOUT));
+ kthread_queue_delayed_work(
+ &disp_thread->worker,
+ &sde_enc->delayed_off_work,
+ msecs_to_jiffies(IDLE_TIMEOUT));
SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
SDE_EVTLOG_FUNC_CASE2);
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
@@ -1329,7 +1363,8 @@
case SDE_ENC_RC_EVENT_STOP:
/* cancel delayed off work, if any */
- if (cancel_delayed_work_sync(&sde_enc->delayed_off_work))
+ if (kthread_cancel_delayed_work_sync(
+ &sde_enc->delayed_off_work))
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
sw_event);
@@ -1353,6 +1388,7 @@
SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE3);
+
sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
mutex_unlock(&sde_enc->rc_lock);
@@ -1360,7 +1396,8 @@
case SDE_ENC_RC_EVENT_EARLY_WAKE_UP:
/* cancel delayed off work, if any */
- if (cancel_delayed_work_sync(&sde_enc->delayed_off_work)) {
+ if (kthread_cancel_delayed_work_sync(
+ &sde_enc->delayed_off_work)) {
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
sw_event);
schedule_off = true;
@@ -1398,7 +1435,9 @@
*/
if (schedule_off && !sde_crtc_frame_pending(drm_enc->crtc)) {
/* schedule delayed off work */
- schedule_delayed_work(&sde_enc->delayed_off_work,
+ kthread_queue_delayed_work(
+ &disp_thread->worker,
+ &sde_enc->delayed_off_work,
msecs_to_jiffies(IDLE_TIMEOUT));
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1413,6 +1452,22 @@
if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
sw_event, sde_enc->rc_state);
+ SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event,
+ sde_enc->rc_state);
+ mutex_unlock(&sde_enc->rc_lock);
+ return 0;
+ }
+
+ /*
+ * if we are in ON but a frame was just kicked off,
+ * ignore the IDLE event, it's probably a stale timer event
+ */
+ if (sde_enc->frame_busy_mask[0]) {
+ SDE_DEBUG_ENC(sde_enc,
+ "sw_event:%d, rc:%d frame pending\n",
+ sw_event, sde_enc->rc_state);
+ SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event,
+ sde_enc->rc_state);
mutex_unlock(&sde_enc->rc_lock);
return 0;
}
@@ -1436,11 +1491,10 @@
return 0;
}
-static void sde_encoder_off_work(struct work_struct *work)
+static void sde_encoder_off_work(struct kthread_work *work)
{
- struct delayed_work *dw = to_delayed_work(work);
- struct sde_encoder_virt *sde_enc = container_of(dw,
- struct sde_encoder_virt, delayed_off_work);
+ struct sde_encoder_virt *sde_enc = container_of(work,
+ struct sde_encoder_virt, delayed_off_work.work);
if (!sde_enc) {
SDE_ERROR("invalid sde encoder\n");
@@ -1856,27 +1910,41 @@
struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
unsigned int i;
- if (!sde_enc->frame_busy_mask[0]) {
- /* suppress frame_done without waiter, likely autorefresh */
- SDE_EVT32(DRMID(drm_enc), event, ready_phys->intf_idx);
- return;
- }
+ if (event & (SDE_ENCODER_FRAME_EVENT_DONE
+ | SDE_ENCODER_FRAME_EVENT_ERROR
+ | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
- /* One of the physical encoders has become idle */
- for (i = 0; i < sde_enc->num_phys_encs; i++)
- if (sde_enc->phys_encs[i] == ready_phys) {
- clear_bit(i, sde_enc->frame_busy_mask);
- SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
- sde_enc->frame_busy_mask[0]);
+ if (!sde_enc->frame_busy_mask[0]) {
+ /**
+ * suppress frame_done without waiter,
+ * likely autorefresh
+ */
+ SDE_EVT32(DRMID(drm_enc), event, ready_phys->intf_idx);
+ return;
}
- if (!sde_enc->frame_busy_mask[0]) {
- atomic_set(&sde_enc->frame_done_timeout, 0);
- del_timer(&sde_enc->frame_done_timer);
+ /* One of the physical encoders has become idle */
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ if (sde_enc->phys_encs[i] == ready_phys) {
+ clear_bit(i, sde_enc->frame_busy_mask);
+ SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
+ sde_enc->frame_busy_mask[0]);
+ }
+ }
- sde_encoder_resource_control(drm_enc,
- SDE_ENC_RC_EVENT_FRAME_DONE);
+ if (!sde_enc->frame_busy_mask[0]) {
+ atomic_set(&sde_enc->frame_done_timeout, 0);
+ del_timer(&sde_enc->frame_done_timer);
+ sde_encoder_resource_control(drm_enc,
+ SDE_ENC_RC_EVENT_FRAME_DONE);
+
+ if (sde_enc->crtc_frame_event_cb)
+ sde_enc->crtc_frame_event_cb(
+ sde_enc->crtc_frame_event_cb_data,
+ event);
+ }
+ } else {
if (sde_enc->crtc_frame_event_cb)
sde_enc->crtc_frame_event_cb(
sde_enc->crtc_frame_event_cb_data, event);
@@ -1917,6 +1985,9 @@
pending_kickoff_cnt = sde_encoder_phys_inc_pending(phys);
+ if (phys->ops.is_master && phys->ops.is_master(phys))
+ atomic_inc(&phys->pending_retire_fence_cnt);
+
if (extra_flush_bits && ctl->ops.update_pending_flush)
ctl->ops.update_pending_flush(ctl, extra_flush_bits);
@@ -2319,6 +2390,7 @@
SDE_EVT32(DRMID(drm_enc));
/* prepare for next kickoff, may include waiting on previous kickoff */
+ SDE_ATRACE_BEGIN("enc_prepare_for_kickoff");
for (i = 0; i < sde_enc->num_phys_encs; i++) {
phys = sde_enc->phys_encs[i];
if (phys) {
@@ -2329,6 +2401,7 @@
_sde_encoder_setup_dither(phys);
}
}
+ SDE_ATRACE_END("enc_prepare_for_kickoff");
sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
@@ -3019,7 +3092,8 @@
}
mutex_init(&sde_enc->rc_lock);
- INIT_DELAYED_WORK(&sde_enc->delayed_off_work, sde_encoder_off_work);
+ kthread_init_delayed_work(&sde_enc->delayed_off_work,
+ sde_encoder_off_work);
memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
@@ -3062,7 +3136,9 @@
};
if (phys && fn_wait) {
+ SDE_ATRACE_BEGIN("wait_for_completion_event");
ret = fn_wait(phys);
+ SDE_ATRACE_END("wait_for_completion_event");
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index 9c2d3e9..3dae994 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -24,9 +24,11 @@
#include "msm_prop.h"
#include "sde_hw_mdss.h"
-#define SDE_ENCODER_FRAME_EVENT_DONE BIT(0)
-#define SDE_ENCODER_FRAME_EVENT_ERROR BIT(1)
-#define SDE_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2)
+#define SDE_ENCODER_FRAME_EVENT_DONE BIT(0)
+#define SDE_ENCODER_FRAME_EVENT_ERROR BIT(1)
+#define SDE_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2)
+#define SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE BIT(3)
+#define SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE BIT(4)
/**
* Encoder functions and data types
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index 4b12651..c1a40f5 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -235,6 +235,8 @@
* scheduled. Decremented in irq handler
* @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
* pending.
+ * @pending_retire_fence_cnt: Atomic counter tracking the pending retire
+ * fences that have to be signalled.
* @pending_kickoff_wq: Wait queue for blocking until kickoff completes
* @irq: IRQ tracking structures
*/
@@ -261,6 +263,7 @@
atomic_t underrun_cnt;
atomic_t pending_ctlstart_cnt;
atomic_t pending_kickoff_cnt;
+ atomic_t pending_retire_fence_cnt;
wait_queue_head_t pending_kickoff_wq;
struct sde_encoder_irq irq[INTR_IDX_MAX];
};
@@ -307,6 +310,8 @@
* @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt
* after ctl_start instead of before next frame kickoff
* @pp_timeout_report_cnt: number of pingpong done irq timeout errors
+ * @pending_rd_ptr_cnt: atomic counter to indicate if retire fence can be
+ * signaled at the next rd_ptr_irq
* @autorefresh: autorefresh feature state
*/
struct sde_encoder_phys_cmd {
@@ -315,6 +320,7 @@
bool serialize_wait4pp;
int pp_timeout_report_cnt;
struct sde_encoder_phys_cmd_autorefresh autorefresh;
+ atomic_t pending_rd_ptr_cnt;
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index da85257..2a46636 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -17,6 +17,7 @@
#include "sde_hw_interrupts.h"
#include "sde_core_irq.h"
#include "sde_formats.h"
+#include "sde_trace.h"
#define SDE_DEBUG_CMDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
@@ -160,24 +161,28 @@
struct sde_encoder_phys *phys_enc = arg;
unsigned long lock_flags;
int new_cnt;
+ u32 event = SDE_ENCODER_FRAME_EVENT_DONE |
+ SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
if (!phys_enc || !phys_enc->hw_pp)
return;
+ SDE_ATRACE_BEGIN("pp_done_irq");
/* notify all synchronous clients first, then asynchronous clients */
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
- phys_enc, SDE_ENCODER_FRAME_EVENT_DONE);
+ phys_enc, event);
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
SDE_EVT32_IRQ(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0, new_cnt);
+ phys_enc->hw_pp->idx - PINGPONG_0, new_cnt, event);
/* Signal any waiting atomic commit thread */
wake_up_all(&phys_enc->pending_kickoff_wq);
+ SDE_ATRACE_END("pp_done_irq");
}
static void sde_encoder_phys_cmd_autorefresh_done_irq(void *arg, int irq_idx)
@@ -206,35 +211,88 @@
static void sde_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
{
struct sde_encoder_phys *phys_enc = arg;
+ struct sde_encoder_phys_cmd *cmd_enc;
+ bool signal_fence = false;
if (!phys_enc || !phys_enc->hw_pp)
return;
+ SDE_ATRACE_BEGIN("rd_ptr_irq");
+ cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
+
+ /**
+ * signal only for master,
+ * - when the ctl_start irq is done and incremented
+ * the pending_rd_ptr_cnt.
+ * - when ctl_start irq status bit is set. This handles the case
+ * where ctl_start status bit is set in hardware, but the interrupt
+ * is delayed due to some reason.
+ */
+ if (sde_encoder_phys_cmd_is_master(phys_enc) &&
+ atomic_read(&phys_enc->pending_retire_fence_cnt)) {
+
+ if (atomic_add_unless(
+ &cmd_enc->pending_rd_ptr_cnt, -1, 0)) {
+ signal_fence = true;
+ } else {
+ signal_fence =
+ sde_core_irq_read_nolock(phys_enc->sde_kms,
+ phys_enc->irq[INTR_IDX_CTL_START].irq_idx,
+ false);
+ if (signal_fence)
+ SDE_EVT32_IRQ(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(
+ &phys_enc->pending_retire_fence_cnt),
+ SDE_EVTLOG_FUNC_CASE1);
+ }
+
+ if (signal_fence && phys_enc->parent_ops.handle_frame_done) {
+ atomic_add_unless(
+ &phys_enc->pending_retire_fence_cnt, -1, 0);
+ phys_enc->parent_ops.handle_frame_done(
+ phys_enc->parent, phys_enc,
+ SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE);
+ }
+ }
+
SDE_EVT32_IRQ(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0, 0xfff);
+ phys_enc->hw_pp->idx - PINGPONG_0, signal_fence, 0xfff);
if (phys_enc->parent_ops.handle_vblank_virt)
phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
phys_enc);
+
+ SDE_ATRACE_END("rd_ptr_irq");
}
static void sde_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
{
struct sde_encoder_phys *phys_enc = arg;
+ struct sde_encoder_phys_cmd *cmd_enc;
struct sde_hw_ctl *ctl;
- if (!phys_enc)
+ if (!phys_enc || !phys_enc->hw_ctl)
return;
- if (!phys_enc->hw_ctl)
- return;
+ SDE_ATRACE_BEGIN("ctl_start_irq");
+ cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
ctl = phys_enc->hw_ctl;
SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, 0xfff);
atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
+ /*
+ * this is required for the fence signalling to be done in rd_ptr_irq
+ * after ctrl_start_irq
+ */
+ if (sde_encoder_phys_cmd_is_master(phys_enc)
+ && atomic_read(&phys_enc->pending_retire_fence_cnt))
+ atomic_inc(&cmd_enc->pending_rd_ptr_cnt);
+
/* Signal any waiting ctl start interrupt */
wake_up_all(&phys_enc->pending_kickoff_wq);
+ SDE_ATRACE_END("ctl_start_irq");
}
static void sde_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
@@ -332,7 +390,8 @@
{
struct sde_encoder_phys_cmd *cmd_enc =
to_sde_encoder_phys_cmd(phys_enc);
- u32 frame_event = SDE_ENCODER_FRAME_EVENT_ERROR;
+ u32 frame_event = SDE_ENCODER_FRAME_EVENT_ERROR
+ | SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE;
bool do_log = false;
cmd_enc->pp_timeout_report_cnt++;
@@ -345,7 +404,8 @@
SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
cmd_enc->pp_timeout_report_cnt,
- atomic_read(&phys_enc->pending_kickoff_cnt));
+ atomic_read(&phys_enc->pending_kickoff_cnt),
+ frame_event);
/* to avoid flooding, only log first time, and "dead" time */
if (do_log) {
@@ -523,7 +583,6 @@
{
struct sde_encoder_phys_cmd *cmd_enc =
to_sde_encoder_phys_cmd(phys_enc);
- unsigned long lock_flags;
int ret = 0;
if (!phys_enc) {
@@ -539,8 +598,6 @@
__builtin_return_address(0),
enable, atomic_read(&phys_enc->vblank_refcount));
- spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-
SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
enable, atomic_read(&phys_enc->vblank_refcount));
@@ -550,8 +607,6 @@
ret = sde_encoder_helper_unregister_irq(phys_enc,
INTR_IDX_RDPTR);
- spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-
end:
if (ret)
SDE_ERROR_CMDENC(cmd_enc,
@@ -571,6 +626,9 @@
cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
+ SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
+ enable, atomic_read(&phys_enc->vblank_refcount));
+
if (enable) {
sde_encoder_helper_register_irq(phys_enc, INTR_IDX_PINGPONG);
sde_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
@@ -1230,6 +1288,8 @@
atomic_set(&phys_enc->vblank_refcount, 0);
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
+ atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
+ atomic_set(&cmd_enc->pending_rd_ptr_cnt, 0);
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
atomic_set(&cmd_enc->autorefresh.kickoff_cnt, 0);
init_waitqueue_head(&cmd_enc->autorefresh.kickoff_wq);
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index e34f46e..933e4812 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -16,6 +16,7 @@
#include "sde_core_irq.h"
#include "sde_formats.h"
#include "dsi_display.h"
+#include "sde_trace.h"
#define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
@@ -378,11 +379,25 @@
unsigned long lock_flags;
u32 flush_register = 0;
int new_cnt = -1, old_cnt = -1;
+ u32 event = 0;
if (!phys_enc)
return;
hw_ctl = phys_enc->hw_ctl;
+ SDE_ATRACE_BEGIN("vblank_irq");
+
+ /* signal only for master, where there is a pending kickoff */
+ if (sde_encoder_phys_vid_is_master(phys_enc)
+ && atomic_add_unless(
+ &phys_enc->pending_retire_fence_cnt, -1, 0)) {
+ event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE
+ | SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE;
+
+ if (phys_enc->parent_ops.handle_frame_done)
+ phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
+ phys_enc, event);
+ }
if (phys_enc->parent_ops.handle_vblank_virt)
phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
@@ -405,10 +420,11 @@
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
SDE_EVT32_IRQ(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
- old_cnt, new_cnt, flush_register);
+ old_cnt, new_cnt, flush_register, event);
/* Signal any waiting atomic commit thread */
wake_up_all(&phys_enc->pending_kickoff_wq);
+ SDE_ATRACE_END("vblank_irq");
}
static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
@@ -505,7 +521,6 @@
{
int ret = 0;
struct sde_encoder_phys_vid *vid_enc;
- unsigned long lock_flags;
if (!phys_enc) {
SDE_ERROR("invalid encoder\n");
@@ -522,8 +537,6 @@
__builtin_return_address(0),
enable, atomic_read(&phys_enc->vblank_refcount));
- spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-
SDE_EVT32(DRMID(phys_enc->parent), enable,
atomic_read(&phys_enc->vblank_refcount));
@@ -533,8 +546,6 @@
ret = sde_encoder_helper_unregister_irq(phys_enc,
INTR_IDX_VSYNC);
- spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-
if (ret)
SDE_ERROR_VIDENC(vid_enc,
"control vblank irq error %d, enable %d\n",
@@ -948,6 +959,7 @@
atomic_set(&phys_enc->vblank_refcount, 0);
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+ atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
phys_enc->enable_state = SDE_ENC_DISABLED;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
index 875d99d..c95fb47 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -644,6 +644,7 @@
struct sde_encoder_phys_wb *wb_enc = arg;
struct sde_encoder_phys *phys_enc = &wb_enc->base;
struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+ u32 event = 0;
SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0,
wb_enc->frame_count);
@@ -652,12 +653,20 @@
if (phys_enc->enable_state == SDE_ENC_DISABLING)
goto complete;
+ event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE
+ | SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
+ | SDE_ENCODER_FRAME_EVENT_DONE;
+
+ atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0);
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
- phys_enc, SDE_ENCODER_FRAME_EVENT_DONE);
+ phys_enc, event);
- phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
- phys_enc);
+ if (phys_enc->parent_ops.handle_vblank_virt)
+ phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
+ phys_enc);
+
+ SDE_EVT32_IRQ(DRMID(phys_enc->parent), hw_wb->idx - WB_0, event);
complete:
complete_all(&wb_enc->wbdone_complete);
@@ -783,7 +792,7 @@
{
unsigned long ret;
struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
- u32 irq_status;
+ u32 irq_status, event = 0;
u64 wb_time = 0;
int rc = 0;
u32 timeout = max_t(u32, wb_enc->wbdone_timeout, KICKOFF_TIMEOUT_MS);
@@ -802,7 +811,6 @@
if (!ret) {
SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc),
wb_enc->frame_count);
-
irq_status = sde_core_irq_read(phys_enc->sde_kms,
wb_enc->irq_idx, true);
if (irq_status) {
@@ -812,10 +820,15 @@
} else {
SDE_ERROR("wb:%d kickoff timed out\n",
wb_enc->wb_dev->wb_idx - WB_0);
+ atomic_add_unless(
+ &phys_enc->pending_retire_fence_cnt, -1, 0);
+
+ event = SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE
+ | SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE
+ | SDE_ENCODER_FRAME_EVENT_ERROR;
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(
- phys_enc->parent, phys_enc,
- SDE_ENCODER_FRAME_EVENT_ERROR);
+ phys_enc->parent, phys_enc, event);
rc = -ETIMEDOUT;
}
}
@@ -844,7 +857,7 @@
}
SDE_EVT32(DRMID(phys_enc->parent), WBID(wb_enc), wb_enc->frame_count,
- wb_time);
+ wb_time, event, rc);
return rc;
}
@@ -1296,6 +1309,7 @@
phys_enc->intf_mode = INTF_MODE_WB_LINE;
phys_enc->intf_idx = p->intf_idx;
phys_enc->enc_spinlock = p->enc_spinlock;
+ atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
INIT_LIST_HEAD(&wb_enc->irq_cb.list);
/* create internal buffer for disable logic */
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.c b/drivers/gpu/drm/msm/sde/sde_fence.c
index bd9fdac..b654e5a 100644
--- a/drivers/gpu/drm/msm/sde/sde_fence.c
+++ b/drivers/gpu/drm/msm/sde/sde_fence.c
@@ -338,7 +338,7 @@
return rc;
}
-void sde_fence_signal(struct sde_fence_context *ctx, bool is_error)
+void sde_fence_signal(struct sde_fence_context *ctx, ktime_t ts, bool is_error)
{
unsigned long flags;
struct sde_fence *fc, *next;
@@ -358,16 +358,19 @@
if ((int)(ctx->done_count - ctx->commit_count) < 0) {
++ctx->done_count;
SDE_DEBUG("fence_signal:done count:%d commit count:%d\n",
- ctx->commit_count, ctx->done_count);
+ ctx->done_count, ctx->commit_count);
} else {
SDE_ERROR("extra signal attempt! done count:%d commit:%d\n",
ctx->done_count, ctx->commit_count);
+ SDE_EVT32(ctx->drm_id, ctx->done_count, ctx->commit_count,
+ ktime_to_us(ts), SDE_EVTLOG_FATAL);
spin_unlock_irqrestore(&ctx->lock, flags);
return;
}
spin_unlock_irqrestore(&ctx->lock, flags);
- SDE_EVT32(ctx->drm_id, ctx->done_count);
+ SDE_EVT32(ctx->drm_id, ctx->done_count, ctx->commit_count,
+ ktime_to_us(ts));
spin_lock(&ctx->list_lock);
if (list_empty(&ctx->fence_list_head)) {
@@ -382,6 +385,7 @@
list_for_each_entry_safe(fc, next, &local_list_head, fence_list) {
spin_lock_irqsave(&ctx->lock, flags);
+ fc->base.timestamp = ts;
is_signaled = fence_is_signaled_locked(&fc->base);
spin_unlock_irqrestore(&ctx->lock, flags);
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.h b/drivers/gpu/drm/msm/sde/sde_fence.h
index 207f29c..51afdae 100644
--- a/drivers/gpu/drm/msm/sde/sde_fence.h
+++ b/drivers/gpu/drm/msm/sde/sde_fence.h
@@ -127,9 +127,11 @@
/**
* sde_fence_signal - advance fence timeline to signal outstanding fences
* @fence: Pointer fence container
+ * @ts: fence timestamp
* @is_error: Set to non-zero if the commit didn't complete successfully
*/
-void sde_fence_signal(struct sde_fence_context *fence, bool is_error);
+void sde_fence_signal(struct sde_fence_context *fence, ktime_t ts,
+ bool is_error);
#else
static inline void *sde_sync_get(uint64_t fd)
{
@@ -168,7 +170,7 @@
}
static inline void sde_fence_signal(struct sde_fence_context *fence,
- bool is_error)
+ ktime_t ts, bool is_error)
{
/* do nothing */
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
index 35fc2b5..5307464 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
@@ -19,6 +19,7 @@
#define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input))
#define MERGE_WIDTH_RIGHT 6
#define MERGE_WIDTH_LEFT 5
+#define AD_IPC_FRAME_COUNT 2
enum ad4_ops_bitmask {
ad4_init = BIT(AD_INIT),
@@ -31,34 +32,66 @@
enum ad4_state {
ad4_state_idle,
ad4_state_run,
+ /* idle power collapse resume state */
+ ad4_state_ipcr,
ad4_state_max,
};
typedef int (*ad4_prop_setup)(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *ad);
+static int ad4_params_check(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+
+static int ad4_no_op_setup(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_mode_setup(struct sde_hw_dspp *dspp, enum ad4_modes mode);
static int ad4_mode_setup_common(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
+static int ad4_init_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg);
static int ad4_init_setup_idle(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
+static int ad4_init_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_init_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_cfg_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg);
static int ad4_cfg_setup_idle(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
+static int ad4_cfg_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_cfg_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_input_setup(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
static int ad4_input_setup_idle(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
-static int ad4_mode_setup(struct sde_hw_dspp *dspp, enum ad4_modes mode);
-static int ad4_init_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg);
-static int ad4_cfg_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg);
-static int ad4_input_setup(struct sde_hw_dspp *dspp,
+static int ad4_input_setup_ipcr(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
static int ad4_suspend_setup(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
-static int ad4_params_check(struct sde_hw_dspp *dspp,
- struct sde_ad_hw_cfg *cfg);
static int ad4_assertive_setup(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
static int ad4_backlight_setup(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg);
+static int ad4_ipc_suspend_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_ipc_resume_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_ipc_resume_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_ipc_reset_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_mem_init_enable(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_mem_init_disable(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_cfg_ipc_resume(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+static int ad4_cfg_ipc_reset(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg);
+
static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = {
[ad4_state_idle][AD_MODE] = ad4_mode_setup_common,
[ad4_state_idle][AD_INIT] = ad4_init_setup_idle,
@@ -67,13 +100,29 @@
[ad4_state_idle][AD_SUSPEND] = ad4_suspend_setup,
[ad4_state_idle][AD_ASSERTIVE] = ad4_assertive_setup,
[ad4_state_idle][AD_BACKLIGHT] = ad4_backlight_setup,
+ [ad4_state_idle][AD_IPC_SUSPEND] = ad4_no_op_setup,
+ [ad4_state_idle][AD_IPC_RESUME] = ad4_no_op_setup,
+ [ad4_state_idle][AD_IPC_RESET] = ad4_no_op_setup,
[ad4_state_run][AD_MODE] = ad4_mode_setup_common,
- [ad4_state_run][AD_INIT] = ad4_init_setup,
- [ad4_state_run][AD_CFG] = ad4_cfg_setup,
+ [ad4_state_run][AD_INIT] = ad4_init_setup_run,
+ [ad4_state_run][AD_CFG] = ad4_cfg_setup_run,
[ad4_state_run][AD_INPUT] = ad4_input_setup,
[ad4_state_run][AD_SUSPEND] = ad4_suspend_setup,
[ad4_state_run][AD_ASSERTIVE] = ad4_assertive_setup,
[ad4_state_run][AD_BACKLIGHT] = ad4_backlight_setup,
+ [ad4_state_run][AD_IPC_SUSPEND] = ad4_ipc_suspend_setup_run,
+ [ad4_state_run][AD_IPC_RESUME] = ad4_ipc_resume_setup_run,
+ [ad4_state_run][AD_IPC_RESET] = ad4_no_op_setup,
+ [ad4_state_ipcr][AD_MODE] = ad4_mode_setup_common,
+ [ad4_state_ipcr][AD_INIT] = ad4_init_setup_ipcr,
+ [ad4_state_ipcr][AD_CFG] = ad4_cfg_setup_ipcr,
+ [ad4_state_ipcr][AD_INPUT] = ad4_input_setup_ipcr,
+ [ad4_state_ipcr][AD_SUSPEND] = ad4_suspend_setup,
+ [ad4_state_ipcr][AD_ASSERTIVE] = ad4_assertive_setup,
+ [ad4_state_ipcr][AD_BACKLIGHT] = ad4_backlight_setup,
+ [ad4_state_ipcr][AD_IPC_SUSPEND] = ad4_no_op_setup,
+ [ad4_state_ipcr][AD_IPC_RESUME] = ad4_ipc_resume_setup_ipcr,
+ [ad4_state_ipcr][AD_IPC_RESET] = ad4_ipc_reset_setup_ipcr,
};
struct ad4_info {
@@ -81,14 +130,19 @@
u32 completed_ops_mask;
bool ad4_support;
enum ad4_modes cached_mode;
+ bool is_master;
+ u32 frame_count;
+ u32 tf_ctrl;
+ u32 vc_control_0;
+ u32 last_str;
u32 cached_als;
};
static struct ad4_info info[DSPP_MAX] = {
- [DSPP_0] = {ad4_state_idle, 0, true, AD4_OFF},
- [DSPP_1] = {ad4_state_idle, 0, true, AD4_OFF},
- [DSPP_2] = {ad4_state_max, 0, false, AD4_OFF},
- [DSPP_3] = {ad4_state_max, 0, false, AD4_OFF},
+ [DSPP_0] = {ad4_state_idle, 0, true, AD4_OFF, false},
+ [DSPP_1] = {ad4_state_idle, 0, true, AD4_OFF, false},
+ [DSPP_2] = {ad4_state_max, 0, false, AD4_OFF, false},
+ [DSPP_3] = {ad4_state_max, 0, false, AD4_OFF, false},
};
void sde_setup_dspp_ad4(struct sde_hw_dspp *dspp, void *ad_cfg)
@@ -118,7 +172,7 @@
return -EINVAL;
}
- if (dspp->idx > DSPP_MAX || !info[dspp->idx].ad4_support) {
+ if (dspp->idx >= DSPP_MAX || !info[dspp->idx].ad4_support) {
DRM_ERROR("ad4 not supported for dspp idx %d\n", dspp->idx);
return -EINVAL;
}
@@ -142,7 +196,7 @@
return -EINVAL;
}
- if (dspp->idx > DSPP_MAX || !info[dspp->idx].ad4_support) {
+ if (dspp->idx >= DSPP_MAX || !info[dspp->idx].ad4_support) {
DRM_ERROR("ad4 not supported for dspp idx %d\n", dspp->idx);
return -EINVAL;
}
@@ -170,6 +224,10 @@
return -EINVAL;
}
hw_lm = cfg->hw_cfg->mixer_info;
+ if (!hw_lm) {
+ DRM_ERROR("invalid mixer info\n");
+ return -EINVAL;
+ }
if (cfg->hw_cfg->num_of_mixers == 1 &&
hw_lm->cfg.out_height != cfg->hw_cfg->displayv &&
@@ -179,7 +237,7 @@
cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
return -EINVAL;
} else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv &&
- hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) {
+ hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) {
DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n",
hw_lm->cfg.out_height, hw_lm->cfg.out_width,
cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
@@ -189,6 +247,11 @@
return 0;
}
+static int ad4_no_op_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg)
+{
+ return 0;
+}
+
static int ad4_mode_setup(struct sde_hw_dspp *dspp, enum ad4_modes mode)
{
u32 blk_offset;
@@ -200,7 +263,8 @@
info[dspp->idx].state = ad4_state_idle;
info[dspp->idx].completed_ops_mask = 0;
} else {
- info[dspp->idx].state = ad4_state_run;
+ if (info[dspp->idx].state == ad4_state_idle)
+ info[dspp->idx].state = ad4_state_run;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
0x100);
}
@@ -235,6 +299,7 @@
proc_start = 0;
proc_end = 0xffff;
tile_ctl = 0;
+ info[dspp->idx].is_master = true;
} else {
tile_ctl = 0x5;
if (hw_lm->cfg.right_mixer) {
@@ -244,6 +309,7 @@
proc_start = (cfg->hw_cfg->displayh >> 1);
proc_end = frame_end;
tile_ctl |= 0x10;
+ info[dspp->idx].is_master = false;
} else {
frame_start = 0;
frame_end = (cfg->hw_cfg->displayh >> 1) +
@@ -251,23 +317,21 @@
proc_start = 0;
proc_end = (cfg->hw_cfg->displayh >> 1) - 1;
tile_ctl |= 0x10;
+ info[dspp->idx].is_master = true;
}
}
init = cfg->hw_cfg->payload;
- blk_offset = 8;
- SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- init->init_param_009);
blk_offset = 0xc;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- init->init_param_010);
+ init->init_param_010);
init->init_param_012 = cfg->hw_cfg->displayv & (BIT(17) - 1);
init->init_param_011 = cfg->hw_cfg->displayh & (BIT(17) - 1);
blk_offset = 0x10;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- ((init->init_param_011 << 16) | init->init_param_012));
+ ((init->init_param_011 << 16) | init->init_param_012));
blk_offset = 0x14;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
@@ -275,8 +339,8 @@
blk_offset = 0x44;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- ((((init->init_param_013) & (BIT(17) - 1)) << 16) |
- (init->init_param_014 & (BIT(17) - 1))));
+ ((((init->init_param_013) & (BIT(17) - 1)) << 16) |
+ (init->init_param_014 & (BIT(17) - 1))));
blk_offset = 0x5c;
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
@@ -583,23 +647,25 @@
val = (ad_cfg->cfg_param_004 & (BIT(16) - 1));
val |= ((ad_cfg->cfg_param_003 & (BIT(16) - 1)) << 16);
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
+
+ blk_offset = 0x20;
val = (ad_cfg->cfg_param_005 & (BIT(8) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
+ blk_offset = 0x24;
val = (ad_cfg->cfg_param_006 & (BIT(7) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
blk_offset = 0x30;
val = (ad_cfg->cfg_param_007 & (BIT(8) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_008 & (BIT(8) - 1));
- SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
+
+ info[dspp->idx].tf_ctrl = (ad_cfg->cfg_param_008 & (BIT(8) - 1));
+
+ blk_offset = 0x38;
val = (ad_cfg->cfg_param_009 & (BIT(10) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
+
+ blk_offset = 0x3c;
val = (ad_cfg->cfg_param_010 & (BIT(12) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
blk_offset += 4;
@@ -607,7 +673,6 @@
val |= (ad_cfg->cfg_param_012 & (BIT(16) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
blk_offset = 0x88;
val = (ad_cfg->cfg_param_013 & (BIT(8) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
@@ -697,14 +762,10 @@
blk_offset = 0x134;
val = (ad_cfg->cfg_param_040 & (BIT(12) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_041 & (BIT(7) - 1));
- SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset = 0x15c;
- val = (ad_cfg->cfg_param_042 & (BIT(10) - 1));
- SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
+ info[dspp->idx].vc_control_0 = (ad_cfg->cfg_param_041 & (BIT(7) - 1));
+
+ blk_offset += 160;
val = (ad_cfg->cfg_param_043 & (BIT(10) - 1));
SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
@@ -791,6 +852,52 @@
if (ret)
return ret;
+ ret = ad4_mem_init_enable(dspp, cfg);
+ if (ret)
+ return ret;
+
+ info[dspp->idx].completed_ops_mask |= ad4_init;
+
+ if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
+ ad4_mode_setup(dspp, info[dspp->idx].cached_mode);
+
+ return 0;
+}
+
+static int ad4_init_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_init;
+ return 0;
+ }
+
+ ret = ad4_init_setup(dspp, cfg);
+ if (ret)
+ return ret;
+ ret = ad4_mem_init_disable(dspp, cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int ad4_init_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_init;
+ return 0;
+ }
+
+ ret = ad4_init_setup(dspp, cfg);
+ if (ret)
+ return ret;
+
info[dspp->idx].completed_ops_mask |= ad4_init;
if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
@@ -812,6 +919,52 @@
ret = ad4_cfg_setup(dspp, cfg);
if (ret)
return ret;
+ ret = ad4_cfg_ipc_reset(dspp, cfg);
+ if (ret)
+ return ret;
+
+ info[dspp->idx].completed_ops_mask |= ad4_cfg;
+ if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
+ ad4_mode_setup(dspp, info[dspp->idx].cached_mode);
+ return 0;
+}
+
+static int ad4_cfg_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
+ return 0;
+ }
+
+ ret = ad4_cfg_setup(dspp, cfg);
+ if (ret)
+ return ret;
+ ret = ad4_cfg_ipc_reset(dspp, cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int ad4_cfg_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
+ return 0;
+ }
+
+ ret = ad4_cfg_setup(dspp, cfg);
+ if (ret)
+ return ret;
+ ret = ad4_cfg_ipc_resume(dspp, cfg);
+ if (ret)
+ return ret;
info[dspp->idx].completed_ops_mask |= ad4_cfg;
if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
@@ -835,6 +988,22 @@
return 0;
}
+static int ad4_input_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ ret = ad4_input_setup(dspp, cfg);
+ if (ret)
+ return ret;
+
+ info[dspp->idx].completed_ops_mask |= ad4_input;
+ if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
+ ad4_mode_setup(dspp, info[dspp->idx].cached_mode);
+
+ return 0;
+}
+
static int ad4_assertive_setup(struct sde_hw_dspp *dspp,
struct sde_ad_hw_cfg *cfg)
{
@@ -900,3 +1069,182 @@
break;
}
}
+
+static int ad4_ipc_suspend_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ u32 strength = 0, i = 0;
+ struct sde_hw_mixer *hw_lm;
+
+ hw_lm = cfg->hw_cfg->mixer_info;
+ if ((cfg->hw_cfg->num_of_mixers == 2) && hw_lm->cfg.right_mixer) {
+ /* this AD core is the salve core */
+ for (i = DSPP_0; i < DSPP_MAX; i++) {
+ if (info[i].is_master) {
+ strength = info[i].last_str;
+ break;
+ }
+ }
+ } else {
+ strength = SDE_REG_READ(&dspp->hw,
+ dspp->cap->sblk->ad.base + 0x4c);
+ }
+ info[dspp->idx].last_str = strength;
+
+ return 0;
+}
+
+static int ad4_ipc_resume_setup_run(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+
+ info[dspp->idx].state = ad4_state_ipcr;
+
+ info[dspp->idx].frame_count = 0;
+ ret = ad4_cfg_ipc_resume(dspp, cfg);
+
+ return ret;
+}
+
+static int ad4_ipc_resume_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ info[dspp->idx].frame_count = 0;
+ return 0;
+}
+
+static int ad4_ipc_reset_setup_ipcr(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ int ret;
+ u32 strength = 0, i = 0;
+ struct sde_hw_mixer *hw_lm;
+
+ /* Read AD calculator strength output during the 2 frames of manual
+ * strength mode, and assign the strength output to last_str
+ * when frame count reaches AD_IPC_FRAME_COUNT to avoid flickers
+ * caused by strength was not converged before entering IPC mode
+ */
+ hw_lm = cfg->hw_cfg->mixer_info;
+ if ((cfg->hw_cfg->num_of_mixers == 2) && hw_lm->cfg.right_mixer) {
+ /* this AD core is the salve core */
+ for (i = DSPP_0; i < DSPP_MAX; i++) {
+ if (info[i].is_master) {
+ strength = info[i].last_str;
+ break;
+ }
+ }
+ } else {
+ strength = SDE_REG_READ(&dspp->hw,
+ dspp->cap->sblk->ad.base + 0x4c);
+ }
+
+ if (info[dspp->idx].frame_count == AD_IPC_FRAME_COUNT) {
+ info[dspp->idx].state = ad4_state_run;
+ info[dspp->idx].last_str = strength;
+ ret = ad4_cfg_ipc_reset(dspp, cfg);
+ if (ret)
+ return ret;
+ } else {
+ info[dspp->idx].frame_count++;
+ }
+
+ return 0;
+}
+
+static int ad4_mem_init_enable(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ u32 blk_offset;
+ struct drm_msm_ad4_init *init;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_init;
+ return 0;
+ }
+
+ if (cfg->hw_cfg->len != sizeof(struct drm_msm_ad4_init)) {
+ DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
+ sizeof(struct drm_msm_ad4_init), cfg->hw_cfg->len,
+ cfg->hw_cfg->payload);
+ return -EINVAL;
+ }
+
+ init = cfg->hw_cfg->payload;
+ blk_offset = 0x8;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
+ (init->init_param_009 & 0xdfff));
+ blk_offset = 0x450;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 1);
+
+ return 0;
+}
+
+static int ad4_mem_init_disable(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ u32 blk_offset;
+ struct drm_msm_ad4_init *init;
+
+ if (!cfg->hw_cfg->payload) {
+ info[dspp->idx].completed_ops_mask &= ~ad4_init;
+ return 0;
+ }
+
+ if (cfg->hw_cfg->len != sizeof(struct drm_msm_ad4_init)) {
+ DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
+ sizeof(struct drm_msm_ad4_init), cfg->hw_cfg->len,
+ cfg->hw_cfg->payload);
+ return -EINVAL;
+ }
+
+ init = cfg->hw_cfg->payload;
+ blk_offset = 0x8;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
+ (init->init_param_009 | 0x2000));
+ blk_offset = 0x450;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0);
+
+ return 0;
+}
+
+static int ad4_cfg_ipc_resume(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ u32 blk_offset, val;
+
+ /* disable temporal filters */
+ blk_offset = 0x34;
+ val = (0x55 & (BIT(8) - 1));
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
+
+ /* set manual strength */
+ blk_offset = 0x15c;
+ val = (info[dspp->idx].last_str & (BIT(10) - 1));
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
+
+ /* enable manul mode */
+ blk_offset = 0x138;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0);
+
+ return 0;
+}
+
+static int ad4_cfg_ipc_reset(struct sde_hw_dspp *dspp,
+ struct sde_ad_hw_cfg *cfg)
+{
+ u32 blk_offset;
+
+ /* enable temporal filters */
+ blk_offset = 0x34;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
+ info[dspp->idx].tf_ctrl);
+
+ /* disable manul mode */
+ blk_offset = 0x138;
+ SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
+ info[dspp->idx].vc_control_0);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dsc.c b/drivers/gpu/drm/msm/sde/sde_hw_dsc.c
index 1a346f0..9fd3c25 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dsc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dsc.c
@@ -120,7 +120,6 @@
data |= dsc->max_qp_flatness << 5;
data |= dsc->min_qp_flatness;
SDE_REG_WRITE(dsc_c, DSC_FLATNESS, data);
- SDE_REG_WRITE(dsc_c, DSC_FLATNESS, 0x983);
data = dsc->rc_model_size;
SDE_REG_WRITE(dsc_c, DSC_RC_MODEL_SIZE, data);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
index 8c3d4fc..8eebf89fc 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
@@ -710,6 +710,9 @@
return;
SDE_REG_WRITE(&intr->hw, reg_off, mask);
+
+ /* ensure register writes go through */
+ wmb();
}
static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr,
@@ -731,7 +734,7 @@
* Now need to go through each IRQ status and find matching
* irq lookup index.
*/
- spin_lock_irqsave(&intr->status_lock, irq_flags);
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
for (reg_idx = 0; reg_idx < ARRAY_SIZE(sde_intr_set); reg_idx++) {
irq_status = intr->save_irq_status[reg_idx];
@@ -766,7 +769,7 @@
if (cbfunc)
cbfunc(arg, irq_idx);
else
- intr->ops.clear_interrupt_status(
+ intr->ops.clear_intr_status_nolock(
intr, irq_idx);
/*
@@ -777,7 +780,7 @@
irq_status &= ~sde_irq_map[irq_idx].irq_mask;
}
}
- spin_unlock_irqrestore(&intr->status_lock, irq_flags);
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
}
static int sde_hw_intr_enable_irq(struct sde_hw_intr *intr, int irq_idx)
@@ -801,7 +804,7 @@
reg_idx = irq->reg_idx;
reg = &sde_intr_set[reg_idx];
- spin_lock_irqsave(&intr->mask_lock, irq_flags);
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
cache_irq_mask = intr->cache_irq_mask[reg_idx];
if (cache_irq_mask & irq->irq_mask) {
dbgstr = "SDE IRQ already set:";
@@ -814,9 +817,12 @@
/* Enabling interrupts with the new mask */
SDE_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
+ /* ensure register write goes through */
+ wmb();
+
intr->cache_irq_mask[reg_idx] = cache_irq_mask;
}
- spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
irq->irq_mask, cache_irq_mask);
@@ -845,7 +851,7 @@
reg_idx = irq->reg_idx;
reg = &sde_intr_set[reg_idx];
- spin_lock_irqsave(&intr->mask_lock, irq_flags);
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
cache_irq_mask = intr->cache_irq_mask[reg_idx];
if ((cache_irq_mask & irq->irq_mask) == 0) {
dbgstr = "SDE IRQ is already cleared:";
@@ -858,9 +864,12 @@
/* Cleaning any pending interrupt */
SDE_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
+ /* ensure register write goes through */
+ wmb();
+
intr->cache_irq_mask[reg_idx] = cache_irq_mask;
}
- spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
irq->irq_mask, cache_irq_mask);
@@ -878,6 +887,9 @@
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off, 0xffffffff);
+ /* ensure register writes go through */
+ wmb();
+
return 0;
}
@@ -891,6 +903,9 @@
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
SDE_REG_WRITE(&intr->hw, sde_intr_set[i].en_off, 0x00000000);
+ /* ensure register writes go through */
+ wmb();
+
return 0;
}
@@ -926,7 +941,7 @@
if (!intr)
return;
- spin_lock_irqsave(&intr->status_lock, irq_flags);
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) {
/* Read interrupt status */
intr->save_irq_status[i] = SDE_REG_READ(&intr->hw,
@@ -943,25 +958,68 @@
/* Finally update IRQ status based on enable mask */
intr->save_irq_status[i] &= enable_mask;
}
- spin_unlock_irqrestore(&intr->status_lock, irq_flags);
+
+ /* ensure register writes go through */
+ wmb();
+
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
}
-static void sde_hw_intr_clear_interrupt_status(struct sde_hw_intr *intr,
+static void sde_hw_intr_clear_intr_status_nolock(struct sde_hw_intr *intr,
int irq_idx)
{
int reg_idx;
- unsigned long irq_flags;
if (!intr)
return;
- spin_lock_irqsave(&intr->mask_lock, irq_flags);
-
reg_idx = sde_irq_map[irq_idx].reg_idx;
SDE_REG_WRITE(&intr->hw, sde_intr_set[reg_idx].clr_off,
sde_irq_map[irq_idx].irq_mask);
- spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+ /* ensure register writes go through */
+ wmb();
+}
+
+static void sde_hw_intr_clear_interrupt_status(struct sde_hw_intr *intr,
+ int irq_idx)
+{
+ unsigned long irq_flags;
+
+ if (!intr)
+ return;
+
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
+ sde_hw_intr_clear_intr_status_nolock(intr, irq_idx);
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
+}
+
+static u32 sde_hw_intr_get_intr_status_nolock(struct sde_hw_intr *intr,
+ int irq_idx, bool clear)
+{
+ int reg_idx;
+ u32 intr_status;
+
+ if (!intr)
+ return 0;
+
+ if (irq_idx >= ARRAY_SIZE(sde_irq_map) || irq_idx < 0) {
+ pr_err("invalid IRQ index: [%d]\n", irq_idx);
+ return 0;
+ }
+
+ reg_idx = sde_irq_map[irq_idx].reg_idx;
+ intr_status = SDE_REG_READ(&intr->hw,
+ sde_intr_set[reg_idx].status_off) &
+ sde_irq_map[irq_idx].irq_mask;
+ if (intr_status && clear)
+ SDE_REG_WRITE(&intr->hw, sde_intr_set[reg_idx].clr_off,
+ intr_status);
+
+ /* ensure register writes go through */
+ wmb();
+
+ return intr_status;
}
static u32 sde_hw_intr_get_interrupt_status(struct sde_hw_intr *intr,
@@ -979,7 +1037,7 @@
return 0;
}
- spin_lock_irqsave(&intr->mask_lock, irq_flags);
+ spin_lock_irqsave(&intr->irq_lock, irq_flags);
reg_idx = sde_irq_map[irq_idx].reg_idx;
intr_status = SDE_REG_READ(&intr->hw,
@@ -989,7 +1047,10 @@
SDE_REG_WRITE(&intr->hw, sde_intr_set[reg_idx].clr_off,
intr_status);
- spin_unlock_irqrestore(&intr->mask_lock, irq_flags);
+ /* ensure register writes go through */
+ wmb();
+
+ spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
return intr_status;
}
@@ -1007,7 +1068,9 @@
ops->get_interrupt_sources = sde_hw_intr_get_interrupt_sources;
ops->get_interrupt_statuses = sde_hw_intr_get_interrupt_statuses;
ops->clear_interrupt_status = sde_hw_intr_clear_interrupt_status;
+ ops->clear_intr_status_nolock = sde_hw_intr_clear_intr_status_nolock;
ops->get_interrupt_status = sde_hw_intr_get_interrupt_status;
+ ops->get_intr_status_nolock = sde_hw_intr_get_intr_status_nolock;
}
static struct sde_mdss_base_cfg *__intr_offset(struct sde_mdss_cfg *m,
@@ -1059,8 +1122,7 @@
return ERR_PTR(-ENOMEM);
}
- spin_lock_init(&intr->mask_lock);
- spin_lock_init(&intr->status_lock);
+ spin_lock_init(&intr->irq_lock);
return intr;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
index aaba1be..ced4077 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
@@ -187,6 +187,15 @@
int irq_idx);
/**
+ * clear_intr_status_nolock() - clears the HW interrupts without lock
+ * @intr: HW interrupt handle
+ * @irq_idx: Lookup irq index return from irq_idx_lookup
+ */
+ void (*clear_intr_status_nolock)(
+ struct sde_hw_intr *intr,
+ int irq_idx);
+
+ /**
* get_interrupt_status - Gets HW interrupt status, and clear if set,
* based on given lookup IRQ index.
* @intr: HW interrupt handle
@@ -199,6 +208,17 @@
bool clear);
/**
+ * get_intr_status_nolock - nolock version of get_interrupt_status
+ * @intr: HW interrupt handle
+ * @irq_idx: Lookup irq index return from irq_idx_lookup
+ * @clear: True to clear irq after read
+ */
+ u32 (*get_intr_status_nolock)(
+ struct sde_hw_intr *intr,
+ int irq_idx,
+ bool clear);
+
+ /**
* get_valid_interrupts - Gets a mask of all valid interrupt sources
* within SDE. These are actually status bits
* within interrupt registers that specify the
@@ -232,8 +252,7 @@
* @cache_irq_mask: array of IRQ enable masks reg storage created during init
* @save_irq_status: array of IRQ status reg storage created during init
* @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
- * @mask_lock: spinlock for accessing IRQ mask
- * @status_lock: spinlock for accessing IRQ status
+ * @irq_lock: spinlock for accessing IRQ resources
*/
struct sde_hw_intr {
struct sde_hw_blk_reg_map hw;
@@ -241,8 +260,7 @@
u32 *cache_irq_mask;
u32 *save_irq_status;
u32 irq_idx_tbl_size;
- spinlock_t mask_lock;
- spinlock_t status_lock;
+ spinlock_t irq_lock;
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index b9fbd62..42af245 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -393,9 +393,6 @@
{
struct sde_kms *sde_kms;
struct msm_drm_private *priv;
- struct drm_crtc *crtc;
- struct drm_crtc_state *old_crtc_state;
- int i;
if (!kms || !old_state)
return;
@@ -405,8 +402,6 @@
return;
priv = sde_kms->dev->dev_private;
- for_each_crtc_in_state(old_state, crtc, old_crtc_state, i)
- sde_crtc_complete_commit(crtc, old_crtc_state);
sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
@@ -519,8 +514,10 @@
}
/* old_state actually contains updated crtc pointers */
- for_each_crtc_in_state(old_state, crtc, old_crtc_state, i)
- sde_crtc_prepare_commit(crtc, old_crtc_state);
+ for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+ if (crtc->state->active)
+ sde_crtc_prepare_commit(crtc, old_crtc_state);
+ }
}
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 20fca52..665315d 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -1753,6 +1753,15 @@
drm_rect_height(&rstate->out_rot_rect) >> 16,
rstate->out_rot_rect.x1 >> 16,
rstate->out_rot_rect.y1 >> 16);
+ SDE_EVT32_VERBOSE(DRMID(plane), rstate->sequence_id,
+ rstate->out_xpos, rstate->nplane,
+ in_rot->x1 >> 16, in_rot->y1 >> 16,
+ drm_rect_width(in_rot) >> 16,
+ drm_rect_height(in_rot) >> 16,
+ rstate->out_rot_rect.x1 >> 16,
+ rstate->out_rot_rect.y1 >> 16,
+ drm_rect_width(&rstate->out_rot_rect) >> 16,
+ drm_rect_height(&rstate->out_rot_rect) >> 16);
}
/**
@@ -1951,7 +1960,7 @@
struct sde_kms_fbo *fbo;
struct drm_framebuffer *fb;
- if (!plane || !cstate || !rstate)
+ if (!plane || !cstate || !rstate || !rstate->rot_hw)
return;
fbo = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
@@ -2014,27 +2023,6 @@
if (sde_plane_enabled(new_state) && !new_rstate->out_fb)
_sde_plane_rot_get_fb(plane, cstate, new_rstate);
- /* release buffer if output format configuration changes */
- if (new_rstate->out_fb &&
- ((new_rstate->out_fb_height != new_rstate->out_fb->height) ||
- (new_rstate->out_fb_width != new_rstate->out_fb->width) ||
- (new_rstate->out_fb_pixel_format !=
- new_rstate->out_fb->pixel_format) ||
- (new_rstate->out_fb_modifier[0] !=
- new_rstate->out_fb->modifier[0]) ||
- (new_rstate->out_fb_flags != new_rstate->out_fb->flags))) {
-
- SDE_DEBUG("plane%d.%d release fb/fbo\n", plane->base.id,
- new_rstate->sequence_id);
-
- sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
- (u64) &new_rstate->rot_hw->base);
- new_rstate->out_fb = NULL;
- sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
- (u64) &new_rstate->rot_hw->base);
- new_rstate->out_fbo = NULL;
- }
-
/* create new stream buffer if it is not available */
if (sde_plane_enabled(new_state) && !new_rstate->out_fb) {
u32 fb_w = drm_rect_width(&new_rstate->out_rot_rect) >> 16;
@@ -2069,6 +2057,8 @@
ret = -EINVAL;
goto error_create_fb;
}
+ SDE_EVT32_VERBOSE(DRMID(plane), new_rstate->sequence_id,
+ new_rstate->out_fb->base.id);
ret = sde_crtc_res_add(cstate, SDE_CRTC_RES_ROT_OUT_FB,
(u64) &new_rstate->rot_hw->base,
@@ -2222,22 +2212,24 @@
rstate->out_sbuf = psde->sbuf_mode || rstate->rot90;
if (sde_plane_enabled(state) && rstate->out_sbuf) {
- SDE_DEBUG("plane%d.%d acquire rotator\n",
- plane->base.id, rstate->sequence_id);
+ SDE_DEBUG("plane%d.%d acquire rotator, fb %d\n",
+ plane->base.id, rstate->sequence_id,
+ state->fb ? state->fb->base.id : -1);
hw_blk = sde_crtc_res_get(cstate, SDE_HW_BLK_ROT,
(u64) state->fb);
if (!hw_blk) {
- SDE_ERROR("plane%d no available rotator\n",
- plane->base.id);
+ SDE_ERROR("plane%d.%d no available rotator, fb %d\n",
+ plane->base.id, rstate->sequence_id,
+ state->fb ? state->fb->base.id : -1);
return -EINVAL;
}
rstate->rot_hw = to_sde_hw_rot(hw_blk);
if (!rstate->rot_hw->ops.commit) {
- SDE_ERROR("plane%d invalid rotator ops\n",
- plane->base.id);
+ SDE_ERROR("plane%d.%d invalid rotator ops\n",
+ plane->base.id, rstate->sequence_id);
sde_crtc_res_put(cstate,
SDE_HW_BLK_ROT, (u64) state->fb);
rstate->rot_hw = NULL;
@@ -2251,19 +2243,44 @@
}
if (sde_plane_enabled(state) && rstate->out_sbuf && rstate->rot_hw) {
+ uint32_t fb_id;
- SDE_DEBUG("plane%d.%d use rotator\n",
- plane->base.id, rstate->sequence_id);
+ fb_id = state->fb ? state->fb->base.id : -1;
+ SDE_DEBUG("plane%d.%d use rotator, fb %d\n",
+ plane->base.id, rstate->sequence_id, fb_id);
sde_plane_rot_calc_cfg(plane, state);
- /* attempt to reuse stream buffer if already available */
- if (sde_plane_enabled(state))
- _sde_plane_rot_get_fb(plane, cstate, rstate);
-
ret = sde_plane_rot_submit_command(plane, state,
SDE_HW_ROT_CMD_VALIDATE);
+ if (ret)
+ return ret;
+ /* check if stream buffer is already attached to rotator */
+ _sde_plane_rot_get_fb(plane, cstate, rstate);
+
+ /* release buffer if output format configuration changes */
+ if (rstate->out_fb &&
+ ((rstate->out_fb_height != rstate->out_fb->height) ||
+ (rstate->out_fb_width != rstate->out_fb->width) ||
+ (rstate->out_fb_pixel_format !=
+ rstate->out_fb->pixel_format) ||
+ (rstate->out_fb_modifier[0] !=
+ rstate->out_fb->modifier[0]) ||
+ (rstate->out_fb_flags != rstate->out_fb->flags))) {
+
+ SDE_DEBUG("plane%d.%d release fb/fbo\n", plane->base.id,
+ rstate->sequence_id);
+ SDE_EVT32_VERBOSE(DRMID(plane),
+ rstate->sequence_id, fb_id);
+
+ sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
+ (u64) &rstate->rot_hw->base);
+ rstate->out_fb = NULL;
+ sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
+ (u64) &rstate->rot_hw->base);
+ rstate->out_fbo = NULL;
+ }
} else {
SDE_DEBUG("plane%d.%d bypass rotator\n", plane->base.id,
@@ -2382,8 +2399,6 @@
{
struct sde_plane_state *pstate = to_sde_plane_state(new_state);
struct sde_plane_rot_state *rstate = &pstate->rot;
- struct drm_crtc_state *cstate;
- int ret;
rstate->sequence_id++;
@@ -2391,19 +2406,7 @@
rstate->sequence_id,
!!rstate->out_sbuf, !!rstate->rot_hw);
- cstate = _sde_plane_get_crtc_state(new_state);
- if (IS_ERR(cstate)) {
- ret = PTR_ERR(cstate);
- SDE_ERROR("invalid crtc state %d\n", ret);
- return -EINVAL;
- }
-
- if (rstate->rot_hw && cstate)
- sde_crtc_res_get(cstate, SDE_HW_BLK_ROT, (u64) rstate->in_fb);
- else if (rstate->rot_hw && !cstate)
- SDE_ERROR("plane%d.%d zombie rotator hw\n",
- plane->base.id, rstate->sequence_id);
-
+ rstate->rot_hw = NULL;
rstate->out_fb = NULL;
rstate->out_fbo = NULL;
@@ -3441,7 +3444,7 @@
}
if (psde->pipe_hw->ops.setup_sys_cache) {
- if (rstate->out_sbuf) {
+ if (rstate->out_sbuf && rstate->rot_hw) {
if (rstate->nplane < 2)
pstate->sc_cfg.op_mode =
SDE_PIPE_SC_OP_MODE_INLINE_SINGLE;
diff --git a/drivers/gpu/drm/msm/sde/sde_trace.h b/drivers/gpu/drm/msm/sde/sde_trace.h
index e233fc7..47fc39b 100644
--- a/drivers/gpu/drm/msm/sde/sde_trace.h
+++ b/drivers/gpu/drm/msm/sde/sde_trace.h
@@ -125,7 +125,7 @@
TP_printk("crtc:%d", __entry->crtc_id)
);
-TRACE_EVENT(sde_mark_write,
+TRACE_EVENT(tracing_mark_write,
TP_PROTO(int pid, const char *name, bool trace_begin),
TP_ARGS(pid, name, trace_begin),
TP_STRUCT__entry(
@@ -230,8 +230,8 @@
__entry->update_clk)
);
-#define SDE_ATRACE_END(name) trace_sde_mark_write(current->tgid, name, 0)
-#define SDE_ATRACE_BEGIN(name) trace_sde_mark_write(current->tgid, name, 1)
+#define SDE_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
+#define SDE_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define SDE_ATRACE_FUNC() SDE_ATRACE_BEGIN(__func__)
#define SDE_ATRACE_INT(name, value) \
diff --git a/drivers/gpu/drm/msm/sde_dbg.h b/drivers/gpu/drm/msm/sde_dbg.h
index 02d46c7..e14d60e 100644
--- a/drivers/gpu/drm/msm/sde_dbg.h
+++ b/drivers/gpu/drm/msm/sde_dbg.h
@@ -27,6 +27,7 @@
#define SDE_EVTLOG_FUNC_CASE5 0x7777
#define SDE_EVTLOG_PANIC 0xdead
#define SDE_EVTLOG_FATAL 0xbad
+#define SDE_EVTLOG_ERROR 0xebad
#define SDE_DBG_DUMP_DATA_LIMITER (NULL)
diff --git a/drivers/gpu/drm/msm/sde_rsc.c b/drivers/gpu/drm/msm/sde_rsc.c
index 9730f0b..54bdd42 100644
--- a/drivers/gpu/drm/msm/sde_rsc.c
+++ b/drivers/gpu/drm/msm/sde_rsc.c
@@ -46,8 +46,9 @@
#define RSC_TIME_SLOT_0_NS ((SINGLE_TCS_EXECUTION_TIME * 2) + 100)
#define DEFAULT_PANEL_FPS 60
-#define DEFAULT_PANEL_JITTER 5
-#define DEFAULT_PANEL_PREFILL_LINES 16
+#define DEFAULT_PANEL_JITTER_NUMERATOR 2
+#define DEFAULT_PANEL_JITTER_DENOMINATOR 1
+#define DEFAULT_PANEL_PREFILL_LINES 25
#define DEFAULT_PANEL_VTOTAL (480 + DEFAULT_PANEL_PREFILL_LINES)
#define TICKS_IN_NANO_SECOND 1000000000
@@ -57,6 +58,13 @@
#define TRY_CLK_MODE_SWITCH 0xFFFE
#define STATE_UPDATE_NOT_ALLOWED 0xFFFD
+/**
+ * Expected primary command mode panel vsync ranges
+ * Note: update if a primary panel is expected to run lower than 60fps
+ */
+#define PRIMARY_VBLANK_MIN_US (18 * 1000)
+#define PRIMARY_VBLANK_MAX_US (20 * 1000)
+
static struct sde_rsc_priv *rsc_prv_list[MAX_RSC_COUNT];
/**
@@ -320,21 +328,25 @@
/* calculate for 640x480 60 fps resolution by default */
if (!rsc->cmd_config.fps)
rsc->cmd_config.fps = DEFAULT_PANEL_FPS;
- if (!rsc->cmd_config.jitter)
- rsc->cmd_config.jitter = DEFAULT_PANEL_JITTER;
+ if (!rsc->cmd_config.jitter_numer)
+ rsc->cmd_config.jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR;
+ if (!rsc->cmd_config.jitter_denom)
+ rsc->cmd_config.jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR;
if (!rsc->cmd_config.vtotal)
rsc->cmd_config.vtotal = DEFAULT_PANEL_VTOTAL;
if (!rsc->cmd_config.prefill_lines)
rsc->cmd_config.prefill_lines = DEFAULT_PANEL_PREFILL_LINES;
- pr_debug("frame fps:%d jitter:%d vtotal:%d prefill lines:%d\n",
- rsc->cmd_config.fps, rsc->cmd_config.jitter,
- rsc->cmd_config.vtotal, rsc->cmd_config.prefill_lines);
+ pr_debug("frame fps:%d jitter_numer:%d jitter_denom:%d vtotal:%d prefill lines:%d\n",
+ rsc->cmd_config.fps, rsc->cmd_config.jitter_numer,
+ rsc->cmd_config.jitter_denom, rsc->cmd_config.vtotal,
+ rsc->cmd_config.prefill_lines);
/* 1 nano second */
frame_time_ns = TICKS_IN_NANO_SECOND;
frame_time_ns = div_u64(frame_time_ns, rsc->cmd_config.fps);
- frame_jitter = frame_time_ns * rsc->cmd_config.jitter;
+ frame_jitter = frame_time_ns * rsc->cmd_config.jitter_numer;
+ frame_jitter = div_u64(frame_jitter, rsc->cmd_config.jitter_denom);
/* convert it to percentage */
frame_jitter = div_u64(frame_jitter, 100);
@@ -477,8 +489,7 @@
/* wait for vsync for vid to cmd state switch and config update */
if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
rsc->current_state == SDE_RSC_CMD_STATE))
- drm_wait_one_vblank(rsc->master_drm,
- rsc->primary_client->crtc_id);
+ usleep_range(PRIMARY_VBLANK_MIN_US, PRIMARY_VBLANK_MAX_US);
end:
return rc;
}
@@ -502,8 +513,7 @@
/* wait for vsync for cmd to clk state switch */
if (!rc && rsc->primary_client &&
(rsc->current_state == SDE_RSC_CMD_STATE))
- drm_wait_one_vblank(rsc->master_drm,
- rsc->primary_client->crtc_id);
+ usleep_range(PRIMARY_VBLANK_MIN_US, PRIMARY_VBLANK_MAX_US);
end:
return rc;
}
@@ -532,8 +542,7 @@
/* wait for vsync for cmd to vid state switch */
if (!rc && rsc->primary_client &&
(rsc->current_state == SDE_RSC_CMD_STATE))
- drm_wait_one_vblank(rsc->master_drm,
- rsc->primary_client->crtc_id);
+ usleep_range(PRIMARY_VBLANK_MIN_US, PRIMARY_VBLANK_MAX_US);
end:
return rc;
@@ -749,8 +758,9 @@
rsc->timer_config.rsc_time_slot_0_ns);
seq_printf(s, "rsc time slot 1(ns):%d\n",
rsc->timer_config.rsc_time_slot_1_ns);
- seq_printf(s, "frame fps:%d jitter:%d vtotal:%d prefill lines:%d\n",
- rsc->cmd_config.fps, rsc->cmd_config.jitter,
+ seq_printf(s, "frame fps:%d jitter_numer:%d jitter_denom:%d vtotal:%d prefill lines:%d\n",
+ rsc->cmd_config.fps, rsc->cmd_config.jitter_numer,
+ rsc->cmd_config.jitter_denom,
rsc->cmd_config.vtotal, rsc->cmd_config.prefill_lines);
seq_puts(s, "\n");
diff --git a/drivers/gpu/drm/msm/sde_rsc_hw.c b/drivers/gpu/drm/msm/sde_rsc_hw.c
index 87a350e..26a3154 100644
--- a/drivers/gpu/drm/msm/sde_rsc_hw.c
+++ b/drivers/gpu/drm/msm/sde_rsc_hw.c
@@ -18,12 +18,14 @@
#include <linux/delay.h>
#include "sde_rsc_priv.h"
+#include "sde_dbg.h"
/* display rsc offset */
#define SDE_RSCC_PDC_SEQ_START_ADDR_REG_OFFSET_DRV0 0x020
#define SDE_RSCC_PDC_MATCH_VALUE_LO_REG_OFFSET_DRV0 0x024
#define SDE_RSCC_PDC_MATCH_VALUE_HI_REG_OFFSET_DRV0 0x028
#define SDE_RSCC_PDC_SLAVE_ID_DRV0 0x02c
+#define SDE_RSCC_SEQ_PROGRAM_COUNTER 0x408
#define SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0 0x410
#define SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0 0x414
#define SDE_RSCC_SEQ_MEM_0_DRV0 0x600
@@ -299,6 +301,7 @@
{
int rc = -EBUSY;
int count, reg;
+ unsigned long power_status;
rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_RESTORE);
@@ -335,9 +338,14 @@
/* make sure that mode-2 exit before wait*/
wmb();
- /* check for sequence running status before exiting */
+ /* this wait is required to make sure that gdsc is powered on */
for (count = MAX_CHECK_LOOPS; count > 0; count--) {
- if (regulator_is_enabled(rsc->fs)) {
+ power_status = dss_reg_r(&rsc->wrapper_io,
+ SDE_RSCC_PWR_CTRL, rsc->debug_mode);
+ if (!test_bit(POWER_CTRL_BIT_12, &power_status)) {
+ reg = dss_reg_r(&rsc->drv_io,
+ SDE_RSCC_SEQ_PROGRAM_COUNTER, rsc->debug_mode);
+ SDE_EVT32(count, reg, power_status);
rc = 0;
break;
}
@@ -415,7 +423,7 @@
rc = 0;
break;
}
- usleep_range(1, 2);
+ usleep_range(10, 100);
}
if (rc) {
diff --git a/drivers/input/misc/hbtp_input.c b/drivers/input/misc/hbtp_input.c
index c9ea89d..0dea590 100644
--- a/drivers/input/misc/hbtp_input.c
+++ b/drivers/input/misc/hbtp_input.c
@@ -1362,10 +1362,12 @@
ret = kstrtou32(buf, 10, &status);
if (ret) {
pr_err("hbtp: ret error: %zd\n", ret);
+ mutex_unlock(&hbtp->mutex);
return ret;
}
if (!hbtp || !hbtp->input_dev) {
pr_err("hbtp: hbtp or hbtp->input_dev not ready!\n");
+ mutex_unlock(&hbtp->mutex);
return ret;
}
if (status) {
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c
index 15b8a2d..ae01baf 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c
@@ -283,6 +283,59 @@
return;
}
+/*
+ * sde_mdp_set_vbif_memtype - set memtype output for the given xin port
+ * @mdata: pointer to global rotator data
+ * @xin_id: xin identifier
+ * @memtype: memtype output configuration
+ * return: none
+ */
+static void sde_mdp_set_vbif_memtype(struct sde_rot_data_type *mdata,
+ u32 xin_id, u32 memtype)
+{
+ u32 reg_off;
+ u32 bit_off;
+ u32 reg_val;
+
+ /*
+ * Assume 4 bits per bit field, 8 fields per 32-bit register.
+ */
+ if (xin_id >= 8)
+ return;
+
+ reg_off = MMSS_VBIF_NRT_VBIF_OUT_AXI_AMEMTYPE_CONF0;
+
+ bit_off = (xin_id & 0x7) * 4;
+ reg_val = SDE_VBIF_READ(mdata, reg_off);
+ reg_val &= ~(0x7 << bit_off);
+ reg_val |= (memtype & 0x7) << bit_off;
+ SDE_VBIF_WRITE(mdata, reg_off, reg_val);
+}
+
+/*
+ * sde_mdp_init_vbif - initialize static vbif configuration
+ * return: 0 if success; error code otherwise
+ */
+int sde_mdp_init_vbif(void)
+{
+ struct sde_rot_data_type *mdata = sde_rot_get_mdata();
+ int i;
+
+ if (!mdata)
+ return -EINVAL;
+
+ if (mdata->vbif_memtype_count && mdata->vbif_memtype) {
+ for (i = 0; i < mdata->vbif_memtype_count; i++)
+ sde_mdp_set_vbif_memtype(mdata, i,
+ mdata->vbif_memtype[i]);
+
+ SDEROT_DBG("amemtype=0x%x\n", SDE_VBIF_READ(mdata,
+ MMSS_VBIF_NRT_VBIF_OUT_AXI_AMEMTYPE_CONF0));
+ }
+
+ return 0;
+}
+
struct reg_bus_client *sde_reg_bus_vote_client_create(char *client_name)
{
struct reg_bus_client *client;
@@ -398,6 +451,32 @@
return len;
}
+static void sde_mdp_parse_vbif_memtype(struct platform_device *pdev,
+ struct sde_rot_data_type *mdata)
+{
+ int rc;
+
+ mdata->vbif_memtype_count = sde_mdp_parse_dt_prop_len(pdev,
+ "qcom,mdss-rot-vbif-memtype");
+ mdata->vbif_memtype = kzalloc(sizeof(u32) *
+ mdata->vbif_memtype_count, GFP_KERNEL);
+ if (!mdata->vbif_memtype) {
+ mdata->vbif_memtype_count = 0;
+ return;
+ }
+
+ rc = sde_mdp_parse_dt_handler(pdev,
+ "qcom,mdss-rot-vbif-memtype", mdata->vbif_memtype,
+ mdata->vbif_memtype_count);
+ if (rc) {
+ SDEROT_DBG("vbif memtype not found\n");
+ kfree(mdata->vbif_memtype);
+ mdata->vbif_memtype = NULL;
+ mdata->vbif_memtype_count = 0;
+ return;
+ }
+}
+
static void sde_mdp_parse_vbif_qos(struct platform_device *pdev,
struct sde_rot_data_type *mdata)
{
@@ -409,14 +488,19 @@
"qcom,mdss-rot-vbif-qos-setting");
mdata->vbif_nrt_qos = kzalloc(sizeof(u32) *
mdata->npriority_lvl, GFP_KERNEL);
- if (!mdata->vbif_nrt_qos)
+ if (!mdata->vbif_nrt_qos) {
+ mdata->npriority_lvl = 0;
return;
+ }
rc = sde_mdp_parse_dt_handler(pdev,
"qcom,mdss-rot-vbif-qos-setting", mdata->vbif_nrt_qos,
mdata->npriority_lvl);
if (rc) {
SDEROT_DBG("vbif setting not found\n");
+ kfree(mdata->vbif_nrt_qos);
+ mdata->vbif_nrt_qos = NULL;
+ mdata->npriority_lvl = 0;
return;
}
}
@@ -579,6 +663,8 @@
sde_mdp_parse_vbif_qos(pdev, mdata);
+ sde_mdp_parse_vbif_memtype(pdev, mdata);
+
sde_mdp_parse_rot_lut_setting(pdev, mdata);
sde_mdp_parse_inline_rot_lut_setting(pdev, mdata);
@@ -588,6 +674,17 @@
return 0;
}
+static void sde_mdp_destroy_dt_misc(struct platform_device *pdev,
+ struct sde_rot_data_type *mdata)
+{
+ kfree(mdata->vbif_memtype);
+ mdata->vbif_memtype = NULL;
+ kfree(mdata->vbif_rt_qos);
+ mdata->vbif_rt_qos = NULL;
+ kfree(mdata->vbif_nrt_qos);
+ mdata->vbif_nrt_qos = NULL;
+}
+
#define MDP_REG_BUS_VECTOR_ENTRY(ab_val, ib_val) \
{ \
.src = MSM_BUS_MASTER_AMPSS_M0, \
@@ -742,6 +839,7 @@
sde_rot_res = NULL;
sde_mdp_bus_scale_unregister(mdata);
+ sde_mdp_destroy_dt_misc(pdev, mdata);
sde_rot_iounmap(&mdata->vbif_nrt_io);
sde_rot_iounmap(&mdata->sde_io);
devm_kfree(&pdev->dev, mdata);
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.h
index 313c709..b1438d5 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.h
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.h
@@ -225,6 +225,9 @@
u32 *vbif_nrt_qos;
u32 npriority_lvl;
+ u32 vbif_memtype_count;
+ u32 *vbif_memtype;
+
int iommu_attached;
int iommu_ref_cnt;
@@ -271,6 +274,8 @@
void sde_mdp_set_ot_limit(struct sde_mdp_set_ot_params *params);
+int sde_mdp_init_vbif(void);
+
#define SDE_VBIF_WRITE(mdata, offset, value) \
(sde_reg_w(&mdata->vbif_nrt_io, offset, value, 0))
#define SDE_VBIF_READ(mdata, offset) \
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
index df2642c..9d10b06 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
@@ -341,6 +341,8 @@
if (!on) {
mgr->minimum_bw_vote = 0;
sde_rotator_update_perf(mgr);
+ } else {
+ sde_mdp_init_vbif();
}
mgr->regulator_enable = on;
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_hwio.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_hwio.h
index de448a4..5593919 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_hwio.h
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_hwio.h
@@ -65,6 +65,7 @@
#define MMSS_VBIF_NRT_VBIF_IN_WR_LIM_CONF2 0x00C8
#define MMSS_VBIF_NRT_VBIF_OUT_RD_LIM_CONF0 0x00D0
#define MMSS_VBIF_NRT_VBIF_OUT_WR_LIM_CONF0 0x00D4
+#define MMSS_VBIF_NRT_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x0160
#define MMSS_VBIF_NRT_VBIF_QOS_RP_REMAP_000 0x0550
#define MMSS_VBIF_NRT_VBIF_QOS_LVL_REMAP_000 0x0590
diff --git a/drivers/net/wireless/ath/wil6210/sysfs.c b/drivers/net/wireless/ath/wil6210/sysfs.c
index b4c4d09..b91bf51 100644
--- a/drivers/net/wireless/ath/wil6210/sysfs.c
+++ b/drivers/net/wireless/ath/wil6210/sysfs.c
@@ -291,6 +291,8 @@
return err;
}
+ kobject_uevent(&dev->kobj, KOBJ_CHANGE);
+
return 0;
}
@@ -299,4 +301,5 @@
struct device *dev = wil_to_dev(wil);
sysfs_remove_group(&dev->kobj, &wil6210_attribute_group);
+ kobject_uevent(&dev->kobj, KOBJ_CHANGE);
}
diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c
index 808391f..9f417bb 100644
--- a/drivers/platform/msm/ipa/ipa_api.c
+++ b/drivers/platform/msm/ipa/ipa_api.c
@@ -2971,6 +2971,25 @@
}
EXPORT_SYMBOL(ipa_get_pdev);
+int ipa_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data),
+ void *user_data)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_ntn_uc_reg_rdyCB,
+ ipauc_ready_cb, user_data);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_ntn_uc_reg_rdyCB);
+
+void ipa_ntn_uc_dereg_rdyCB(void)
+{
+ IPA_API_DISPATCH(ipa_ntn_uc_dereg_rdyCB);
+}
+EXPORT_SYMBOL(ipa_ntn_uc_dereg_rdyCB);
+
+
static const struct dev_pm_ops ipa_pm_ops = {
.suspend_noirq = ipa_ap_suspend,
.resume_noirq = ipa_ap_resume,
diff --git a/drivers/platform/msm/ipa/ipa_api.h b/drivers/platform/msm/ipa/ipa_api.h
index d3d4178..133e058 100644
--- a/drivers/platform/msm/ipa/ipa_api.h
+++ b/drivers/platform/msm/ipa/ipa_api.h
@@ -378,6 +378,11 @@
int ipa_ep_idx_dl);
struct device *(*ipa_get_pdev)(void);
+
+ int (*ipa_ntn_uc_reg_rdyCB)(void (*ipauc_ready_cb)(void *user_data),
+ void *user_data);
+
+ void (*ipa_ntn_uc_dereg_rdyCB)(void);
};
#ifdef CONFIG_IPA
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c b/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c
index 2dd82c1..a15a9d8 100644
--- a/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c
@@ -620,3 +620,41 @@
return ret;
}
EXPORT_SYMBOL(ipa_uc_offload_cleanup);
+
+/**
+ * ipa_uc_offload_uc_rdyCB() - To register uC ready CB if uC not
+ * ready
+ * @inout: [in/out] input/output parameters
+ * from/to client
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ */
+int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *inp)
+{
+ int ret = 0;
+
+ if (!inp) {
+ IPA_UC_OFFLOAD_ERR("Invalid input\n");
+ return -EINVAL;
+ }
+
+ if (inp->proto == IPA_UC_NTN)
+ ret = ipa_ntn_uc_reg_rdyCB(inp->notify, inp->priv);
+
+ if (ret == -EEXIST) {
+ inp->is_uC_ready = true;
+ ret = 0;
+ } else
+ inp->is_uC_ready = false;
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_uc_offload_reg_rdyCB);
+
+void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto)
+{
+ if (proto == IPA_UC_NTN)
+ ipa_ntn_uc_dereg_rdyCB();
+}
+EXPORT_SYMBOL(ipa_uc_offload_dereg_rdyCB);
diff --git a/drivers/platform/msm/ipa/ipa_common_i.h b/drivers/platform/msm/ipa/ipa_common_i.h
index 69c83d4..07bca0c 100644
--- a/drivers/platform/msm/ipa/ipa_common_i.h
+++ b/drivers/platform/msm/ipa/ipa_common_i.h
@@ -374,13 +374,15 @@
struct ipa_ntn_conn_out_params *outp);
int ipa_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
-
u8 *ipa_write_64(u64 w, u8 *dest);
u8 *ipa_write_32(u32 w, u8 *dest);
u8 *ipa_write_16(u16 hw, u8 *dest);
u8 *ipa_write_8(u8 b, u8 *dest);
u8 *ipa_pad_to_64(u8 *dest);
u8 *ipa_pad_to_32(u8 *dest);
+int ipa_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data),
+ void *user_data);
+void ipa_ntn_uc_dereg_rdyCB(void);
const char *ipa_get_version_string(enum ipa_hw_type ver);
#endif /* _IPA_COMMON_I_H_ */
diff --git a/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h b/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h
index ae6cfc4..0bc4b76 100644
--- a/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h
+++ b/drivers/platform/msm/ipa/ipa_uc_offload_common_i.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -21,4 +21,7 @@
struct ipa_ntn_conn_out_params *outp);
int ipa_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
+int ipa_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data),
+ void *user_data);
+void ipa_ntn_uc_dereg_rdyCB(void);
#endif /* _IPA_UC_OFFLOAD_COMMON_I_H_ */
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
index 877e4c7..0c2410f 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
@@ -1520,6 +1520,8 @@
ipa_notify_cb notify, void *priv, u8 hdr_len,
struct ipa_ntn_conn_out_params *outp);
int ipa2_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
+int ipa2_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv);
+void ipa2_ntn_uc_dereg_rdyCB(void);
/*
* To retrieve doorbell physical address of
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_ntn.c b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_ntn.c
index 6f59ebd..d4116eb 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_ntn.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_ntn.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -165,6 +165,17 @@
return -EEXIST;
}
+int ipa2_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv)
+{
+ return ipa2_register_ipa_ready_cb(ipauc_ready_cb, priv);
+}
+
+void ipa2_ntn_uc_dereg_rdyCB(void)
+{
+ ipa_ctx->uc_ntn_ctx.uc_ready_cb = NULL;
+ ipa_ctx->uc_ntn_ctx.priv = NULL;
+}
+
static void ipa_uc_ntn_loaded_handler(void)
{
if (!ipa_ctx) {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
index 4652fc8..b133f9c 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
@@ -5086,6 +5086,8 @@
api_ctrl->ipa_tear_down_uc_offload_pipes =
ipa2_tear_down_uc_offload_pipes;
api_ctrl->ipa_get_pdev = ipa2_get_pdev;
+ api_ctrl->ipa_ntn_uc_reg_rdyCB = ipa2_ntn_uc_reg_rdyCB;
+ api_ctrl->ipa_ntn_uc_dereg_rdyCB = ipa2_ntn_uc_dereg_rdyCB;
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
index ad3fe30..f172dc4 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
@@ -1257,8 +1257,6 @@
if (!ipa3_get_ntn_stats(&stats)) {
nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,
"TX num_pkts_processed=%u\n"
- "TX tail_ptr_val=%u\n"
- "TX num_db_fired=%u\n"
"TX ringFull=%u\n"
"TX ringEmpty=%u\n"
"TX ringUsageHigh=%u\n"
@@ -1270,27 +1268,25 @@
"TX bamFifoUsageLow=%u\n"
"TX bamUtilCount=%u\n"
"TX num_db=%u\n"
- "TX num_qmb_int_handled=%u\n",
+ "TX num_qmb_int_handled=%u\n"
+ "TX ipa_pipe_number=%u\n",
TX_STATS(num_pkts_processed),
- TX_STATS(tail_ptr_val),
- TX_STATS(num_db_fired),
- TX_STATS(tx_comp_ring_stats.ringFull),
- TX_STATS(tx_comp_ring_stats.ringEmpty),
- TX_STATS(tx_comp_ring_stats.ringUsageHigh),
- TX_STATS(tx_comp_ring_stats.ringUsageLow),
- TX_STATS(tx_comp_ring_stats.RingUtilCount),
- TX_STATS(bam_stats.bamFifoFull),
- TX_STATS(bam_stats.bamFifoEmpty),
- TX_STATS(bam_stats.bamFifoUsageHigh),
- TX_STATS(bam_stats.bamFifoUsageLow),
- TX_STATS(bam_stats.bamUtilCount),
+ TX_STATS(ring_stats.ringFull),
+ TX_STATS(ring_stats.ringEmpty),
+ TX_STATS(ring_stats.ringUsageHigh),
+ TX_STATS(ring_stats.ringUsageLow),
+ TX_STATS(ring_stats.RingUtilCount),
+ TX_STATS(gsi_stats.bamFifoFull),
+ TX_STATS(gsi_stats.bamFifoEmpty),
+ TX_STATS(gsi_stats.bamFifoUsageHigh),
+ TX_STATS(gsi_stats.bamFifoUsageLow),
+ TX_STATS(gsi_stats.bamUtilCount),
TX_STATS(num_db),
- TX_STATS(num_qmb_int_handled));
+ TX_STATS(num_qmb_int_handled),
+ TX_STATS(ipa_pipe_number));
cnt += nbytes;
nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt,
- "RX max_outstanding_pkts=%u\n"
"RX num_pkts_processed=%u\n"
- "RX rx_ring_rp_value=%u\n"
"RX ringFull=%u\n"
"RX ringEmpty=%u\n"
"RX ringUsageHigh=%u\n"
@@ -1301,21 +1297,23 @@
"RX bamFifoUsageHigh=%u\n"
"RX bamFifoUsageLow=%u\n"
"RX bamUtilCount=%u\n"
- "RX num_db=%u\n",
- RX_STATS(max_outstanding_pkts),
+ "RX num_db=%u\n"
+ "RX num_qmb_int_handled=%u\n"
+ "RX ipa_pipe_number=%u\n",
RX_STATS(num_pkts_processed),
- RX_STATS(rx_ring_rp_value),
- RX_STATS(rx_ind_ring_stats.ringFull),
- RX_STATS(rx_ind_ring_stats.ringEmpty),
- RX_STATS(rx_ind_ring_stats.ringUsageHigh),
- RX_STATS(rx_ind_ring_stats.ringUsageLow),
- RX_STATS(rx_ind_ring_stats.RingUtilCount),
- RX_STATS(bam_stats.bamFifoFull),
- RX_STATS(bam_stats.bamFifoEmpty),
- RX_STATS(bam_stats.bamFifoUsageHigh),
- RX_STATS(bam_stats.bamFifoUsageLow),
- RX_STATS(bam_stats.bamUtilCount),
- RX_STATS(num_db));
+ RX_STATS(ring_stats.ringFull),
+ RX_STATS(ring_stats.ringEmpty),
+ RX_STATS(ring_stats.ringUsageHigh),
+ RX_STATS(ring_stats.ringUsageLow),
+ RX_STATS(ring_stats.RingUtilCount),
+ RX_STATS(gsi_stats.bamFifoFull),
+ RX_STATS(gsi_stats.bamFifoEmpty),
+ RX_STATS(gsi_stats.bamFifoUsageHigh),
+ RX_STATS(gsi_stats.bamFifoUsageLow),
+ RX_STATS(gsi_stats.bamUtilCount),
+ RX_STATS(num_db),
+ RX_STATS(num_qmb_int_handled),
+ RX_STATS(ipa_pipe_number));
cnt += nbytes;
} else {
nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index f8e6fe6..1bed1c8 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -1679,6 +1679,8 @@
ipa_notify_cb notify, void *priv, u8 hdr_len,
struct ipa_ntn_conn_out_params *outp);
int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
+int ipa3_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv);
+void ipa3_ntn_uc_dereg_rdyCB(void);
/*
* To retrieve doorbell physical address of
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c
index ce47623..b6427d0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c
@@ -104,41 +104,83 @@
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
TX_STATS(num_pkts_processed);
- TX_STATS(tail_ptr_val);
- TX_STATS(num_db_fired);
- TX_STATS(tx_comp_ring_stats.ringFull);
- TX_STATS(tx_comp_ring_stats.ringEmpty);
- TX_STATS(tx_comp_ring_stats.ringUsageHigh);
- TX_STATS(tx_comp_ring_stats.ringUsageLow);
- TX_STATS(tx_comp_ring_stats.RingUtilCount);
- TX_STATS(bam_stats.bamFifoFull);
- TX_STATS(bam_stats.bamFifoEmpty);
- TX_STATS(bam_stats.bamFifoUsageHigh);
- TX_STATS(bam_stats.bamFifoUsageLow);
- TX_STATS(bam_stats.bamUtilCount);
+ TX_STATS(ring_stats.ringFull);
+ TX_STATS(ring_stats.ringEmpty);
+ TX_STATS(ring_stats.ringUsageHigh);
+ TX_STATS(ring_stats.ringUsageLow);
+ TX_STATS(ring_stats.RingUtilCount);
+ TX_STATS(gsi_stats.bamFifoFull);
+ TX_STATS(gsi_stats.bamFifoEmpty);
+ TX_STATS(gsi_stats.bamFifoUsageHigh);
+ TX_STATS(gsi_stats.bamFifoUsageLow);
+ TX_STATS(gsi_stats.bamUtilCount);
TX_STATS(num_db);
TX_STATS(num_qmb_int_handled);
+ TX_STATS(ipa_pipe_number);
- RX_STATS(max_outstanding_pkts);
RX_STATS(num_pkts_processed);
- RX_STATS(rx_ring_rp_value);
- RX_STATS(rx_ind_ring_stats.ringFull);
- RX_STATS(rx_ind_ring_stats.ringEmpty);
- RX_STATS(rx_ind_ring_stats.ringUsageHigh);
- RX_STATS(rx_ind_ring_stats.ringUsageLow);
- RX_STATS(rx_ind_ring_stats.RingUtilCount);
- RX_STATS(bam_stats.bamFifoFull);
- RX_STATS(bam_stats.bamFifoEmpty);
- RX_STATS(bam_stats.bamFifoUsageHigh);
- RX_STATS(bam_stats.bamFifoUsageLow);
- RX_STATS(bam_stats.bamUtilCount);
+ RX_STATS(ring_stats.ringFull);
+ RX_STATS(ring_stats.ringEmpty);
+ RX_STATS(ring_stats.ringUsageHigh);
+ RX_STATS(ring_stats.ringUsageLow);
+ RX_STATS(ring_stats.RingUtilCount);
+ RX_STATS(gsi_stats.bamFifoFull);
+ RX_STATS(gsi_stats.bamFifoEmpty);
+ RX_STATS(gsi_stats.bamFifoUsageHigh);
+ RX_STATS(gsi_stats.bamFifoUsageLow);
+ RX_STATS(gsi_stats.bamUtilCount);
RX_STATS(num_db);
+ RX_STATS(num_qmb_int_handled);
+ RX_STATS(ipa_pipe_number);
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
return 0;
}
+
+int ipa3_ntn_uc_reg_rdyCB(void (*ipa_ready_cb)(void *), void *user_data)
+{
+ int ret;
+
+ if (!ipa3_ctx) {
+ IPAERR("IPA ctx is null\n");
+ return -ENXIO;
+ }
+
+ ret = ipa3_uc_state_check();
+ if (ret) {
+ ipa3_ctx->uc_ntn_ctx.uc_ready_cb = ipa_ready_cb;
+ ipa3_ctx->uc_ntn_ctx.priv = user_data;
+ return 0;
+ }
+
+ return -EEXIST;
+}
+
+void ipa3_ntn_uc_dereg_rdyCB(void)
+{
+ ipa3_ctx->uc_ntn_ctx.uc_ready_cb = NULL;
+ ipa3_ctx->uc_ntn_ctx.priv = NULL;
+}
+
+static void ipa3_uc_ntn_loaded_handler(void)
+{
+ if (!ipa3_ctx) {
+ IPAERR("IPA ctx is null\n");
+ return;
+ }
+
+ if (ipa3_ctx->uc_ntn_ctx.uc_ready_cb) {
+ ipa3_ctx->uc_ntn_ctx.uc_ready_cb(
+ ipa3_ctx->uc_ntn_ctx.priv);
+
+ ipa3_ctx->uc_ntn_ctx.uc_ready_cb =
+ NULL;
+ ipa3_ctx->uc_ntn_ctx.priv = NULL;
+ }
+}
+
int ipa3_ntn_init(void)
{
struct ipa3_uc_hdlrs uc_ntn_cbs = { 0 };
@@ -146,6 +188,8 @@
uc_ntn_cbs.ipa_uc_event_hdlr = ipa3_uc_ntn_event_handler;
uc_ntn_cbs.ipa_uc_event_log_info_hdlr =
ipa3_uc_ntn_event_log_info_handler;
+ uc_ntn_cbs.ipa_uc_loaded_hdlr =
+ ipa3_uc_ntn_loaded_handler;
ipa3_uc_register_handlers(IPA_HW_FEATURE_NTN, &uc_ntn_cbs);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
index 79f0973..2e5a832 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
@@ -383,22 +383,21 @@
* struct NTN3RxInfoData_t - NTN Structure holding the Rx pipe
* information
*
- *@max_outstanding_pkts: Number of outstanding packets in Rx
- * Ring
*@num_pkts_processed: Number of packets processed - cumulative
- *@rx_ring_rp_value: Read pointer last advertized to the WLAN FW
*
- *@rx_ind_ring_stats:
- *@bam_stats:
+ *@ring_stats:
+ *@gsi_stats:
*@num_db: Number of times the doorbell was rung
+ *@num_qmb_int_handled: Number of QMB interrupts handled
+ *@ipa_pipe_number: The IPA Rx/Tx pipe number.
*/
struct NTN3RxInfoData_t {
- u32 max_outstanding_pkts;
u32 num_pkts_processed;
- u32 rx_ring_rp_value;
- struct IpaHwRingStats_t rx_ind_ring_stats;
- struct IpaHwBamStats_t bam_stats;
- u32 num_db;
+ struct IpaHwRingStats_t ring_stats;
+ struct IpaHwBamStats_t gsi_stats;
+ u32 num_db;
+ u32 num_qmb_int_handled;
+ u32 ipa_pipe_number;
} __packed;
@@ -417,12 +416,11 @@
*/
struct NTN3TxInfoData_t {
u32 num_pkts_processed;
- u32 tail_ptr_val;
- u32 num_db_fired;
- struct IpaHwRingStats_t tx_comp_ring_stats;
- struct IpaHwBamStats_t bam_stats;
- u32 num_db;
- u32 num_qmb_int_handled;
+ struct IpaHwRingStats_t ring_stats;
+ struct IpaHwBamStats_t gsi_stats;
+ u32 num_db;
+ u32 num_qmb_int_handled;
+ u32 ipa_pipe_number;
} __packed;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 4cebdaf..a251359 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -4474,6 +4474,8 @@
api_ctrl->ipa_tear_down_uc_offload_pipes =
ipa3_tear_down_uc_offload_pipes;
api_ctrl->ipa_get_pdev = ipa3_get_pdev;
+ api_ctrl->ipa_ntn_uc_reg_rdyCB = ipa3_ntn_uc_reg_rdyCB;
+ api_ctrl->ipa_ntn_uc_dereg_rdyCB = ipa3_ntn_uc_dereg_rdyCB;
return 0;
}
diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c
index a8dc044..a0982bc 100644
--- a/drivers/soc/qcom/icnss.c
+++ b/drivers/soc/qcom/icnss.c
@@ -3378,6 +3378,7 @@
struct dma_iommu_mapping *mapping;
int atomic_ctx = 1;
int s1_bypass = 1;
+ int fast = 1;
int ret = 0;
icnss_pr_dbg("Initializing SMMU\n");
@@ -3391,7 +3392,17 @@
goto map_fail;
}
- if (!priv->bypass_s1_smmu) {
+ if (priv->bypass_s1_smmu) {
+ ret = iommu_domain_set_attr(mapping->domain,
+ DOMAIN_ATTR_S1_BYPASS,
+ &s1_bypass);
+ if (ret < 0) {
+ icnss_pr_err("Set s1_bypass attribute failed, err = %d\n",
+ ret);
+ goto set_attr_fail;
+ }
+ icnss_pr_dbg("SMMU S1 BYPASS\n");
+ } else {
ret = iommu_domain_set_attr(mapping->domain,
DOMAIN_ATTR_ATOMIC,
&atomic_ctx);
@@ -3400,14 +3411,17 @@
ret);
goto set_attr_fail;
}
- }
+ icnss_pr_dbg("SMMU ATTR ATOMIC\n");
- ret = iommu_domain_set_attr(mapping->domain,
- DOMAIN_ATTR_S1_BYPASS,
- &s1_bypass);
- if (ret < 0) {
- icnss_pr_err("Set s1_bypass attribute failed, err = %d\n", ret);
- goto set_attr_fail;
+ ret = iommu_domain_set_attr(mapping->domain,
+ DOMAIN_ATTR_FAST,
+ &fast);
+ if (ret < 0) {
+ icnss_pr_err("Set fast map attribute failed, err = %d\n",
+ ret);
+ goto set_attr_fail;
+ }
+ icnss_pr_dbg("SMMU FAST map set\n");
}
ret = arm_iommu_attach_device(&priv->pdev->dev, mapping);
diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c
index d1cde1b..cc33b68 100644
--- a/drivers/tty/serial/msm_geni_serial.c
+++ b/drivers/tty/serial/msm_geni_serial.c
@@ -1886,7 +1886,8 @@
struct msm_geni_serial_port *port = platform_get_drvdata(pdev);
struct uart_port *uport = &port->uport;
- if (uart_console(uport)) {
+ if (uart_console(uport) &&
+ console_suspend_enabled && uport->suspended) {
se_geni_resources_on(&port->serial_rsc);
uart_resume_port((struct uart_driver *)uport->private_data,
uport);
diff --git a/include/linux/ipa_uc_offload.h b/include/linux/ipa_uc_offload.h
index 0277e87..85d0ce9 100644
--- a/include/linux/ipa_uc_offload.h
+++ b/include/linux/ipa_uc_offload.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -163,6 +163,20 @@
u32 max_supported_bw_mbps;
};
+/**
+ * struct ipa_uc_ready_params - uC ready CB parameters
+ * @is_uC_ready: uC loaded or not
+ * @priv : callback cookie
+ * @notify: callback
+ * @proto: uC offload protocol type
+ */
+struct ipa_uc_ready_params {
+ bool is_uC_ready;
+ void *priv;
+ ipa_uc_ready_cb notify;
+ enum ipa_uc_offload_proto proto;
+};
+
#if defined CONFIG_IPA || defined CONFIG_IPA3
/**
@@ -223,6 +237,19 @@
*/
int ipa_set_perf_profile(struct ipa_perf_profile *profile);
+
+/*
+ * To register uC ready callback if uC not ready
+ * and also check uC readiness
+ * if uC not ready only, register callback
+ */
+int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *param);
+
+/*
+ * To de-register uC ready callback
+ */
+void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto);
+
#else /* (CONFIG_IPA || CONFIG_IPA3) */
static inline int ipa_uc_offload_reg_intf(
@@ -254,6 +281,15 @@
return -EPERM;
}
+static inline int ipa_uc_offload_reg_rdyCB(struct ipa_uc_ready_params *param)
+{
+ return -EPERM;
+}
+
+static void ipa_uc_offload_dereg_rdyCB(enum ipa_uc_offload_proto proto)
+{
+}
+
#endif /* CONFIG_IPA3 */
#endif /* _IPA_UC_OFFLOAD_H_ */
diff --git a/include/linux/sde_rsc.h b/include/linux/sde_rsc.h
index 1450caa..0320210 100644
--- a/include/linux/sde_rsc.h
+++ b/include/linux/sde_rsc.h
@@ -114,15 +114,16 @@
*
* @fps: panel te interval
* @vtotal: current vertical total (height + vbp + vfp)
- * @jitter: panel can set the jitter to wake up rsc/solver early
- * This value causes mdp core to exit certain mode
- * early. Default is 10% jitter
+ * @jitter_numer: panel jitter numerator value. This config causes rsc/solver
+ * early before te. Default is 0.8% jitter.
+ * @jitter_denom: panel jitter denominator.
* @prefill_lines: max prefill lines based on panel
*/
struct sde_rsc_cmd_config {
u32 fps;
u32 vtotal;
- u32 jitter;
+ u32 jitter_numer;
+ u32 jitter_denom;
u32 prefill_lines;
};
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index db8d37f..e0ab4d6 100755
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -11119,6 +11119,7 @@
#if defined(CONFIG_SCHED_WALT)
+static DEFINE_RAW_SPINLOCK(migration_lock);
void check_for_migration(struct rq *rq, struct task_struct *p)
{
int new_cpu;
@@ -11130,6 +11131,7 @@
rq->curr->nr_cpus_allowed == 1)
return;
+ raw_spin_lock(&migration_lock);
rcu_read_lock();
new_cpu = energy_aware_wake_cpu(p, cpu, 0);
rcu_read_unlock();
@@ -11137,11 +11139,14 @@
active_balance = kick_active_balance(rq, p, new_cpu);
if (active_balance) {
mark_reserved(new_cpu);
+ raw_spin_unlock(&migration_lock);
stop_one_cpu_nowait(cpu,
active_load_balance_cpu_stop, rq,
&rq->active_balance_work);
+ return;
}
}
+ raw_spin_unlock(&migration_lock);
}
}
diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
index 6bd1508..19b89b1 100644
--- a/net/netfilter/nf_conntrack_core.c
+++ b/net/netfilter/nf_conntrack_core.c
@@ -1022,7 +1022,7 @@
static void conntrack_gc_work_init(struct conntrack_gc_work *gc_work)
{
- INIT_DELAYED_WORK(&gc_work->dwork, gc_worker);
+ INIT_DEFERRABLE_WORK(&gc_work->dwork, gc_worker);
gc_work->next_gc_run = HZ;
gc_work->exiting = false;
}