/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h>

&soc {
	/* USB port for DWC3 controller */
	usb: ssusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x0a600000 0xf8c00>;
		reg-names = "core_base";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <0 131 0>, <0 130 0>, <0 59 0>;
		interrupt-names = "hs_phy_irq", "pwr_event_irq", "ss_phy_irq";

		USB3_GDSC-supply = <&gdsc_usb30>;
		qcom,usb-dbm = <&dbm_1p5>;
		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
		qcom,num-gsi-evt-buffs = <0x3>;

		clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
			 <&clock_gcc GCC_SYS_NOC_USB3_CLK>,
			 <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,
			 <&clock_gcc GCC_USB30_SLEEP_CLK>,
			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>;

		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
				"cfg_ahb_clk", "xo";

		qcom,core-clk-rate = <133333333>;
		qcom,core-clk-rate-hs = <66666667>;

		resets = <&clock_gcc GCC_USB30_BCR>;
		reset-names = "core_reset";

		dwc3@a600000 {
			compatible = "snps,dwc3";
			reg = <0x0a600000 0xcd00>;
			interrupt-parent = <&intc>;
			interrupts = <0 133 0>;
			usb-phy = <&usb2_phy>, <&usb3_qmp_phy>;
			tx-fifo-resize;
			linux,sysdev_is_parent;
			snps,disable-clk-gating;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x10>;
		};
	};

	/* USB port for High Speed PHY */
	usb2_phy: hsphy@ff1000 {
		compatible = "qcom,usb-hsphy-snps-femto";
		reg = <0xff1000 0x400>;
		reg-names = "hsusb_phy_base";

		vdd-supply = <&pmxpoorwills_l4>;
		vdda18-supply = <&pmxpoorwills_l5>;
		vdda33-supply = <&pmxpoorwills_l10>;
		qcom,vdd-voltage-level = <0 872000 872000>;
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
		clock-names = "ref_clk_src", "cfg_ahb_clk";

		resets = <&clock_gcc GCC_QUSB2PHY_BCR>;
		reset-names = "phy_reset";
	};

	dbm_1p5: dbm@a6f8000 {
		compatible = "qcom,usb-dbm-1p5";
		reg = <0xa6f8000 0x400>;
		qcom,reset-ep-after-lpm-resume;
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	/* USB port for Super Speed PHY */
	usb3_qmp_phy: ssphy@ff0000 {
		compatible = "qcom,usb-ssphy-qmp-v2";
		reg = <0xff0000 0x1000>,
		    <0x01fcb244 0x4>;
		reg-names = "qmp_phy_base",
			"vls_clamp_reg";

		vdd-supply = <&pmxpoorwills_l4>;
		core-supply = <&pmxpoorwills_l1>;
		qcom,vdd-voltage-level = <0 872000 872000>;
		qcom,vbus-valid-override;
		qcom,qmp-phy-init-seq =
		/* <reg_offset, value, delay> */
			<0x058 0x07 0x00 /* QSERDES_COM_PLL_IVCO */
			 0x094 0x1a 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */
			 0x044 0x14 0x00 /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
			 0x154 0x31 0x00 /* QSERDES_COM_CLK_SELECT */
			 0x04c 0x02 0x00 /* QSERDES_COM_SYS_CLK_CTRL */
			 0x0a0 0x08 0x00 /* QSERDES_COM_RESETSM_CNTRL2 */
			 0x17c 0x06 0x00 /* QSERDES_COM_CMN_CONFIG */
			 0x184 0x05 0x00 /* QSERDES_COM_SVS_MODE_CLK_SEL */
			 0x1bc 0x11 0x00 /* QSERDES_COM_BIN_VCOCAL_HSCLK_SEL*/
			 0x158 0x01 0x00 /* QSERDES_COM_HSCLK_SEL */
			 0x0bc 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */
			 0x0cc 0xab 0x00 /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
			 0x0d0 0xea 0x00 /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
			 0x0d4 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */
			 0x1ac 0xca 0x00 /* COM_BIN_VCOCAL_CMP_CODE1_MODE0 */
			 0x1b0 0x1e 0x00 /* COM_BIN_VCOCAL_CMP_CODE2_MODE0 */
			 0x074 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */
			 0x07c 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */
			 0x084 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */
			 0x0f0 0x00 0x00 /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
			 0x0ec 0x3f 0x00 /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
			 0x114 0x02 0x00 /* QSERDES_COM_VCO_TUNE2_MODE0 */
			 0x110 0x24 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */
			 0x168 0x0a 0x00 /* QSERDES_COM_CORECLK_DIV_MODE0 */
			 0x0b0 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */
			 0x0ac 0x14 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */
			 0x0a4 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */
			 0x174 0x00 0x00 /* QSERDES_COM_CORE_CLK_EN */
			 0x0a8 0x00 0x00 /* QSERDES_COM_LOCK_CMP_CFG */
			 0x10c 0x00 0x00 /* QSERDES_COM_VCO_TUNE_MAP */
			 0x050 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */
			 0x00c 0x0a 0x00 /* QSERDES_COM_BG_TIMER */
			 0x010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */
			 0x01c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */
			 0x020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */
			 0x014 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER1 */
			 0x018 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER2 */
			 0x030 0xde 0x00 /* QSERDES_COM_SSC_STEP_SIZE1_MODE1 */
			 0x034 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2_MODE1 */
			 0x024 0xde 0x00 /* QSERDES_COM_SSC_STEP_SIZE1_MODE0 */
			 0x028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE1_MODE0 */
			 0x4a4 0x3f 0x00 /* QSERDES_RX_RX_IDAC_ENABLES */
			 0x594 0xbf 0x00 /* QSERDES_RX_RX_MODE_01_HIGH4 */
			 0x590 0x09 0x00 /* QSERDES_RX_RX_MODE_01_HIGH3 */
			 0x58c 0xc8 0x00 /* QSERDES_RX_RX_MODE_01_HIGH2 */
			 0x588 0xc8 0x00 /* QSERDES_RX_RX_MODE_01_HIGH */
			 0x584 0xe0 0x00 /* QSERDES_RX_RX_MODE_01_LOW */
			 0x444 0x01 0x00 /* QSERDES_RX_UCDR_PI_CONTROLS */
			 0x408 0x0a 0x00 /* QSERDES_RX_UCDR_FO_GAIN */
			 0x414 0x06 0x00 /* QSERDES_RX_UCDR_SO_GAIN */
			 0x430 0x2f 0x00 /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
			 0x43c 0xff 0x00 /* RX_UCDR_FASTLOCK_COUNT_LOW */
			 0x440 0x0f 0x00 /* RX_UCDR_FASTLOCK_COUNT_HIGH */
			 0x420 0x0a 0x00 /* QSERDES_RX_UCDR_SVS_FO_GAIN */
			 0x42c 0x06 0x00 /* QSERDES_RX_UCDR_SVS_SO_GAIN */
			 0x434 0x7f 0x00 /* RX_UCDR_SO_SATURATION_AND_ENABLE */
			 0x4d8 0x0c 0x00 /* QSERDES_RX_VGA_CAL_CNTRL2 */
			 0x4ec 0x0e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
			 0x4f0 0x4e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
			 0x4f4 0x18 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
			 0x5b4 0x04 0x00 /* QSERDES_RX_DFE_EN_TIMER */
			 0x510 0x77 0x00 /* RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
			 0x514 0x80 0x00 /* RX_RX_OFFSET_ADAPTOR_CNTRL2 */
			 0x51c 0x04 0x00 /* QSERDES_RX_SIGDET_CNTRL */
			 0x524 0x1a 0x00 /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
			 0x4fc 0x00 0x00 /* QSERDES_RX_RX_IDAC_TSETTLE_HIGH */
			 0x4f8 0xc0 0x00 /* QSERDES_RX_RX_IDAC_TSETTLE_LOW */
			 0x258 0x10 0x00 /* QSERDES_TX_HIGHZ_DRVR_EN */
			 0x29c 0x12 0x00 /* QSERDES_TX_RCV_DETECT_LVL_2 */
			 0x284 0x05 0x00 /* QSERDES_TX_LANE_MODE_1 */
			 0x288 0x02 0x00 /* QSERDES_TX_LANE_MODE_2 */
			 0x28c 0x00 0x00 /* QSERDES_TX_LANE_MODE_3*/
			 0x89c 0x83 0x00 /* USB3_UNI_PCS_FLL_CNTRL2 */
			 0x8a0 0x09 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_L */
			 0x8a4 0xa2 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
			 0x8a8 0x40 0x00 /* USB3_UNI_PCS_FLL_MAN_CODE */
			 0x898 0x02 0x00 /* USB3_UNI_PCS_FLL_CNTRL1 */
			 0x8c4 0xd0 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
			 0x8c8 0x17 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
			 0x8cc 0x20 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
			 0x890 0x4f 0x00 /* USB3_UNI_PCS_POWER_STATE_CONFIG1 */
			 0x990 0xe7 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
			 0x994 0x03 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
			 0x988 0xba 0x00 /* USB3_UNI_PCS_RX_SIGDET_LVL */
			 0xe2c 0x75 0x00 /* USB3_RXEQTRAINING_WAIT_TIME */
			 0xe38 0x07 0x00 /* USB3_RXEQTRAINING_DFE_TIME_S2 */
			 0xe18 0x64 0x00 /* USB3_LFPS_DET_HIGH_COUNT_VAL */
			 0x9c0 0x88 0x00 /* USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 */
			 0x9c4 0x13 0x00 /* USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 */
			 0x9dc 0x0d 0x00 /* USB3_UNI_PCS_EQ_CONFIG1 */
			 0x9e0 0x0d 0x00 /* USB3_UNI_PCS_EQ_CONFIG2 */
			 0x8dc 0x21 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
			 0x8e0 0x60 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
			 0xffffffff 0xffffffff 0x00>;

		qcom,qmp-phy-reg-offset =
				<0x814 /* USB3_UNI_PCS_PCS_STATUS */
				 0xe08 /* USB3_UNI_PCS_AUTONOMOUS_MODE_CTRL */
				 0xe14 /* USB3_UNI_PCS_LFPS_RXTERM_IRQ_CLEAR */
				 0x840 /* USB3_UNI_PCS_POWER_DOWN_CONTROL */
				 0x800 /* USB3_UNI_PCS_SW_RESET */
				 0x844>; /* USB3_UNI_PCS_START_CONTROL */

		clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,
			 <&clock_gcc GCC_USB3_PHY_PIPE_CLK>,
			 <&clock_rpmh RPMH_CXO_CLK>,
			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
				"cfg_ahb_clk";
		resets = <&clock_gcc GCC_USB3_PHY_BCR>,
		       <&clock_gcc GCC_USB3PHY_PHY_BCR>;
		reset-names = "phy_reset", "phy_phy_reset";
	};
};