| commit | e419990b5e811027b1552cbc5b76a6cc180f7f48 | [log] [tgz] |
|---|---|---|
| author | Seungwon Jeon <tgih.jun@samsung.com> | Tue May 22 13:01:21 2012 +0900 |
| committer | Chris Ball <cjb@laptop.org> | Wed Jun 06 09:38:51 2012 -0400 |
| tree | 12791ff201b9e56f74caaa86c22ce0964a8effcc | |
| parent | fda5f736864c46324dbc50246ef1ca0e84ebf4ae [diff] |
mmc: dw_mmc: correct the calculation for CLKDIV In case of "host->bus_hz < slot->clock", divider value is miscalculated. And clock divider register value is multiple of 2. If calculated divider value is odd number, result can be over-clocking. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Will Newton <will.newton@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>