clk: qcom: gcc-sdm845: Update the PCIe pipe clock structures
Clock clients would want to control the peripheral and core
memories of the PCIe pipe clocks on SDM845. Update the clock
structures for the same to allow doing so.
Change-Id: I67e0d053466d632cb369a52d541f2bc8a1a51cb8
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 25f9d62..894efd9 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1914,14 +1914,15 @@
},
};
-static struct clk_gate2 gcc_pcie_0_pipe_clk = {
- .udelay = 500,
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+ .halt_reg = 0x6b020,
+ .halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
- .ops = &clk_gate2_ops,
+ .ops = &clk_branch2_ops,
},
},
};
@@ -2013,14 +2014,15 @@
},
};
-static struct clk_gate2 gcc_pcie_1_pipe_clk = {
- .udelay = 500,
+static struct clk_branch gcc_pcie_1_pipe_clk = {
+ .halt_reg = 0x8d020,
+ .halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
- .ops = &clk_gate2_ops,
+ .ops = &clk_branch2_ops,
},
},
};