tree 8c293cf58ca0e05cc7ce78d9b47a3420c98c5ad5
parent c0452fb9fb8f49c7d68ab9fa0ad092016be7b45f
author John David Anglin <dave.anglin@bell.net> 1480036694 -0500
committer Helge Deller <deller@gmx.de> 1480073521 +0100

parisc: Also flush data TLB in flush_icache_page_asm

This is the second issue I noticed in reviewing the parisc TLB code.

The fic instruction may use either the instruction or data TLB in
flushing the instruction cache.  Thus, on machines with a split TLB, we
should also flush the data TLB after setting up the temporary alias
registers.

Although this has no functional impact, I changed the pdtlb and pitlb
instructions to consistently use the index register %r0.  These
instructions do not support integer displacements.

Tested on rp3440 and c8000.

Signed-off-by: John David Anglin  <dave.anglin@bell.net>
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Helge Deller <deller@gmx.de>