commit 50e6a2a74413806bd7fefb2a9aa4044aa49d3924
author Ben Widawsky <benjamin.widawsky@intel.com> Mon Mar 31 17:16:43 2014 -0700
committer Daniel Vetter <daniel.vetter@ffwll.ch> Tue Apr 01 22:58:28 2014 +0200
tree 6dc08b16c4cd00587b96b4c3dab5ad9ad2d0dbb7
parent 3280e8b08fd0647629530c27cd36b37982a3b597

drm/i915/bdw: RPS frequency bits are the same as HSW

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98abacd..cebe0d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3041,7 +3041,7 @@
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev))
+		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else