usb: dwc3: Add snapshot of DWC3 MSM drivers
This change adds dwc3-msm.c and required other QTI MSM
specific driver files. This snapshot is taken as of msm-4.4
commit <9d9cf7636c0d> ("Merge "clk: msm: clock-gpu-cobalt:
Update the GPU PLL FMAXes"").
Change-Id: I00149a0c56d0a5a00a6afe266b691dd9d0ffa992
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 0000000..2b2bfe4
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,108 @@
+MSM SuperSpeed USB3.0 SoC controller
+
+Required properties :
+- compatible : should be "qcom,dwc-usb3-msm"
+ - reg: Address and length of the register set for the device
+ Required regs are:
+ "core_base" : usb controller register set
+- interrupts: IRQ lines used by this controller
+- interrupt-names : Interrupt resource entries are :
+ "hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM.
+ "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM.
+ Used for SS-USB power events.
+ - clocks: a list of phandles to the controller clocks. Use as per
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+ property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk"
+ and "utmi_clk".
+
+Optional properties :
+- reg: Additional registers
+ "tcsr_base" : top-level CSR register to be written during power-on reset
+ initialize the internal MUX that controls whether to use USB3 controller
+ with primary port.
+ "ahb2phy_base" : top-level register to configure read/write wait cycle with
+ both QMP and QUSB PHY registers.
+- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
+ below optional properties:
+ - qcom,msm_bus,name
+ - qcom,msm_bus,num_cases
+ - qcom,msm_bus,num_paths
+ - qcom,msm_bus,vectors
+- interrupt-names : Optional interrupt resource entries are:
+ "pmic_id_irq" : Interrupt from PMIC for external ID pin notification.
+ "ss_phy_irq" : Interrupt from super speed phy for wake up notification.
+ - clocks: a list of phandles to the controller clocks. Use as per
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+ property. Optional clocks are "bus_aggr_clk" and "cfg_ahb_clk".
+- qcom,charging-disabled: If present then battery charging using USB
+ is disabled.
+- vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode.
+- USB3_GDSC-supply : phandle to the globally distributed switch controller
+ regulator node to the USB controller.
+- qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for
+ TX fifo allocation in bytes
+- qcom,usb-dbm : phandle for the DBM device
+- qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source
+ after USB is kept into LPM.
+- qcom,ext-hub-reset-gpio: This corresponds to gpio which is used for HUB reset.
+- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode.
+- qcom,disable-host-mode-pm: If present, it disables XHCI PM runtime functionality when USB
+ host mode is used.
+- extcon: phandles to external connector devices. First phandle should point to
+ external connector, which provide "USB" cable events, the second
+ should point to external connector device, which provide "USB-HOST"
+ cable events. A single phandle may be specified if a single connector
+ device provides both "USB" and "USB-HOST" events.
+
+Sub nodes:
+- Sub node for "DWC3- USB3 controller".
+ This sub node is required property for device node. The properties of this subnode
+ are specified in dwc3.txt.
+
+Example MSM USB3.0 controller device node :
+ usb@f9200000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0xf9200000 0xfc000>,
+ <0xfd4ab000 0x4>,
+ <0xf9b3e000 0x3ff>;
+ reg-names = "core_base",
+ "tcsr_base",
+ "ahb2phy_base",
+ interrupts = <0 133 0>;
+ interrupt-names = "hs_phy_irq";
+ vbus_dwc3-supply = <&pm8941_mvs1>;
+ USB3_GDSC-supply = <&gdsc_usb30>;
+ qcom,dwc-usb3-msm-dbm-eps = <4>
+ qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>;
+ qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
+ qcom,usb-dbm = <&dbm_1p4>;
+ qcom,lpm-to-suspend-delay-ms = <2>;
+
+ qcom,msm_bus,name = "usb3";
+ qcom,msm_bus,num_cases = <2>;
+ qcom,msm_bus,num_paths = <1>;
+ qcom,msm_bus,vectors =
+ <61 512 0 0>,
+ <61 512 240000000 960000000>;
+
+ clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
+ <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
+ <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,
+ <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
+ <&clock_gcc clk_gcc_usb30_sleep_clk>,
+ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
+ <&clock_gcc clk_cxo_dwc3_clk>;
+
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
+
+ dwc3@f9200000 {
+ compatible = "synopsys,dwc3";
+ reg = <0xf9200000 0xfc000>;
+ interrupts = <0 131 0>, <0 179 0>;
+ interrupt-names = "irq", "otg_irq";
+ tx-fifo-resize;
+ };
+ };