| commit | 51511d05defe92715c19c3e583c9d1ac1c82e1e6 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Thu Jul 30 18:47:07 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Aug 13 13:47:56 2015 +0200 |
| tree | ed99b1b09875c65286362cf4f55672a9cc6a22dd | |
| parent | 8044449556338fb27b1a03f6b1dbbdbc59e4ebfa [diff] |
drm/tegra: sor: Write correct head state registers The head state registers are per head, so they must be properly indexed. This has worked fine so far because all boards with eDP use it as the primary output, so it is very likely to end up attached to head 0. Signed-off-by: Thierry Reding <treding@nvidia.com>