| commit | 4ccc402ece35695dd2884ec0b652d52ae0230f13 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Fri Apr 04 15:55:15 2014 +0200 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Thu Apr 17 14:12:46 2014 +0300 |
| tree | e72273317bd892e4678ee6ccf776831e863554a1 | |
| parent | c61e4e75b95bda4c6fec134aa9f08b5629b532e6 [diff] |
clk: tegra: Fix enabling of PLLE When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com>