clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by
default.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 3d70634..143ce1f 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1254,8 +1254,11 @@
{csite, clk_max, 0, 1},
{emc, clk_max, 0, 1},
{cclk, clk_max, 0, 1},
- {uarta, pll_p, 0, 1},
- {uartd, pll_p, 0, 1},
+ {uarta, pll_p, 0, 0},
+ {uartb, pll_p, 0, 0},
+ {uartc, pll_p, 0, 0},
+ {uartd, pll_p, 0, 0},
+ {uarte, pll_p, 0, 0},
{usbd, clk_max, 12000000, 0},
{usb2, clk_max, 12000000, 0},
{usb3, clk_max, 12000000, 0},