tg3: Prevent a PCIe tx glitch
This patch prevents a PCIe tx glitch by allowing the transmitter to go
to a low power state.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 40501cb..530c36b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1953,10 +1953,34 @@
#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
+
/* Currently this is fixed. */
+#define TG3_PHY_PCIE_ADDR 0x00
#define TG3_PHY_MII_ADDR 0x01
-/* Tigon3 specific PHY MII registers. */
+
+/*** Tigon3 specific PHY PCIE registers. ***/
+
+#define TG3_PCIEPHY_BLOCK_ADDR 0x1f
+#define TG3_PCIEPHY_XGXS_BLK1 0x0801
+#define TG3_PCIEPHY_TXB_BLK 0x0861
+#define TG3_PCIEPHY_BLOCK_SHIFT 4
+
+/* TG3_PCIEPHY_TXB_BLK */
+#define TG3_PCIEPHY_TX0CTRL1 0x15
+#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
+#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
+#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
+#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
+#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
+
+/* TG3_PCIEPHY_XGXS_BLK1 */
+#define TG3_PCIEPHY_PWRMGMT4 0x1a
+#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
+#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
+
+
+/*** Tigon3 specific PHY MII registers. ***/
#define TG3_BMCR_SPEED1000 0x0040
#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */