Merge "iommu/arm-smmu: implement generic DT bindings" into msm-4.8
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index fcbae6a..2e5c1ee 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -56,6 +56,8 @@
layout using the generic DT graph presentation found in
"bindings/graph.txt".
+ * coresight-name: unique descriptive name of the component.
+
* Additional required properties for System Trace Macrocells (STM):
* reg: along with the physical base address and length of the register
set as described above, another entry is required to describe the
@@ -70,9 +72,21 @@
* compatible: Currently supported value is (note the absence of the
AMBA markee):
- "arm,coresight-replicator"
+ - "qcom,coresight-csr"
+ - "arm,coresight-cti"
+ - "qcom,coresight-tpda"
+ - "qcom,coresight-tpdm"
+ - "qcom,coresight-remote-etm"
+ - "qcom,coresight-hwevent"
+ - "qcom,coresight-dummy"
* port or ports: same as above.
+ * coresight-name: unique descriptive name of the component.
+
+* Optional properties for all components:
+ * reg-names: names corresponding to each reg property value.
+
* Optional properties for ETM/PTMs:
* arm,cp14: must be present if the system accesses ETM/PTM management
@@ -86,6 +100,48 @@
* arm,buffer-size: size of contiguous buffer space for TMC ETR
(embedded trace router)
+ * arm,default-sink: represents the default compile time CoreSight sink
+
+ * coresight-ctis: represents flush and reset CTIs for TMC buffer
+
+ * qcom,force-reg-dump: enables TMC reg dump support
+
+ * arm,sg-enable : indicates whether scatter gather feature is enabled
+ by default for TMC ETR configuration.
+
+* Required property for TPDAs:
+
+ * qcom,tpda-atid: must be present. Specifies the ATID for TPDA.
+
+* Optional properties for TPDAs:
+
+ * qcom,bc-elem-size: specifies the BC element size supported by each
+ monitor connected to the aggregator on each port. Should be specified
+ in pairs (port, bc element size).
+
+ * qcom,tc-elem-size: specifies the TC element size supported by each
+ monitor connected to the aggregator on each port. Should be specified
+ in pairs (port, tc element size).
+
+ * qcom,dsb-elem-size: specifies the DSB element size supported by each
+ monitor connected to the aggregator on each port. Should be specified
+ in pairs (port, dsb element size).
+
+ * qcom,cmb-elem-size: specifies the CMB element size supported by each
+ monitor connected to the aggregator on each port. Should be specified
+ in pairs (port, cmb element size).
+
+* Optional properties for TPDM:
+
+ * qcom,clk-enable: specifies whether additional clock bit needs to be
+ set for M4M TPDM.
+
+ * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed
+ after enabling the subunit.
+
+* Required property for Remote ETMs:
+
+ * qcom,inst-id: must be present. QMI instance id for remote ETMs.
Example:
@@ -202,6 +258,42 @@
};
};
+ tpda_mss: tpda@7043000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x7043000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-mss";
+
+ qcom,tpda-atid = <67>;
+ qcom,dsb-elem-size = <0 32>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_mss_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpda_mss>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tpda_mss_in_tpdm_mss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mss_out_tpda_mss>;
+ };
+ };
+ };
+ };
+
3. Sources
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -247,5 +339,36 @@
};
};
+ tpdm_mss: tpdm@7042000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7042000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mss";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_mss_out_tpda_mss: endpoint {
+ remote-endpoint = <&tpda_mss_in_tpdm_mss>;
+ };
+ };
+ };
+
+4. CTIs
+ cti0: cti@6010000 {
+ compatible = "arm,coresight-cti";
+ reg = <0x6010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&clock_gcc clk_qdss_clk>,
+ <&clock_gcc clk_qdss_a_clk>;
+ clock-names = "core_clk", "core_a_clk";
+ };
+
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.
diff --git a/arch/arm64/configs/msmskunk-perf_defconfig b/arch/arm64/configs/msmskunk-perf_defconfig
index 59b72ce..ece7fbb 100644
--- a/arch/arm64/configs/msmskunk-perf_defconfig
+++ b/arch/arm64/configs/msmskunk-perf_defconfig
@@ -339,6 +339,10 @@
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_QCOM_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
CONFIG_SECURITY=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SMACK=y
diff --git a/arch/arm64/configs/msmskunk_defconfig b/arch/arm64/configs/msmskunk_defconfig
index d4674e4..7683cda 100644
--- a/arch/arm64/configs/msmskunk_defconfig
+++ b/arch/arm64/configs/msmskunk_defconfig
@@ -387,6 +387,7 @@
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_QCOM_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
CONFIG_SECURITY=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SMACK=y
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index 26f7af31..19e001e 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -122,15 +122,62 @@
return clk_branch_toggle(hw, true, clk_branch_check_halt);
}
+static int clk_cbcr_set_flags(struct regmap *regmap, unsigned int reg,
+ unsigned long flags)
+{
+ u32 cbcr_val;
+
+ regmap_read(regmap, reg, &cbcr_val);
+
+ switch (flags) {
+ case CLKFLAG_PERIPH_OFF_SET:
+ cbcr_val |= BIT(12);
+ break;
+ case CLKFLAG_PERIPH_OFF_CLEAR:
+ cbcr_val &= ~BIT(12);
+ break;
+ case CLKFLAG_RETAIN_PERIPH:
+ cbcr_val |= BIT(13);
+ break;
+ case CLKFLAG_NORETAIN_PERIPH:
+ cbcr_val &= ~BIT(13);
+ break;
+ case CLKFLAG_RETAIN_MEM:
+ cbcr_val |= BIT(14);
+ break;
+ case CLKFLAG_NORETAIN_MEM:
+ cbcr_val &= ~BIT(14);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write(regmap, reg, cbcr_val);
+
+ /* Make sure power is enabled/disabled before returning. */
+ mb();
+ udelay(1);
+
+ return 0;
+}
+
static void clk_branch_disable(struct clk_hw *hw)
{
clk_branch_toggle(hw, false, clk_branch_check_halt);
}
+static int clk_branch_set_flags(struct clk_hw *hw, unsigned int flags)
+{
+ struct clk_branch *br = to_clk_branch(hw);
+
+ return clk_cbcr_set_flags(br->clkr.regmap, br->halt_reg, flags);
+}
+
const struct clk_ops clk_branch_ops = {
.enable = clk_branch_enable,
.disable = clk_branch_disable,
.is_enabled = clk_is_enabled_regmap,
+ .set_flags = clk_branch_set_flags,
};
EXPORT_SYMBOL_GPL(clk_branch_ops);
@@ -148,6 +195,7 @@
.enable = clk_branch2_enable,
.disable = clk_branch2_disable,
.is_enabled = clk_is_enabled_regmap,
+ .set_flags = clk_branch_set_flags,
};
EXPORT_SYMBOL_GPL(clk_branch2_ops);
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 284df3f..0a22c5d 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -53,4 +53,13 @@
#define to_clk_branch(_hw) \
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
+enum branch_mem_flags {
+ CLKFLAG_RETAIN_PERIPH,
+ CLKFLAG_NORETAIN_PERIPH,
+ CLKFLAG_RETAIN_MEM,
+ CLKFLAG_NORETAIN_MEM,
+ CLKFLAG_PERIPH_OFF_SET,
+ CLKFLAG_PERIPH_OFF_CLEAR,
+};
+
#endif
diff --git a/drivers/clk/qcom/clk-dummy.c b/drivers/clk/qcom/clk-dummy.c
index b7ca1d5..6334b10 100644
--- a/drivers/clk/qcom/clk-dummy.c
+++ b/drivers/clk/qcom/clk-dummy.c
@@ -55,10 +55,16 @@
return dummy->rrate;
}
+static int dummy_clk_set_flags(struct clk_hw *hw, unsigned int flags)
+{
+ return 0;
+}
+
struct clk_ops clk_dummy_ops = {
.set_rate = dummy_clk_set_rate,
.round_rate = dummy_clk_round_rate,
.recalc_rate = dummy_clk_recalc_rate,
+ .set_flags = dummy_clk_set_flags,
};
EXPORT_SYMBOL_GPL(clk_dummy_ops);
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 404bd0c..21f8abc 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -92,6 +92,7 @@
config CORESIGHT_OST
bool "CoreSight OST framework"
+ depends on CORESIGHT_STM
help
This enables support for OST packet in STM.
endif