| commit | 53a7d2d15ef45fb892defaf624ad6db7d528d8ac | [log] [tgz] |
|---|---|---|
| author | Patrik Jakobsson <patrik.r.jakobsson@gmail.com> | Wed Feb 13 22:20:21 2013 +0100 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Wed Feb 20 00:21:46 2013 +0100 |
| tree | 06e242f35812c3b00d5fbfa079f7343de57b0d4c | |
| parent | 876a8cdf92b23d268275cdce4397df0c37dac3fe [diff] |
drm/i915: Set i9xx lvds clock limits according to specifications The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>